OpenWrt – Blame information for rev 4

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4 office 1 From 667f0792b6f6d000c10f21c29c397c84cbe77f4a Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Wed, 17 Jan 2018 15:11:45 +0800
4 Subject: [PATCH 10/30] fsl-mc: layerscape support
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8  
9 This is an integrated patch for layerscape mc-bus support.
10  
11 Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
12 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
13 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
14 Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
15 Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
16 Signed-off-by: Shiva Kerdel <shiva@exdev.nl>
17 Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
18 Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
19 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
20 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
21 ---
22 drivers/staging/fsl-mc/bus/Kconfig | 41 +-
23 drivers/staging/fsl-mc/bus/Makefile | 10 +-
24 drivers/staging/fsl-mc/bus/dpbp-cmd.h | 80 ++
25 drivers/staging/fsl-mc/bus/dpbp.c | 450 +--------
26 drivers/staging/fsl-mc/bus/dpcon-cmd.h | 85 ++
27 drivers/staging/fsl-mc/bus/dpcon.c | 317 ++++++
28 drivers/staging/fsl-mc/bus/dpio/Makefile | 11 +
29 .../{include/dpcon-cmd.h => bus/dpio/dpio-cmd.h} | 73 +-
30 drivers/staging/fsl-mc/bus/dpio/dpio-driver.c | 296 ++++++
31 drivers/staging/fsl-mc/bus/dpio/dpio-service.c | 693 +++++++++++++
32 drivers/staging/fsl-mc/bus/dpio/dpio.c | 224 +++++
33 drivers/staging/fsl-mc/bus/dpio/dpio.h | 109 ++
34 drivers/staging/fsl-mc/bus/dpio/qbman-portal.c | 1049 ++++++++++++++++++++
35 drivers/staging/fsl-mc/bus/dpio/qbman-portal.h | 662 ++++++++++++
36 drivers/staging/fsl-mc/bus/dpio/qbman_debug.c | 853 ++++++++++++++++
37 drivers/staging/fsl-mc/bus/dpio/qbman_debug.h | 136 +++
38 drivers/staging/fsl-mc/bus/dpio/qbman_private.h | 171 ++++
39 drivers/staging/fsl-mc/bus/dpmcp-cmd.h | 112 +--
40 drivers/staging/fsl-mc/bus/dpmcp.c | 374 +------
41 drivers/staging/fsl-mc/bus/dpmcp.h | 127 +--
42 drivers/staging/fsl-mc/bus/dpmng-cmd.h | 14 +-
43 drivers/staging/fsl-mc/bus/dpmng.c | 37 +-
44 drivers/staging/fsl-mc/bus/dprc-cmd.h | 82 +-
45 drivers/staging/fsl-mc/bus/dprc-driver.c | 38 +-
46 drivers/staging/fsl-mc/bus/dprc.c | 629 +-----------
47 drivers/staging/fsl-mc/bus/fsl-mc-allocator.c | 78 +-
48 drivers/staging/fsl-mc/bus/fsl-mc-bus.c | 318 +++---
49 drivers/staging/fsl-mc/bus/fsl-mc-iommu.c | 104 ++
50 drivers/staging/fsl-mc/bus/fsl-mc-msi.c | 2 +-
51 drivers/staging/fsl-mc/bus/fsl-mc-private.h | 6 +-
52 .../staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c | 10 +-
53 drivers/staging/fsl-mc/bus/mc-io.c | 4 +-
54 drivers/staging/fsl-mc/bus/mc-ioctl.h | 22 +
55 drivers/staging/fsl-mc/bus/mc-restool.c | 405 ++++++++
56 drivers/staging/fsl-mc/bus/mc-sys.c | 14 +-
57 drivers/staging/fsl-mc/include/dpaa2-fd.h | 706 +++++++++++++
58 drivers/staging/fsl-mc/include/dpaa2-global.h | 202 ++++
59 drivers/staging/fsl-mc/include/dpaa2-io.h | 190 ++++
60 drivers/staging/fsl-mc/include/dpbp-cmd.h | 185 ----
61 drivers/staging/fsl-mc/include/dpbp.h | 158 +--
62 drivers/staging/fsl-mc/include/dpcon.h | 115 +++
63 drivers/staging/fsl-mc/include/dpmng.h | 16 +-
64 drivers/staging/fsl-mc/include/dpopr.h | 110 ++
65 drivers/staging/fsl-mc/include/dprc.h | 470 +++------
66 drivers/staging/fsl-mc/include/mc-bus.h | 7 +-
67 drivers/staging/fsl-mc/include/mc-cmd.h | 44 +-
68 drivers/staging/fsl-mc/include/mc-sys.h | 3 +-
69 drivers/staging/fsl-mc/include/mc.h | 17 +-
70 48 files changed, 7247 insertions(+), 2612 deletions(-)
71 create mode 100644 drivers/staging/fsl-mc/bus/dpbp-cmd.h
72 create mode 100644 drivers/staging/fsl-mc/bus/dpcon-cmd.h
73 create mode 100644 drivers/staging/fsl-mc/bus/dpcon.c
74 create mode 100644 drivers/staging/fsl-mc/bus/dpio/Makefile
75 rename drivers/staging/fsl-mc/{include/dpcon-cmd.h => bus/dpio/dpio-cmd.h} (64%)
76 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
77 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-service.c
78 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.c
79 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.h
80 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
81 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
82 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_debug.c
83 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_debug.h
84 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_private.h
85 create mode 100644 drivers/staging/fsl-mc/bus/fsl-mc-iommu.c
86 create mode 100644 drivers/staging/fsl-mc/bus/mc-ioctl.h
87 create mode 100644 drivers/staging/fsl-mc/bus/mc-restool.c
88 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-fd.h
89 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-global.h
90 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-io.h
91 delete mode 100644 drivers/staging/fsl-mc/include/dpbp-cmd.h
92 create mode 100644 drivers/staging/fsl-mc/include/dpcon.h
93 create mode 100644 drivers/staging/fsl-mc/include/dpopr.h
94  
95 --- a/drivers/staging/fsl-mc/bus/Kconfig
96 +++ b/drivers/staging/fsl-mc/bus/Kconfig
97 @@ -1,25 +1,40 @@
98 #
99 -# Freescale Management Complex (MC) bus drivers
100 +# DPAA2 fsl-mc bus
101 #
102 -# Copyright (C) 2014 Freescale Semiconductor, Inc.
103 +# Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
104 #
105 # This file is released under the GPLv2
106 #
107  
108 config FSL_MC_BUS
109 - bool "Freescale Management Complex (MC) bus driver"
110 - depends on OF && ARM64
111 + bool "QorIQ DPAA2 fsl-mc bus driver"
112 + depends on OF && ARCH_LAYERSCAPE
113 select GENERIC_MSI_IRQ_DOMAIN
114 help
115 - Driver to enable the bus infrastructure for the Freescale
116 - QorIQ Management Complex (fsl-mc). The fsl-mc is a hardware
117 - module of the QorIQ LS2 SoCs, that does resource management
118 - for hardware building-blocks in the SoC that can be used
119 - to dynamically create networking hardware objects such as
120 - network interfaces (NICs), crypto accelerator instances,
121 - or L2 switches.
122 + Driver to enable the bus infrastructure for the QorIQ DPAA2
123 + architecture. The fsl-mc bus driver handles discovery of
124 + DPAA2 objects (which are represented as Linux devices) and
125 + binding objects to drivers.
126  
127 - Only enable this option when building the kernel for
128 - Freescale QorQIQ LS2xxxx SoCs.
129 +config FSL_MC_DPIO
130 + tristate "QorIQ DPAA2 DPIO driver"
131 + depends on FSL_MC_BUS
132 + help
133 + Driver for the DPAA2 DPIO object. A DPIO provides queue and
134 + buffer management facilities for software to interact with
135 + other DPAA2 objects. This driver does not expose the DPIO
136 + objects individually, but groups them under a service layer
137 + API.
138  
139 +config FSL_QBMAN_DEBUG
140 + tristate "Freescale QBMAN Debug APIs"
141 + depends on FSL_MC_DPIO
142 + help
143 + QBMan debug assistant APIs.
144  
145 +config FSL_MC_RESTOOL
146 + tristate "Freescale Management Complex (MC) restool driver"
147 + depends on FSL_MC_BUS
148 + help
149 + Driver that provides kernel support for the Freescale Management
150 + Complex resource manager user-space tool.
151 --- a/drivers/staging/fsl-mc/bus/Makefile
152 +++ b/drivers/staging/fsl-mc/bus/Makefile
153 @@ -17,4 +17,12 @@ mc-bus-driver-objs := fsl-mc-bus.o \
154 fsl-mc-msi.o \
155 irq-gic-v3-its-fsl-mc-msi.o \
156 dpmcp.o \
157 - dpbp.o
158 + dpbp.o \
159 + dpcon.o \
160 + fsl-mc-iommu.o
161 +
162 +# MC DPIO driver
163 +obj-$(CONFIG_FSL_MC_DPIO) += dpio/
164 +
165 +# MC restool kernel support
166 +obj-$(CONFIG_FSL_MC_RESTOOL) += mc-restool.o
167 --- /dev/null
168 +++ b/drivers/staging/fsl-mc/bus/dpbp-cmd.h
169 @@ -0,0 +1,80 @@
170 +/*
171 + * Copyright 2013-2016 Freescale Semiconductor Inc.
172 + *
173 + * Redistribution and use in source and binary forms, with or without
174 + * modification, are permitted provided that the following conditions are met:
175 + * * Redistributions of source code must retain the above copyright
176 + * notice, this list of conditions and the following disclaimer.
177 + * * Redistributions in binary form must reproduce the above copyright
178 + * notice, this list of conditions and the following disclaimer in the
179 + * documentation and/or other materials provided with the distribution.
180 + * * Neither the name of the above-listed copyright holders nor the
181 + * names of any contributors may be used to endorse or promote products
182 + * derived from this software without specific prior written permission.
183 + *
184 + * ALTERNATIVELY, this software may be distributed under the terms of the
185 + * GNU General Public License ("GPL") as published by the Free Software
186 + * Foundation, either version 2 of that License or (at your option) any
187 + * later version.
188 + *
189 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
190 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
191 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
192 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
193 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
194 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
195 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
196 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
197 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
198 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
199 + * POSSIBILITY OF SUCH DAMAGE.
200 + */
201 +#ifndef _FSL_DPBP_CMD_H
202 +#define _FSL_DPBP_CMD_H
203 +
204 +/* DPBP Version */
205 +#define DPBP_VER_MAJOR 3
206 +#define DPBP_VER_MINOR 2
207 +
208 +/* Command versioning */
209 +#define DPBP_CMD_BASE_VERSION 1
210 +#define DPBP_CMD_ID_OFFSET 4
211 +
212 +#define DPBP_CMD(id) ((id << DPBP_CMD_ID_OFFSET) | DPBP_CMD_BASE_VERSION)
213 +
214 +/* Command IDs */
215 +#define DPBP_CMDID_CLOSE DPBP_CMD(0x800)
216 +#define DPBP_CMDID_OPEN DPBP_CMD(0x804)
217 +#define DPBP_CMDID_GET_API_VERSION DPBP_CMD(0xa04)
218 +
219 +#define DPBP_CMDID_ENABLE DPBP_CMD(0x002)
220 +#define DPBP_CMDID_DISABLE DPBP_CMD(0x003)
221 +#define DPBP_CMDID_GET_ATTR DPBP_CMD(0x004)
222 +#define DPBP_CMDID_RESET DPBP_CMD(0x005)
223 +#define DPBP_CMDID_IS_ENABLED DPBP_CMD(0x006)
224 +
225 +struct dpbp_cmd_open {
226 + __le32 dpbp_id;
227 +};
228 +
229 +struct dpbp_cmd_destroy {
230 + __le32 object_id;
231 +};
232 +
233 +#define DPBP_ENABLE 0x1
234 +
235 +struct dpbp_rsp_is_enabled {
236 + u8 enabled;
237 +};
238 +
239 +struct dpbp_rsp_get_attributes {
240 + /* response word 0 */
241 + __le16 pad;
242 + __le16 bpid;
243 + __le32 id;
244 + /* response word 1 */
245 + __le16 version_major;
246 + __le16 version_minor;
247 +};
248 +
249 +#endif /* _FSL_DPBP_CMD_H */
250 --- a/drivers/staging/fsl-mc/bus/dpbp.c
251 +++ b/drivers/staging/fsl-mc/bus/dpbp.c
252 @@ -1,4 +1,5 @@
253 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
254 +/*
255 + * Copyright 2013-2016 Freescale Semiconductor Inc.
256 *
257 * Redistribution and use in source and binary forms, with or without
258 * modification, are permitted provided that the following conditions are met:
259 @@ -11,7 +12,6 @@
260 * names of any contributors may be used to endorse or promote products
261 * derived from this software without specific prior written permission.
262 *
263 - *
264 * ALTERNATIVELY, this software may be distributed under the terms of the
265 * GNU General Public License ("GPL") as published by the Free Software
266 * Foundation, either version 2 of that License or (at your option) any
267 @@ -32,7 +32,8 @@
268 #include "../include/mc-sys.h"
269 #include "../include/mc-cmd.h"
270 #include "../include/dpbp.h"
271 -#include "../include/dpbp-cmd.h"
272 +
273 +#include "dpbp-cmd.h"
274  
275 /**
276 * dpbp_open() - Open a control session for the specified object.
277 @@ -105,74 +106,6 @@ int dpbp_close(struct fsl_mc_io *mc_io,
278 EXPORT_SYMBOL(dpbp_close);
279  
280 /**
281 - * dpbp_create() - Create the DPBP object.
282 - * @mc_io: Pointer to MC portal's I/O object
283 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
284 - * @cfg: Configuration structure
285 - * @token: Returned token; use in subsequent API calls
286 - *
287 - * Create the DPBP object, allocate required resources and
288 - * perform required initialization.
289 - *
290 - * The object can be created either by declaring it in the
291 - * DPL file, or by calling this function.
292 - * This function returns a unique authentication token,
293 - * associated with the specific object ID and the specific MC
294 - * portal; this token must be used in all subsequent calls to
295 - * this specific object. For objects that are created using the
296 - * DPL file, call dpbp_open function to get an authentication
297 - * token first.
298 - *
299 - * Return: '0' on Success; Error code otherwise.
300 - */
301 -int dpbp_create(struct fsl_mc_io *mc_io,
302 - u32 cmd_flags,
303 - const struct dpbp_cfg *cfg,
304 - u16 *token)
305 -{
306 - struct mc_command cmd = { 0 };
307 - int err;
308 -
309 - (void)(cfg); /* unused */
310 -
311 - /* prepare command */
312 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
313 - cmd_flags, 0);
314 -
315 - /* send command to mc*/
316 - err = mc_send_command(mc_io, &cmd);
317 - if (err)
318 - return err;
319 -
320 - /* retrieve response parameters */
321 - *token = mc_cmd_hdr_read_token(&cmd);
322 -
323 - return 0;
324 -}
325 -
326 -/**
327 - * dpbp_destroy() - Destroy the DPBP object and release all its resources.
328 - * @mc_io: Pointer to MC portal's I/O object
329 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
330 - * @token: Token of DPBP object
331 - *
332 - * Return: '0' on Success; error code otherwise.
333 - */
334 -int dpbp_destroy(struct fsl_mc_io *mc_io,
335 - u32 cmd_flags,
336 - u16 token)
337 -{
338 - struct mc_command cmd = { 0 };
339 -
340 - /* prepare command */
341 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
342 - cmd_flags, token);
343 -
344 - /* send command to mc*/
345 - return mc_send_command(mc_io, &cmd);
346 -}
347 -
348 -/**
349 * dpbp_enable() - Enable the DPBP.
350 * @mc_io: Pointer to MC portal's I/O object
351 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
352 @@ -250,6 +183,7 @@ int dpbp_is_enabled(struct fsl_mc_io *mc
353  
354 return 0;
355 }
356 +EXPORT_SYMBOL(dpbp_is_enabled);
357  
358 /**
359 * dpbp_reset() - Reset the DPBP, returns the object to initial state.
360 @@ -272,310 +206,7 @@ int dpbp_reset(struct fsl_mc_io *mc_io,
361 /* send command to mc*/
362 return mc_send_command(mc_io, &cmd);
363 }
364 -
365 -/**
366 - * dpbp_set_irq() - Set IRQ information for the DPBP to trigger an interrupt.
367 - * @mc_io: Pointer to MC portal's I/O object
368 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
369 - * @token: Token of DPBP object
370 - * @irq_index: Identifies the interrupt index to configure
371 - * @irq_cfg: IRQ configuration
372 - *
373 - * Return: '0' on Success; Error code otherwise.
374 - */
375 -int dpbp_set_irq(struct fsl_mc_io *mc_io,
376 - u32 cmd_flags,
377 - u16 token,
378 - u8 irq_index,
379 - struct dpbp_irq_cfg *irq_cfg)
380 -{
381 - struct mc_command cmd = { 0 };
382 - struct dpbp_cmd_set_irq *cmd_params;
383 -
384 - /* prepare command */
385 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ,
386 - cmd_flags, token);
387 - cmd_params = (struct dpbp_cmd_set_irq *)cmd.params;
388 - cmd_params->irq_index = irq_index;
389 - cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
390 - cmd_params->irq_addr = cpu_to_le64(irq_cfg->addr);
391 - cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
392 -
393 - /* send command to mc*/
394 - return mc_send_command(mc_io, &cmd);
395 -}
396 -
397 -/**
398 - * dpbp_get_irq() - Get IRQ information from the DPBP.
399 - * @mc_io: Pointer to MC portal's I/O object
400 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
401 - * @token: Token of DPBP object
402 - * @irq_index: The interrupt index to configure
403 - * @type: Interrupt type: 0 represents message interrupt
404 - * type (both irq_addr and irq_val are valid)
405 - * @irq_cfg: IRQ attributes
406 - *
407 - * Return: '0' on Success; Error code otherwise.
408 - */
409 -int dpbp_get_irq(struct fsl_mc_io *mc_io,
410 - u32 cmd_flags,
411 - u16 token,
412 - u8 irq_index,
413 - int *type,
414 - struct dpbp_irq_cfg *irq_cfg)
415 -{
416 - struct mc_command cmd = { 0 };
417 - struct dpbp_cmd_get_irq *cmd_params;
418 - struct dpbp_rsp_get_irq *rsp_params;
419 - int err;
420 -
421 - /* prepare command */
422 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ,
423 - cmd_flags, token);
424 - cmd_params = (struct dpbp_cmd_get_irq *)cmd.params;
425 - cmd_params->irq_index = irq_index;
426 -
427 - /* send command to mc*/
428 - err = mc_send_command(mc_io, &cmd);
429 - if (err)
430 - return err;
431 -
432 - /* retrieve response parameters */
433 - rsp_params = (struct dpbp_rsp_get_irq *)cmd.params;
434 - irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
435 - irq_cfg->addr = le64_to_cpu(rsp_params->irq_addr);
436 - irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
437 - *type = le32_to_cpu(rsp_params->type);
438 -
439 - return 0;
440 -}
441 -
442 -/**
443 - * dpbp_set_irq_enable() - Set overall interrupt state.
444 - * @mc_io: Pointer to MC portal's I/O object
445 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
446 - * @token: Token of DPBP object
447 - * @irq_index: The interrupt index to configure
448 - * @en: Interrupt state - enable = 1, disable = 0
449 - *
450 - * Allows GPP software to control when interrupts are generated.
451 - * Each interrupt can have up to 32 causes. The enable/disable control's the
452 - * overall interrupt state. if the interrupt is disabled no causes will cause
453 - * an interrupt.
454 - *
455 - * Return: '0' on Success; Error code otherwise.
456 - */
457 -int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
458 - u32 cmd_flags,
459 - u16 token,
460 - u8 irq_index,
461 - u8 en)
462 -{
463 - struct mc_command cmd = { 0 };
464 - struct dpbp_cmd_set_irq_enable *cmd_params;
465 -
466 - /* prepare command */
467 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_ENABLE,
468 - cmd_flags, token);
469 - cmd_params = (struct dpbp_cmd_set_irq_enable *)cmd.params;
470 - cmd_params->enable = en & DPBP_ENABLE;
471 - cmd_params->irq_index = irq_index;
472 -
473 - /* send command to mc*/
474 - return mc_send_command(mc_io, &cmd);
475 -}
476 -
477 -/**
478 - * dpbp_get_irq_enable() - Get overall interrupt state
479 - * @mc_io: Pointer to MC portal's I/O object
480 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
481 - * @token: Token of DPBP object
482 - * @irq_index: The interrupt index to configure
483 - * @en: Returned interrupt state - enable = 1, disable = 0
484 - *
485 - * Return: '0' on Success; Error code otherwise.
486 - */
487 -int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
488 - u32 cmd_flags,
489 - u16 token,
490 - u8 irq_index,
491 - u8 *en)
492 -{
493 - struct mc_command cmd = { 0 };
494 - struct dpbp_cmd_get_irq_enable *cmd_params;
495 - struct dpbp_rsp_get_irq_enable *rsp_params;
496 - int err;
497 -
498 - /* prepare command */
499 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_ENABLE,
500 - cmd_flags, token);
501 - cmd_params = (struct dpbp_cmd_get_irq_enable *)cmd.params;
502 - cmd_params->irq_index = irq_index;
503 -
504 - /* send command to mc*/
505 - err = mc_send_command(mc_io, &cmd);
506 - if (err)
507 - return err;
508 -
509 - /* retrieve response parameters */
510 - rsp_params = (struct dpbp_rsp_get_irq_enable *)cmd.params;
511 - *en = rsp_params->enabled & DPBP_ENABLE;
512 - return 0;
513 -}
514 -
515 -/**
516 - * dpbp_set_irq_mask() - Set interrupt mask.
517 - * @mc_io: Pointer to MC portal's I/O object
518 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
519 - * @token: Token of DPBP object
520 - * @irq_index: The interrupt index to configure
521 - * @mask: Event mask to trigger interrupt;
522 - * each bit:
523 - * 0 = ignore event
524 - * 1 = consider event for asserting IRQ
525 - *
526 - * Every interrupt can have up to 32 causes and the interrupt model supports
527 - * masking/unmasking each cause independently
528 - *
529 - * Return: '0' on Success; Error code otherwise.
530 - */
531 -int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
532 - u32 cmd_flags,
533 - u16 token,
534 - u8 irq_index,
535 - u32 mask)
536 -{
537 - struct mc_command cmd = { 0 };
538 - struct dpbp_cmd_set_irq_mask *cmd_params;
539 -
540 - /* prepare command */
541 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_MASK,
542 - cmd_flags, token);
543 - cmd_params = (struct dpbp_cmd_set_irq_mask *)cmd.params;
544 - cmd_params->mask = cpu_to_le32(mask);
545 - cmd_params->irq_index = irq_index;
546 -
547 - /* send command to mc*/
548 - return mc_send_command(mc_io, &cmd);
549 -}
550 -
551 -/**
552 - * dpbp_get_irq_mask() - Get interrupt mask.
553 - * @mc_io: Pointer to MC portal's I/O object
554 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
555 - * @token: Token of DPBP object
556 - * @irq_index: The interrupt index to configure
557 - * @mask: Returned event mask to trigger interrupt
558 - *
559 - * Every interrupt can have up to 32 causes and the interrupt model supports
560 - * masking/unmasking each cause independently
561 - *
562 - * Return: '0' on Success; Error code otherwise.
563 - */
564 -int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
565 - u32 cmd_flags,
566 - u16 token,
567 - u8 irq_index,
568 - u32 *mask)
569 -{
570 - struct mc_command cmd = { 0 };
571 - struct dpbp_cmd_get_irq_mask *cmd_params;
572 - struct dpbp_rsp_get_irq_mask *rsp_params;
573 - int err;
574 -
575 - /* prepare command */
576 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_MASK,
577 - cmd_flags, token);
578 - cmd_params = (struct dpbp_cmd_get_irq_mask *)cmd.params;
579 - cmd_params->irq_index = irq_index;
580 -
581 - /* send command to mc*/
582 - err = mc_send_command(mc_io, &cmd);
583 - if (err)
584 - return err;
585 -
586 - /* retrieve response parameters */
587 - rsp_params = (struct dpbp_rsp_get_irq_mask *)cmd.params;
588 - *mask = le32_to_cpu(rsp_params->mask);
589 -
590 - return 0;
591 -}
592 -
593 -/**
594 - * dpbp_get_irq_status() - Get the current status of any pending interrupts.
595 - *
596 - * @mc_io: Pointer to MC portal's I/O object
597 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
598 - * @token: Token of DPBP object
599 - * @irq_index: The interrupt index to configure
600 - * @status: Returned interrupts status - one bit per cause:
601 - * 0 = no interrupt pending
602 - * 1 = interrupt pending
603 - *
604 - * Return: '0' on Success; Error code otherwise.
605 - */
606 -int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
607 - u32 cmd_flags,
608 - u16 token,
609 - u8 irq_index,
610 - u32 *status)
611 -{
612 - struct mc_command cmd = { 0 };
613 - struct dpbp_cmd_get_irq_status *cmd_params;
614 - struct dpbp_rsp_get_irq_status *rsp_params;
615 - int err;
616 -
617 - /* prepare command */
618 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_STATUS,
619 - cmd_flags, token);
620 - cmd_params = (struct dpbp_cmd_get_irq_status *)cmd.params;
621 - cmd_params->status = cpu_to_le32(*status);
622 - cmd_params->irq_index = irq_index;
623 -
624 - /* send command to mc*/
625 - err = mc_send_command(mc_io, &cmd);
626 - if (err)
627 - return err;
628 -
629 - /* retrieve response parameters */
630 - rsp_params = (struct dpbp_rsp_get_irq_status *)cmd.params;
631 - *status = le32_to_cpu(rsp_params->status);
632 -
633 - return 0;
634 -}
635 -
636 -/**
637 - * dpbp_clear_irq_status() - Clear a pending interrupt's status
638 - *
639 - * @mc_io: Pointer to MC portal's I/O object
640 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
641 - * @token: Token of DPBP object
642 - * @irq_index: The interrupt index to configure
643 - * @status: Bits to clear (W1C) - one bit per cause:
644 - * 0 = don't change
645 - * 1 = clear status bit
646 - *
647 - * Return: '0' on Success; Error code otherwise.
648 - */
649 -int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
650 - u32 cmd_flags,
651 - u16 token,
652 - u8 irq_index,
653 - u32 status)
654 -{
655 - struct mc_command cmd = { 0 };
656 - struct dpbp_cmd_clear_irq_status *cmd_params;
657 -
658 - /* prepare command */
659 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLEAR_IRQ_STATUS,
660 - cmd_flags, token);
661 - cmd_params = (struct dpbp_cmd_clear_irq_status *)cmd.params;
662 - cmd_params->status = cpu_to_le32(status);
663 - cmd_params->irq_index = irq_index;
664 -
665 - /* send command to mc*/
666 - return mc_send_command(mc_io, &cmd);
667 -}
668 +EXPORT_SYMBOL(dpbp_reset);
669  
670 /**
671 * dpbp_get_attributes - Retrieve DPBP attributes.
672 @@ -609,83 +240,40 @@ int dpbp_get_attributes(struct fsl_mc_io
673 rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params;
674 attr->bpid = le16_to_cpu(rsp_params->bpid);
675 attr->id = le32_to_cpu(rsp_params->id);
676 - attr->version.major = le16_to_cpu(rsp_params->version_major);
677 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
678  
679 return 0;
680 }
681 EXPORT_SYMBOL(dpbp_get_attributes);
682  
683 /**
684 - * dpbp_set_notifications() - Set notifications towards software
685 - * @mc_io: Pointer to MC portal's I/O object
686 + * dpbp_get_api_version - Get Data Path Buffer Pool API version
687 + * @mc_io: Pointer to Mc portal's I/O object
688 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
689 - * @token: Token of DPBP object
690 - * @cfg: notifications configuration
691 + * @major_ver: Major version of Buffer Pool API
692 + * @minor_ver: Minor version of Buffer Pool API
693 *
694 * Return: '0' on Success; Error code otherwise.
695 */
696 -int dpbp_set_notifications(struct fsl_mc_io *mc_io,
697 - u32 cmd_flags,
698 - u16 token,
699 - struct dpbp_notification_cfg *cfg)
700 +int dpbp_get_api_version(struct fsl_mc_io *mc_io,
701 + u32 cmd_flags,
702 + u16 *major_ver,
703 + u16 *minor_ver)
704 {
705 struct mc_command cmd = { 0 };
706 - struct dpbp_cmd_set_notifications *cmd_params;
707 -
708 - /* prepare command */
709 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_NOTIFICATIONS,
710 - cmd_flags, token);
711 - cmd_params = (struct dpbp_cmd_set_notifications *)cmd.params;
712 - cmd_params->depletion_entry = cpu_to_le32(cfg->depletion_entry);
713 - cmd_params->depletion_exit = cpu_to_le32(cfg->depletion_exit);
714 - cmd_params->surplus_entry = cpu_to_le32(cfg->surplus_entry);
715 - cmd_params->surplus_exit = cpu_to_le32(cfg->surplus_exit);
716 - cmd_params->options = cpu_to_le16(cfg->options);
717 - cmd_params->message_ctx = cpu_to_le64(cfg->message_ctx);
718 - cmd_params->message_iova = cpu_to_le64(cfg->message_iova);
719 -
720 - /* send command to mc*/
721 - return mc_send_command(mc_io, &cmd);
722 -}
723 -
724 -/**
725 - * dpbp_get_notifications() - Get the notifications configuration
726 - * @mc_io: Pointer to MC portal's I/O object
727 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
728 - * @token: Token of DPBP object
729 - * @cfg: notifications configuration
730 - *
731 - * Return: '0' on Success; Error code otherwise.
732 - */
733 -int dpbp_get_notifications(struct fsl_mc_io *mc_io,
734 - u32 cmd_flags,
735 - u16 token,
736 - struct dpbp_notification_cfg *cfg)
737 -{
738 - struct mc_command cmd = { 0 };
739 - struct dpbp_rsp_get_notifications *rsp_params;
740 int err;
741  
742 /* prepare command */
743 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_NOTIFICATIONS,
744 - cmd_flags,
745 - token);
746 + cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_API_VERSION,
747 + cmd_flags, 0);
748  
749 - /* send command to mc*/
750 + /* send command to mc */
751 err = mc_send_command(mc_io, &cmd);
752 if (err)
753 return err;
754  
755 /* retrieve response parameters */
756 - rsp_params = (struct dpbp_rsp_get_notifications *)cmd.params;
757 - cfg->depletion_entry = le32_to_cpu(rsp_params->depletion_entry);
758 - cfg->depletion_exit = le32_to_cpu(rsp_params->depletion_exit);
759 - cfg->surplus_entry = le32_to_cpu(rsp_params->surplus_entry);
760 - cfg->surplus_exit = le32_to_cpu(rsp_params->surplus_exit);
761 - cfg->options = le16_to_cpu(rsp_params->options);
762 - cfg->message_ctx = le64_to_cpu(rsp_params->message_ctx);
763 - cfg->message_iova = le64_to_cpu(rsp_params->message_iova);
764 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
765  
766 return 0;
767 }
768 +EXPORT_SYMBOL(dpbp_get_api_version);
769 --- /dev/null
770 +++ b/drivers/staging/fsl-mc/bus/dpcon-cmd.h
771 @@ -0,0 +1,85 @@
772 +/*
773 + * Copyright 2013-2016 Freescale Semiconductor Inc.
774 + *
775 + * Redistribution and use in source and binary forms, with or without
776 + * modification, are permitted provided that the following conditions are met:
777 + * * Redistributions of source code must retain the above copyright
778 + * notice, this list of conditions and the following disclaimer.
779 + * * Redistributions in binary form must reproduce the above copyright
780 + * notice, this list of conditions and the following disclaimer in the
781 + * documentation and/or other materials provided with the distribution.
782 + * * Neither the name of the above-listed copyright holders nor the
783 + * names of any contributors may be used to endorse or promote products
784 + * derived from this software without specific prior written permission.
785 + *
786 + * ALTERNATIVELY, this software may be distributed under the terms of the
787 + * GNU General Public License ("GPL") as published by the Free Software
788 + * Foundation, either version 2 of that License or (at your option) any
789 + * later version.
790 + *
791 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
792 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
793 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
794 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
795 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
796 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
797 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
798 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
799 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
800 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
801 + * POSSIBILITY OF SUCH DAMAGE.
802 + */
803 +#ifndef _FSL_DPCON_CMD_H
804 +#define _FSL_DPCON_CMD_H
805 +
806 +/* DPCON Version */
807 +#define DPCON_VER_MAJOR 3
808 +#define DPCON_VER_MINOR 2
809 +
810 +/* Command versioning */
811 +#define DPCON_CMD_BASE_VERSION 1
812 +#define DPCON_CMD_ID_OFFSET 4
813 +
814 +#define DPCON_CMD(id) (((id) << DPCON_CMD_ID_OFFSET) | DPCON_CMD_BASE_VERSION)
815 +
816 +/* Command IDs */
817 +#define DPCON_CMDID_CLOSE DPCON_CMD(0x800)
818 +#define DPCON_CMDID_OPEN DPCON_CMD(0x808)
819 +#define DPCON_CMDID_GET_API_VERSION DPCON_CMD(0xa08)
820 +
821 +#define DPCON_CMDID_ENABLE DPCON_CMD(0x002)
822 +#define DPCON_CMDID_DISABLE DPCON_CMD(0x003)
823 +#define DPCON_CMDID_GET_ATTR DPCON_CMD(0x004)
824 +#define DPCON_CMDID_RESET DPCON_CMD(0x005)
825 +#define DPCON_CMDID_IS_ENABLED DPCON_CMD(0x006)
826 +
827 +#define DPCON_CMDID_SET_NOTIFICATION DPCON_CMD(0x100)
828 +
829 +struct dpcon_cmd_open {
830 + __le32 dpcon_id;
831 +};
832 +
833 +#define DPCON_ENABLE 1
834 +
835 +struct dpcon_rsp_is_enabled {
836 + u8 enabled;
837 +};
838 +
839 +struct dpcon_rsp_get_attr {
840 + /* response word 0 */
841 + __le32 id;
842 + __le16 qbman_ch_id;
843 + u8 num_priorities;
844 + u8 pad;
845 +};
846 +
847 +struct dpcon_cmd_set_notification {
848 + /* cmd word 0 */
849 + __le32 dpio_id;
850 + u8 priority;
851 + u8 pad[3];
852 + /* cmd word 1 */
853 + __le64 user_ctx;
854 +};
855 +
856 +#endif /* _FSL_DPCON_CMD_H */
857 --- /dev/null
858 +++ b/drivers/staging/fsl-mc/bus/dpcon.c
859 @@ -0,0 +1,317 @@
860 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
861 + *
862 + * Redistribution and use in source and binary forms, with or without
863 + * modification, are permitted provided that the following conditions are met:
864 + * * Redistributions of source code must retain the above copyright
865 + * notice, this list of conditions and the following disclaimer.
866 + * * Redistributions in binary form must reproduce the above copyright
867 + * notice, this list of conditions and the following disclaimer in the
868 + * documentation and/or other materials provided with the distribution.
869 + * * Neither the name of the above-listed copyright holders nor the
870 + * names of any contributors may be used to endorse or promote products
871 + * derived from this software without specific prior written permission.
872 + *
873 + *
874 + * ALTERNATIVELY, this software may be distributed under the terms of the
875 + * GNU General Public License ("GPL") as published by the Free Software
876 + * Foundation, either version 2 of that License or (at your option) any
877 + * later version.
878 + *
879 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
880 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
881 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
882 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
883 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
884 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
885 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
886 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
887 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
888 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
889 + * POSSIBILITY OF SUCH DAMAGE.
890 + */
891 +#include "../include/mc-sys.h"
892 +#include "../include/mc-cmd.h"
893 +#include "../include/dpcon.h"
894 +
895 +#include "dpcon-cmd.h"
896 +
897 +/**
898 + * dpcon_open() - Open a control session for the specified object
899 + * @mc_io: Pointer to MC portal's I/O object
900 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
901 + * @dpcon_id: DPCON unique ID
902 + * @token: Returned token; use in subsequent API calls
903 + *
904 + * This function can be used to open a control session for an
905 + * already created object; an object may have been declared in
906 + * the DPL or by calling the dpcon_create() function.
907 + * This function returns a unique authentication token,
908 + * associated with the specific object ID and the specific MC
909 + * portal; this token must be used in all subsequent commands for
910 + * this specific object.
911 + *
912 + * Return: '0' on Success; Error code otherwise.
913 + */
914 +int dpcon_open(struct fsl_mc_io *mc_io,
915 + u32 cmd_flags,
916 + int dpcon_id,
917 + u16 *token)
918 +{
919 + struct mc_command cmd = { 0 };
920 + struct dpcon_cmd_open *dpcon_cmd;
921 + int err;
922 +
923 + /* prepare command */
924 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_OPEN,
925 + cmd_flags,
926 + 0);
927 + dpcon_cmd = (struct dpcon_cmd_open *)cmd.params;
928 + dpcon_cmd->dpcon_id = cpu_to_le32(dpcon_id);
929 +
930 + /* send command to mc*/
931 + err = mc_send_command(mc_io, &cmd);
932 + if (err)
933 + return err;
934 +
935 + /* retrieve response parameters */
936 + *token = mc_cmd_hdr_read_token(&cmd);
937 +
938 + return 0;
939 +}
940 +EXPORT_SYMBOL(dpcon_open);
941 +
942 +/**
943 + * dpcon_close() - Close the control session of the object
944 + * @mc_io: Pointer to MC portal's I/O object
945 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
946 + * @token: Token of DPCON object
947 + *
948 + * After this function is called, no further operations are
949 + * allowed on the object without opening a new control session.
950 + *
951 + * Return: '0' on Success; Error code otherwise.
952 + */
953 +int dpcon_close(struct fsl_mc_io *mc_io,
954 + u32 cmd_flags,
955 + u16 token)
956 +{
957 + struct mc_command cmd = { 0 };
958 +
959 + /* prepare command */
960 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE,
961 + cmd_flags,
962 + token);
963 +
964 + /* send command to mc*/
965 + return mc_send_command(mc_io, &cmd);
966 +}
967 +EXPORT_SYMBOL(dpcon_close);
968 +
969 +/**
970 + * dpcon_enable() - Enable the DPCON
971 + * @mc_io: Pointer to MC portal's I/O object
972 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
973 + * @token: Token of DPCON object
974 + *
975 + * Return: '0' on Success; Error code otherwise
976 + */
977 +int dpcon_enable(struct fsl_mc_io *mc_io,
978 + u32 cmd_flags,
979 + u16 token)
980 +{
981 + struct mc_command cmd = { 0 };
982 +
983 + /* prepare command */
984 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE,
985 + cmd_flags,
986 + token);
987 +
988 + /* send command to mc*/
989 + return mc_send_command(mc_io, &cmd);
990 +}
991 +EXPORT_SYMBOL(dpcon_enable);
992 +
993 +/**
994 + * dpcon_disable() - Disable the DPCON
995 + * @mc_io: Pointer to MC portal's I/O object
996 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
997 + * @token: Token of DPCON object
998 + *
999 + * Return: '0' on Success; Error code otherwise
1000 + */
1001 +int dpcon_disable(struct fsl_mc_io *mc_io,
1002 + u32 cmd_flags,
1003 + u16 token)
1004 +{
1005 + struct mc_command cmd = { 0 };
1006 +
1007 + /* prepare command */
1008 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE,
1009 + cmd_flags,
1010 + token);
1011 +
1012 + /* send command to mc*/
1013 + return mc_send_command(mc_io, &cmd);
1014 +}
1015 +EXPORT_SYMBOL(dpcon_disable);
1016 +
1017 +/**
1018 + * dpcon_is_enabled() - Check if the DPCON is enabled.
1019 + * @mc_io: Pointer to MC portal's I/O object
1020 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1021 + * @token: Token of DPCON object
1022 + * @en: Returns '1' if object is enabled; '0' otherwise
1023 + *
1024 + * Return: '0' on Success; Error code otherwise.
1025 + */
1026 +int dpcon_is_enabled(struct fsl_mc_io *mc_io,
1027 + u32 cmd_flags,
1028 + u16 token,
1029 + int *en)
1030 +{
1031 + struct mc_command cmd = { 0 };
1032 + struct dpcon_rsp_is_enabled *dpcon_rsp;
1033 + int err;
1034 +
1035 + /* prepare command */
1036 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_IS_ENABLED,
1037 + cmd_flags,
1038 + token);
1039 +
1040 + /* send command to mc*/
1041 + err = mc_send_command(mc_io, &cmd);
1042 + if (err)
1043 + return err;
1044 +
1045 + /* retrieve response parameters */
1046 + dpcon_rsp = (struct dpcon_rsp_is_enabled *)cmd.params;
1047 + *en = dpcon_rsp->enabled & DPCON_ENABLE;
1048 +
1049 + return 0;
1050 +}
1051 +EXPORT_SYMBOL(dpcon_is_enabled);
1052 +
1053 +/**
1054 + * dpcon_reset() - Reset the DPCON, returns the object to initial state.
1055 + * @mc_io: Pointer to MC portal's I/O object
1056 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1057 + * @token: Token of DPCON object
1058 + *
1059 + * Return: '0' on Success; Error code otherwise.
1060 + */
1061 +int dpcon_reset(struct fsl_mc_io *mc_io,
1062 + u32 cmd_flags,
1063 + u16 token)
1064 +{
1065 + struct mc_command cmd = { 0 };
1066 +
1067 + /* prepare command */
1068 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET,
1069 + cmd_flags, token);
1070 +
1071 + /* send command to mc*/
1072 + return mc_send_command(mc_io, &cmd);
1073 +}
1074 +EXPORT_SYMBOL(dpcon_reset);
1075 +
1076 +/**
1077 + * dpcon_get_attributes() - Retrieve DPCON attributes.
1078 + * @mc_io: Pointer to MC portal's I/O object
1079 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1080 + * @token: Token of DPCON object
1081 + * @attr: Object's attributes
1082 + *
1083 + * Return: '0' on Success; Error code otherwise.
1084 + */
1085 +int dpcon_get_attributes(struct fsl_mc_io *mc_io,
1086 + u32 cmd_flags,
1087 + u16 token,
1088 + struct dpcon_attr *attr)
1089 +{
1090 + struct mc_command cmd = { 0 };
1091 + struct dpcon_rsp_get_attr *dpcon_rsp;
1092 + int err;
1093 +
1094 + /* prepare command */
1095 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_ATTR,
1096 + cmd_flags,
1097 + token);
1098 +
1099 + /* send command to mc*/
1100 + err = mc_send_command(mc_io, &cmd);
1101 + if (err)
1102 + return err;
1103 +
1104 + /* retrieve response parameters */
1105 + dpcon_rsp = (struct dpcon_rsp_get_attr *)cmd.params;
1106 + attr->id = le32_to_cpu(dpcon_rsp->id);
1107 + attr->qbman_ch_id = le16_to_cpu(dpcon_rsp->qbman_ch_id);
1108 + attr->num_priorities = dpcon_rsp->num_priorities;
1109 +
1110 + return 0;
1111 +}
1112 +EXPORT_SYMBOL(dpcon_get_attributes);
1113 +
1114 +/**
1115 + * dpcon_set_notification() - Set DPCON notification destination
1116 + * @mc_io: Pointer to MC portal's I/O object
1117 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1118 + * @token: Token of DPCON object
1119 + * @cfg: Notification parameters
1120 + *
1121 + * Return: '0' on Success; Error code otherwise
1122 + */
1123 +int dpcon_set_notification(struct fsl_mc_io *mc_io,
1124 + u32 cmd_flags,
1125 + u16 token,
1126 + struct dpcon_notification_cfg *cfg)
1127 +{
1128 + struct mc_command cmd = { 0 };
1129 + struct dpcon_cmd_set_notification *dpcon_cmd;
1130 +
1131 + /* prepare command */
1132 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_NOTIFICATION,
1133 + cmd_flags,
1134 + token);
1135 + dpcon_cmd = (struct dpcon_cmd_set_notification *)cmd.params;
1136 + dpcon_cmd->dpio_id = cpu_to_le32(cfg->dpio_id);
1137 + dpcon_cmd->priority = cfg->priority;
1138 + dpcon_cmd->user_ctx = cpu_to_le64(cfg->user_ctx);
1139 +
1140 + /* send command to mc*/
1141 + return mc_send_command(mc_io, &cmd);
1142 +}
1143 +EXPORT_SYMBOL(dpcon_set_notification);
1144 +
1145 +/**
1146 + * dpcon_get_api_version - Get Data Path Concentrator API version
1147 + * @mc_io: Pointer to MC portal's DPCON object
1148 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1149 + * @major_ver: Major version of DPCON API
1150 + * @minor_ver: Minor version of DPCON API
1151 + *
1152 + * Return: '0' on Success; Error code otherwise
1153 + */
1154 +int dpcon_get_api_version(struct fsl_mc_io *mc_io,
1155 + u32 cmd_flags,
1156 + u16 *major_ver,
1157 + u16 *minor_ver)
1158 +{
1159 + struct mc_command cmd = { 0 };
1160 + int err;
1161 +
1162 + /* prepare command */
1163 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_API_VERSION,
1164 + cmd_flags, 0);
1165 +
1166 + /* send command to mc */
1167 + err = mc_send_command(mc_io, &cmd);
1168 + if (err)
1169 + return err;
1170 +
1171 + /* retrieve response parameters */
1172 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
1173 +
1174 + return 0;
1175 +}
1176 +EXPORT_SYMBOL(dpcon_get_api_version);
1177 --- /dev/null
1178 +++ b/drivers/staging/fsl-mc/bus/dpio/Makefile
1179 @@ -0,0 +1,11 @@
1180 +#
1181 +# QorIQ DPAA2 DPIO driver
1182 +#
1183 +
1184 +subdir-ccflags-y := -Werror
1185 +
1186 +obj-$(CONFIG_FSL_MC_DPIO) += fsl-mc-dpio.o
1187 +
1188 +fsl-mc-dpio-objs := dpio.o qbman-portal.o dpio-service.o dpio-driver.o
1189 +
1190 +obj-$(CONFIG_FSL_QBMAN_DEBUG) += qbman_debug.o
1191 --- a/drivers/staging/fsl-mc/include/dpcon-cmd.h
1192 +++ /dev/null
1193 @@ -1,62 +0,0 @@
1194 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
1195 - *
1196 - * Redistribution and use in source and binary forms, with or without
1197 - * modification, are permitted provided that the following conditions are met:
1198 - * * Redistributions of source code must retain the above copyright
1199 - * notice, this list of conditions and the following disclaimer.
1200 - * * Redistributions in binary form must reproduce the above copyright
1201 - * notice, this list of conditions and the following disclaimer in the
1202 - * documentation and/or other materials provided with the distribution.
1203 - * * Neither the name of the above-listed copyright holders nor the
1204 - * names of any contributors may be used to endorse or promote products
1205 - * derived from this software without specific prior written permission.
1206 - *
1207 - *
1208 - * ALTERNATIVELY, this software may be distributed under the terms of the
1209 - * GNU General Public License ("GPL") as published by the Free Software
1210 - * Foundation, either version 2 of that License or (at your option) any
1211 - * later version.
1212 - *
1213 - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1214 - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1215 - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1216 - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
1217 - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1218 - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1219 - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1220 - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1221 - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1222 - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1223 - * POSSIBILITY OF SUCH DAMAGE.
1224 - */
1225 -#ifndef _FSL_DPCON_CMD_H
1226 -#define _FSL_DPCON_CMD_H
1227 -
1228 -/* DPCON Version */
1229 -#define DPCON_VER_MAJOR 2
1230 -#define DPCON_VER_MINOR 1
1231 -
1232 -/* Command IDs */
1233 -#define DPCON_CMDID_CLOSE 0x800
1234 -#define DPCON_CMDID_OPEN 0x808
1235 -#define DPCON_CMDID_CREATE 0x908
1236 -#define DPCON_CMDID_DESTROY 0x900
1237 -
1238 -#define DPCON_CMDID_ENABLE 0x002
1239 -#define DPCON_CMDID_DISABLE 0x003
1240 -#define DPCON_CMDID_GET_ATTR 0x004
1241 -#define DPCON_CMDID_RESET 0x005
1242 -#define DPCON_CMDID_IS_ENABLED 0x006
1243 -
1244 -#define DPCON_CMDID_SET_IRQ 0x010
1245 -#define DPCON_CMDID_GET_IRQ 0x011
1246 -#define DPCON_CMDID_SET_IRQ_ENABLE 0x012
1247 -#define DPCON_CMDID_GET_IRQ_ENABLE 0x013
1248 -#define DPCON_CMDID_SET_IRQ_MASK 0x014
1249 -#define DPCON_CMDID_GET_IRQ_MASK 0x015
1250 -#define DPCON_CMDID_GET_IRQ_STATUS 0x016
1251 -#define DPCON_CMDID_CLEAR_IRQ_STATUS 0x017
1252 -
1253 -#define DPCON_CMDID_SET_NOTIFICATION 0x100
1254 -
1255 -#endif /* _FSL_DPCON_CMD_H */
1256 --- /dev/null
1257 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
1258 @@ -0,0 +1,75 @@
1259 +/*
1260 + * Copyright 2013-2016 Freescale Semiconductor Inc.
1261 + * Copyright 2016 NXP
1262 + *
1263 + * Redistribution and use in source and binary forms, with or without
1264 + * modification, are permitted provided that the following conditions are met:
1265 + * * Redistributions of source code must retain the above copyright
1266 + * notice, this list of conditions and the following disclaimer.
1267 + * * Redistributions in binary form must reproduce the above copyright
1268 + * notice, this list of conditions and the following disclaimer in the
1269 + * documentation and/or other materials provided with the distribution.
1270 + * * Neither the name of the above-listed copyright holders nor the
1271 + * names of any contributors may be used to endorse or promote products
1272 + * derived from this software without specific prior written permission.
1273 + *
1274 + * ALTERNATIVELY, this software may be distributed under the terms of the
1275 + * GNU General Public License ("GPL") as published by the Free Software
1276 + * Foundation, either version 2 of that License or (at your option) any
1277 + * later version.
1278 + *
1279 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1280 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1281 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1282 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
1283 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1284 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1285 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1286 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1287 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1288 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1289 + * POSSIBILITY OF SUCH DAMAGE.
1290 + */
1291 +#ifndef _FSL_DPIO_CMD_H
1292 +#define _FSL_DPIO_CMD_H
1293 +
1294 +/* DPIO Version */
1295 +#define DPIO_VER_MAJOR 4
1296 +#define DPIO_VER_MINOR 2
1297 +
1298 +/* Command Versioning */
1299 +
1300 +#define DPIO_CMD_ID_OFFSET 4
1301 +#define DPIO_CMD_BASE_VERSION 1
1302 +
1303 +#define DPIO_CMD(id) (((id) << DPIO_CMD_ID_OFFSET) | DPIO_CMD_BASE_VERSION)
1304 +
1305 +/* Command IDs */
1306 +#define DPIO_CMDID_CLOSE DPIO_CMD(0x800)
1307 +#define DPIO_CMDID_OPEN DPIO_CMD(0x803)
1308 +#define DPIO_CMDID_GET_API_VERSION DPIO_CMD(0xa03)
1309 +#define DPIO_CMDID_ENABLE DPIO_CMD(0x002)
1310 +#define DPIO_CMDID_DISABLE DPIO_CMD(0x003)
1311 +#define DPIO_CMDID_GET_ATTR DPIO_CMD(0x004)
1312 +
1313 +struct dpio_cmd_open {
1314 + __le32 dpio_id;
1315 +};
1316 +
1317 +#define DPIO_CHANNEL_MODE_MASK 0x3
1318 +
1319 +struct dpio_rsp_get_attr {
1320 + /* cmd word 0 */
1321 + __le32 id;
1322 + __le16 qbman_portal_id;
1323 + u8 num_priorities;
1324 + u8 channel_mode;
1325 + /* cmd word 1 */
1326 + __le64 qbman_portal_ce_addr;
1327 + /* cmd word 2 */
1328 + __le64 qbman_portal_ci_addr;
1329 + /* cmd word 3 */
1330 + __le32 qbman_version;
1331 +};
1332 +
1333 +#endif /* _FSL_DPIO_CMD_H */
1334 --- /dev/null
1335 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
1336 @@ -0,0 +1,296 @@
1337 +/*
1338 + * Copyright 2014-2016 Freescale Semiconductor Inc.
1339 + * Copyright 2016 NXP
1340 + *
1341 + * Redistribution and use in source and binary forms, with or without
1342 + * modification, are permitted provided that the following conditions are met:
1343 + * * Redistributions of source code must retain the above copyright
1344 + * notice, this list of conditions and the following disclaimer.
1345 + * * Redistributions in binary form must reproduce the above copyright
1346 + * notice, this list of conditions and the following disclaimer in the
1347 + * documentation and/or other materials provided with the distribution.
1348 + * * Neither the name of Freescale Semiconductor nor the
1349 + * names of its contributors may be used to endorse or promote products
1350 + * derived from this software without specific prior written permission.
1351 + *
1352 + * ALTERNATIVELY, this software may be distributed under the terms of the
1353 + * GNU General Public License ("GPL") as published by the Free Software
1354 + * Foundation, either version 2 of that License or (at your option) any
1355 + * later version.
1356 + *
1357 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
1358 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
1359 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
1360 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
1361 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1362 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1363 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1364 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1365 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1366 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1367 + */
1368 +
1369 +#include <linux/types.h>
1370 +#include <linux/init.h>
1371 +#include <linux/module.h>
1372 +#include <linux/platform_device.h>
1373 +#include <linux/interrupt.h>
1374 +#include <linux/msi.h>
1375 +#include <linux/dma-mapping.h>
1376 +#include <linux/delay.h>
1377 +
1378 +#include "../../include/mc.h"
1379 +#include "../../include/dpaa2-io.h"
1380 +
1381 +#include "qbman-portal.h"
1382 +#include "dpio.h"
1383 +#include "dpio-cmd.h"
1384 +
1385 +MODULE_LICENSE("Dual BSD/GPL");
1386 +MODULE_AUTHOR("Freescale Semiconductor, Inc");
1387 +MODULE_DESCRIPTION("DPIO Driver");
1388 +
1389 +struct dpio_priv {
1390 + struct dpaa2_io *io;
1391 +};
1392 +
1393 +static irqreturn_t dpio_irq_handler(int irq_num, void *arg)
1394 +{
1395 + struct device *dev = (struct device *)arg;
1396 + struct dpio_priv *priv = dev_get_drvdata(dev);
1397 +
1398 + return dpaa2_io_irq(priv->io);
1399 +}
1400 +
1401 +static void unregister_dpio_irq_handlers(struct fsl_mc_device *dpio_dev)
1402 +{
1403 + struct fsl_mc_device_irq *irq;
1404 +
1405 + irq = dpio_dev->irqs[0];
1406 +
1407 + /* clear the affinity hint */
1408 + irq_set_affinity_hint(irq->msi_desc->irq, NULL);
1409 +}
1410 +
1411 +static int register_dpio_irq_handlers(struct fsl_mc_device *dpio_dev, int cpu)
1412 +{
1413 + struct dpio_priv *priv;
1414 + int error;
1415 + struct fsl_mc_device_irq *irq;
1416 + cpumask_t mask;
1417 +
1418 + priv = dev_get_drvdata(&dpio_dev->dev);
1419 +
1420 + irq = dpio_dev->irqs[0];
1421 + error = devm_request_irq(&dpio_dev->dev,
1422 + irq->msi_desc->irq,
1423 + dpio_irq_handler,
1424 + 0,
1425 + dev_name(&dpio_dev->dev),
1426 + &dpio_dev->dev);
1427 + if (error < 0) {
1428 + dev_err(&dpio_dev->dev,
1429 + "devm_request_irq() failed: %d\n",
1430 + error);
1431 + return error;
1432 + }
1433 +
1434 + /* set the affinity hint */
1435 + cpumask_clear(&mask);
1436 + cpumask_set_cpu(cpu, &mask);
1437 + if (irq_set_affinity_hint(irq->msi_desc->irq, &mask))
1438 + dev_err(&dpio_dev->dev,
1439 + "irq_set_affinity failed irq %d cpu %d\n",
1440 + irq->msi_desc->irq, cpu);
1441 +
1442 + return 0;
1443 +}
1444 +
1445 +static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
1446 +{
1447 + struct dpio_attr dpio_attrs;
1448 + struct dpaa2_io_desc desc;
1449 + struct dpio_priv *priv;
1450 + int err = -ENOMEM;
1451 + struct device *dev = &dpio_dev->dev;
1452 + static int next_cpu = -1;
1453 +
1454 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1455 + if (!priv)
1456 + goto err_priv_alloc;
1457 +
1458 + dev_set_drvdata(dev, priv);
1459 +
1460 + err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
1461 + if (err) {
1462 + dev_dbg(dev, "MC portal allocation failed\n");
1463 + err = -EPROBE_DEFER;
1464 + goto err_mcportal;
1465 + }
1466 +
1467 + err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
1468 + &dpio_dev->mc_handle);
1469 + if (err) {
1470 + dev_err(dev, "dpio_open() failed\n");
1471 + goto err_open;
1472 + }
1473 +
1474 + err = dpio_get_attributes(dpio_dev->mc_io, 0, dpio_dev->mc_handle,
1475 + &dpio_attrs);
1476 + if (err) {
1477 + dev_err(dev, "dpio_get_attributes() failed %d\n", err);
1478 + goto err_get_attr;
1479 + }
1480 + desc.qman_version = dpio_attrs.qbman_version;
1481 +
1482 + err = dpio_enable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1483 + if (err) {
1484 + dev_err(dev, "dpio_enable() failed %d\n", err);
1485 + goto err_get_attr;
1486 + }
1487 +
1488 + /* initialize DPIO descriptor */
1489 + desc.receives_notifications = dpio_attrs.num_priorities ? 1 : 0;
1490 + desc.has_8prio = dpio_attrs.num_priorities == 8 ? 1 : 0;
1491 + desc.dpio_id = dpio_dev->obj_desc.id;
1492 +
1493 + /* get the cpu to use for the affinity hint */
1494 + if (next_cpu == -1)
1495 + next_cpu = cpumask_first(cpu_online_mask);
1496 + else
1497 + next_cpu = cpumask_next(next_cpu, cpu_online_mask);
1498 +
1499 + if (!cpu_possible(next_cpu)) {
1500 + dev_err(dev, "probe failed. Number of DPIOs exceeds NR_CPUS.\n");
1501 + err = -ERANGE;
1502 + goto err_allocate_irqs;
1503 + }
1504 + desc.cpu = next_cpu;
1505 +
1506 + /*
1507 + * Set the CENA regs to be the cache enabled area of the portal to
1508 + * achieve the best performance.
1509 + */
1510 + desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[0].start,
1511 + resource_size(&dpio_dev->regions[0]));
1512 + desc.regs_cinh = ioremap(dpio_dev->regions[1].start,
1513 + resource_size(&dpio_dev->regions[1]));
1514 +
1515 + err = fsl_mc_allocate_irqs(dpio_dev);
1516 + if (err) {
1517 + dev_err(dev, "fsl_mc_allocate_irqs failed. err=%d\n", err);
1518 + goto err_allocate_irqs;
1519 + }
1520 +
1521 + err = register_dpio_irq_handlers(dpio_dev, desc.cpu);
1522 + if (err)
1523 + goto err_register_dpio_irq;
1524 +
1525 + priv->io = dpaa2_io_create(&desc);
1526 + if (!priv->io) {
1527 + dev_err(dev, "dpaa2_io_create failed\n");
1528 + goto err_dpaa2_io_create;
1529 + }
1530 +
1531 + dev_info(dev, "probed\n");
1532 + dev_dbg(dev, " receives_notifications = %d\n",
1533 + desc.receives_notifications);
1534 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1535 + fsl_mc_portal_free(dpio_dev->mc_io);
1536 +
1537 + return 0;
1538 +
1539 +err_dpaa2_io_create:
1540 + unregister_dpio_irq_handlers(dpio_dev);
1541 +err_register_dpio_irq:
1542 + fsl_mc_free_irqs(dpio_dev);
1543 +err_allocate_irqs:
1544 + dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1545 +err_get_attr:
1546 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1547 +err_open:
1548 + fsl_mc_portal_free(dpio_dev->mc_io);
1549 +err_mcportal:
1550 + dev_set_drvdata(dev, NULL);
1551 +err_priv_alloc:
1552 + return err;
1553 +}
1554 +
1555 +/* Tear down interrupts for a given DPIO object */
1556 +static void dpio_teardown_irqs(struct fsl_mc_device *dpio_dev)
1557 +{
1558 + unregister_dpio_irq_handlers(dpio_dev);
1559 + fsl_mc_free_irqs(dpio_dev);
1560 +}
1561 +
1562 +static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev)
1563 +{
1564 + struct device *dev;
1565 + struct dpio_priv *priv;
1566 + int err;
1567 +
1568 + dev = &dpio_dev->dev;
1569 + priv = dev_get_drvdata(dev);
1570 +
1571 + dpaa2_io_down(priv->io);
1572 +
1573 + dpio_teardown_irqs(dpio_dev);
1574 +
1575 + err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
1576 + if (err) {
1577 + dev_err(dev, "MC portal allocation failed\n");
1578 + goto err_mcportal;
1579 + }
1580 +
1581 + err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
1582 + &dpio_dev->mc_handle);
1583 + if (err) {
1584 + dev_err(dev, "dpio_open() failed\n");
1585 + goto err_open;
1586 + }
1587 +
1588 + dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1589 +
1590 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1591 +
1592 + fsl_mc_portal_free(dpio_dev->mc_io);
1593 +
1594 + dev_set_drvdata(dev, NULL);
1595 +
1596 + return 0;
1597 +
1598 +err_open:
1599 + fsl_mc_portal_free(dpio_dev->mc_io);
1600 +err_mcportal:
1601 + return err;
1602 +}
1603 +
1604 +static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = {
1605 + {
1606 + .vendor = FSL_MC_VENDOR_FREESCALE,
1607 + .obj_type = "dpio",
1608 + },
1609 + { .vendor = 0x0 }
1610 +};
1611 +
1612 +static struct fsl_mc_driver dpaa2_dpio_driver = {
1613 + .driver = {
1614 + .name = KBUILD_MODNAME,
1615 + .owner = THIS_MODULE,
1616 + },
1617 + .probe = dpaa2_dpio_probe,
1618 + .remove = dpaa2_dpio_remove,
1619 + .match_id_table = dpaa2_dpio_match_id_table
1620 +};
1621 +
1622 +static int dpio_driver_init(void)
1623 +{
1624 + return fsl_mc_driver_register(&dpaa2_dpio_driver);
1625 +}
1626 +
1627 +static void dpio_driver_exit(void)
1628 +{
1629 + fsl_mc_driver_unregister(&dpaa2_dpio_driver);
1630 +}
1631 +module_init(dpio_driver_init);
1632 +module_exit(dpio_driver_exit);
1633 --- /dev/null
1634 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
1635 @@ -0,0 +1,693 @@
1636 +/*
1637 + * Copyright 2014-2016 Freescale Semiconductor Inc.
1638 + * Copyright 2016 NXP
1639 + *
1640 + * Redistribution and use in source and binary forms, with or without
1641 + * modification, are permitted provided that the following conditions are met:
1642 + * * Redistributions of source code must retain the above copyright
1643 + * notice, this list of conditions and the following disclaimer.
1644 + * * Redistributions in binary form must reproduce the above copyright
1645 + * notice, this list of conditions and the following disclaimer in the
1646 + * documentation and/or other materials provided with the distribution.
1647 + * * Neither the name of Freescale Semiconductor nor the
1648 + * names of its contributors may be used to endorse or promote products
1649 + * derived from this software without specific prior written permission.
1650 + *
1651 + * ALTERNATIVELY, this software may be distributed under the terms of the
1652 + * GNU General Public License ("GPL") as published by the Free Software
1653 + * Foundation, either version 2 of that License or (at your option) any
1654 + * later version.
1655 + *
1656 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
1657 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
1658 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
1659 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
1660 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1661 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1662 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1663 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1664 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1665 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1666 + */
1667 +#include <linux/types.h>
1668 +#include "../../include/mc.h"
1669 +#include "../../include/dpaa2-io.h"
1670 +#include <linux/init.h>
1671 +#include <linux/module.h>
1672 +#include <linux/platform_device.h>
1673 +#include <linux/interrupt.h>
1674 +#include <linux/dma-mapping.h>
1675 +#include <linux/slab.h>
1676 +
1677 +#include "dpio.h"
1678 +#include "qbman-portal.h"
1679 +#include "qbman_debug.h"
1680 +
1681 +struct dpaa2_io {
1682 + atomic_t refs;
1683 + struct dpaa2_io_desc dpio_desc;
1684 + struct qbman_swp_desc swp_desc;
1685 + struct qbman_swp *swp;
1686 + struct list_head node;
1687 + /* protect against multiple management commands */
1688 + spinlock_t lock_mgmt_cmd;
1689 + /* protect notifications list */
1690 + spinlock_t lock_notifications;
1691 + struct list_head notifications;
1692 +};
1693 +
1694 +struct dpaa2_io_store {
1695 + unsigned int max;
1696 + dma_addr_t paddr;
1697 + struct dpaa2_dq *vaddr;
1698 + void *alloced_addr; /* unaligned value from kmalloc() */
1699 + unsigned int idx; /* position of the next-to-be-returned entry */
1700 + struct qbman_swp *swp; /* portal used to issue VDQCR */
1701 + struct device *dev; /* device used for DMA mapping */
1702 +};
1703 +
1704 +/* keep a per cpu array of DPIOs for fast access */
1705 +static struct dpaa2_io *dpio_by_cpu[NR_CPUS];
1706 +static struct list_head dpio_list = LIST_HEAD_INIT(dpio_list);
1707 +static DEFINE_SPINLOCK(dpio_list_lock);
1708 +
1709 +static inline struct dpaa2_io *service_select_by_cpu(struct dpaa2_io *d,
1710 + int cpu)
1711 +{
1712 + if (d)
1713 + return d;
1714 +
1715 + if (unlikely(cpu >= (int)num_possible_cpus()))
1716 + return NULL;
1717 +
1718 + /*
1719 + * If cpu == -1, choose the current cpu, with no guarantees about
1720 + * potentially being migrated away.
1721 + */
1722 + if (cpu < 0)
1723 + cpu = smp_processor_id();
1724 +
1725 + /* If a specific cpu was requested, pick it up immediately */
1726 + return dpio_by_cpu[cpu];
1727 +}
1728 +
1729 +static inline struct dpaa2_io *service_select(struct dpaa2_io *d)
1730 +{
1731 + if (d)
1732 + return d;
1733 +
1734 + d = service_select_by_cpu(d, -1);
1735 + if (d)
1736 + return d;
1737 +
1738 + spin_lock(&dpio_list_lock);
1739 + d = list_entry(dpio_list.next, struct dpaa2_io, node);
1740 + list_del(&d->node);
1741 + list_add_tail(&d->node, &dpio_list);
1742 + spin_unlock(&dpio_list_lock);
1743 +
1744 + return d;
1745 +}
1746 +
1747 +/**
1748 + * dpaa2_io_create() - create a dpaa2_io object.
1749 + * @desc: the dpaa2_io descriptor
1750 + *
1751 + * Activates a "struct dpaa2_io" corresponding to the given config of an actual
1752 + * DPIO object.
1753 + *
1754 + * Return a valid dpaa2_io object for success, or NULL for failure.
1755 + */
1756 +struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc)
1757 +{
1758 + struct dpaa2_io *obj = kmalloc(sizeof(*obj), GFP_KERNEL);
1759 +
1760 + if (!obj)
1761 + return NULL;
1762 +
1763 + /* check if CPU is out of range (-1 means any cpu) */
1764 + if (desc->cpu >= (int)num_possible_cpus()) {
1765 + kfree(obj);
1766 + return NULL;
1767 + }
1768 +
1769 + atomic_set(&obj->refs, 1);
1770 + obj->dpio_desc = *desc;
1771 + obj->swp_desc.cena_bar = obj->dpio_desc.regs_cena;
1772 + obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh;
1773 + obj->swp_desc.qman_version = obj->dpio_desc.qman_version;
1774 + obj->swp = qbman_swp_init(&obj->swp_desc);
1775 +
1776 + if (!obj->swp) {
1777 + kfree(obj);
1778 + return NULL;
1779 + }
1780 +
1781 + INIT_LIST_HEAD(&obj->node);
1782 + spin_lock_init(&obj->lock_mgmt_cmd);
1783 + spin_lock_init(&obj->lock_notifications);
1784 + INIT_LIST_HEAD(&obj->notifications);
1785 +
1786 + /* For now only enable DQRR interrupts */
1787 + qbman_swp_interrupt_set_trigger(obj->swp,
1788 + QBMAN_SWP_INTERRUPT_DQRI);
1789 + qbman_swp_interrupt_clear_status(obj->swp, 0xffffffff);
1790 + if (obj->dpio_desc.receives_notifications)
1791 + qbman_swp_push_set(obj->swp, 0, 1);
1792 +
1793 + spin_lock(&dpio_list_lock);
1794 + list_add_tail(&obj->node, &dpio_list);
1795 + if (desc->cpu >= 0 && !dpio_by_cpu[desc->cpu])
1796 + dpio_by_cpu[desc->cpu] = obj;
1797 + spin_unlock(&dpio_list_lock);
1798 +
1799 + return obj;
1800 +}
1801 +EXPORT_SYMBOL(dpaa2_io_create);
1802 +
1803 +/**
1804 + * dpaa2_io_down() - release the dpaa2_io object.
1805 + * @d: the dpaa2_io object to be released.
1806 + *
1807 + * The "struct dpaa2_io" type can represent an individual DPIO object (as
1808 + * described by "struct dpaa2_io_desc") or an instance of a "DPIO service",
1809 + * which can be used to group/encapsulate multiple DPIO objects. In all cases,
1810 + * each handle obtained should be released using this function.
1811 + */
1812 +void dpaa2_io_down(struct dpaa2_io *d)
1813 +{
1814 + if (!atomic_dec_and_test(&d->refs))
1815 + return;
1816 + kfree(d);
1817 +}
1818 +EXPORT_SYMBOL(dpaa2_io_down);
1819 +
1820 +#define DPAA_POLL_MAX 32
1821 +
1822 +/**
1823 + * dpaa2_io_irq() - ISR for DPIO interrupts
1824 + *
1825 + * @obj: the given DPIO object.
1826 + *
1827 + * Return IRQ_HANDLED for success or IRQ_NONE if there
1828 + * were no pending interrupts.
1829 + */
1830 +irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj)
1831 +{
1832 + const struct dpaa2_dq *dq;
1833 + int max = 0;
1834 + struct qbman_swp *swp;
1835 + u32 status;
1836 +
1837 + swp = obj->swp;
1838 + status = qbman_swp_interrupt_read_status(swp);
1839 + if (!status)
1840 + return IRQ_NONE;
1841 +
1842 + dq = qbman_swp_dqrr_next(swp);
1843 + while (dq) {
1844 + if (qbman_result_is_SCN(dq)) {
1845 + struct dpaa2_io_notification_ctx *ctx;
1846 + u64 q64;
1847 +
1848 + q64 = qbman_result_SCN_ctx(dq);
1849 + ctx = (void *)q64;
1850 + ctx->cb(ctx);
1851 + } else {
1852 + pr_crit("fsl-mc-dpio: Unrecognised/ignored DQRR entry\n");
1853 + }
1854 + qbman_swp_dqrr_consume(swp, dq);
1855 + ++max;
1856 + if (max > DPAA_POLL_MAX)
1857 + goto done;
1858 + dq = qbman_swp_dqrr_next(swp);
1859 + }
1860 +done:
1861 + qbman_swp_interrupt_clear_status(swp, status);
1862 + qbman_swp_interrupt_set_inhibit(swp, 0);
1863 + return IRQ_HANDLED;
1864 +}
1865 +EXPORT_SYMBOL(dpaa2_io_irq);
1866 +
1867 +/**
1868 + * dpaa2_io_service_register() - Prepare for servicing of FQDAN or CDAN
1869 + * notifications on the given DPIO service.
1870 + * @d: the given DPIO service.
1871 + * @ctx: the notification context.
1872 + *
1873 + * The caller should make the MC command to attach a DPAA2 object to
1874 + * a DPIO after this function completes successfully. In that way:
1875 + * (a) The DPIO service is "ready" to handle a notification arrival
1876 + * (which might happen before the "attach" command to MC has
1877 + * returned control of execution back to the caller)
1878 + * (b) The DPIO service can provide back to the caller the 'dpio_id' and
1879 + * 'qman64' parameters that it should pass along in the MC command
1880 + * in order for the object to be configured to produce the right
1881 + * notification fields to the DPIO service.
1882 + *
1883 + * Return 0 for success, or -ENODEV for failure.
1884 + */
1885 +int dpaa2_io_service_register(struct dpaa2_io *d,
1886 + struct dpaa2_io_notification_ctx *ctx)
1887 +{
1888 + unsigned long irqflags;
1889 +
1890 + d = service_select_by_cpu(d, ctx->desired_cpu);
1891 + if (!d)
1892 + return -ENODEV;
1893 +
1894 + ctx->dpio_id = d->dpio_desc.dpio_id;
1895 + ctx->qman64 = (u64)ctx;
1896 + ctx->dpio_private = d;
1897 + spin_lock_irqsave(&d->lock_notifications, irqflags);
1898 + list_add(&ctx->node, &d->notifications);
1899 + spin_unlock_irqrestore(&d->lock_notifications, irqflags);
1900 +
1901 + /* Enable the generation of CDAN notifications */
1902 + if (ctx->is_cdan)
1903 + qbman_swp_CDAN_set_context_enable(d->swp,
1904 + (u16)ctx->id,
1905 + ctx->qman64);
1906 + return 0;
1907 +}
1908 +EXPORT_SYMBOL(dpaa2_io_service_register);
1909 +
1910 +/**
1911 + * dpaa2_io_service_deregister - The opposite of 'register'.
1912 + * @service: the given DPIO service.
1913 + * @ctx: the notification context.
1914 + *
1915 + * This function should be called only after sending the MC command to
1916 + * to detach the notification-producing device from the DPIO.
1917 + */
1918 +void dpaa2_io_service_deregister(struct dpaa2_io *service,
1919 + struct dpaa2_io_notification_ctx *ctx)
1920 +{
1921 + struct dpaa2_io *d = ctx->dpio_private;
1922 + unsigned long irqflags;
1923 +
1924 + if (ctx->is_cdan)
1925 + qbman_swp_CDAN_disable(d->swp, (u16)ctx->id);
1926 +
1927 + spin_lock_irqsave(&d->lock_notifications, irqflags);
1928 + list_del(&ctx->node);
1929 + spin_unlock_irqrestore(&d->lock_notifications, irqflags);
1930 +}
1931 +EXPORT_SYMBOL(dpaa2_io_service_deregister);
1932 +
1933 +/**
1934 + * dpaa2_io_service_rearm() - Rearm the notification for the given DPIO service.
1935 + * @d: the given DPIO service.
1936 + * @ctx: the notification context.
1937 + *
1938 + * Once a FQDAN/CDAN has been produced, the corresponding FQ/channel is
1939 + * considered "disarmed". Ie. the user can issue pull dequeue operations on that
1940 + * traffic source for as long as it likes. Eventually it may wish to "rearm"
1941 + * that source to allow it to produce another FQDAN/CDAN, that's what this
1942 + * function achieves.
1943 + *
1944 + * Return 0 for success.
1945 + */
1946 +int dpaa2_io_service_rearm(struct dpaa2_io *d,
1947 + struct dpaa2_io_notification_ctx *ctx)
1948 +{
1949 + unsigned long irqflags;
1950 + int err;
1951 +
1952 + d = service_select_by_cpu(d, ctx->desired_cpu);
1953 + if (!unlikely(d))
1954 + return -ENODEV;
1955 +
1956 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
1957 + if (ctx->is_cdan)
1958 + err = qbman_swp_CDAN_enable(d->swp, (u16)ctx->id);
1959 + else
1960 + err = qbman_swp_fq_schedule(d->swp, ctx->id);
1961 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
1962 +
1963 + return err;
1964 +}
1965 +EXPORT_SYMBOL(dpaa2_io_service_rearm);
1966 +
1967 +/**
1968 + * dpaa2_io_service_pull_fq() - pull dequeue functions from a fq.
1969 + * @d: the given DPIO service.
1970 + * @fqid: the given frame queue id.
1971 + * @s: the dpaa2_io_store object for the result.
1972 + *
1973 + * Return 0 for success, or error code for failure.
1974 + */
1975 +int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
1976 + struct dpaa2_io_store *s)
1977 +{
1978 + struct qbman_pull_desc pd;
1979 + int err;
1980 +
1981 + qbman_pull_desc_clear(&pd);
1982 + qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
1983 + qbman_pull_desc_set_numframes(&pd, (u8)s->max);
1984 + qbman_pull_desc_set_fq(&pd, fqid);
1985 +
1986 + d = service_select(d);
1987 + if (!d)
1988 + return -ENODEV;
1989 + s->swp = d->swp;
1990 + err = qbman_swp_pull(d->swp, &pd);
1991 + if (err)
1992 + s->swp = NULL;
1993 +
1994 + return err;
1995 +}
1996 +EXPORT_SYMBOL(dpaa2_io_service_pull_fq);
1997 +
1998 +/**
1999 + * dpaa2_io_service_pull_channel() - pull dequeue functions from a channel.
2000 + * @d: the given DPIO service.
2001 + * @channelid: the given channel id.
2002 + * @s: the dpaa2_io_store object for the result.
2003 + *
2004 + * Return 0 for success, or error code for failure.
2005 + */
2006 +int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
2007 + struct dpaa2_io_store *s)
2008 +{
2009 + struct qbman_pull_desc pd;
2010 + int err;
2011 +
2012 + qbman_pull_desc_clear(&pd);
2013 + qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
2014 + qbman_pull_desc_set_numframes(&pd, (u8)s->max);
2015 + qbman_pull_desc_set_channel(&pd, channelid, qbman_pull_type_prio);
2016 +
2017 + d = service_select(d);
2018 + if (!d)
2019 + return -ENODEV;
2020 +
2021 + s->swp = d->swp;
2022 + err = qbman_swp_pull(d->swp, &pd);
2023 + if (err)
2024 + s->swp = NULL;
2025 +
2026 + return err;
2027 +}
2028 +EXPORT_SYMBOL(dpaa2_io_service_pull_channel);
2029 +
2030 +/**
2031 + * dpaa2_io_service_enqueue_fq() - Enqueue a frame to a frame queue.
2032 + * @d: the given DPIO service.
2033 + * @fqid: the given frame queue id.
2034 + * @fd: the frame descriptor which is enqueued.
2035 + *
2036 + * Return 0 for successful enqueue, -EBUSY if the enqueue ring is not ready,
2037 + * or -ENODEV if there is no dpio service.
2038 + */
2039 +int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d,
2040 + u32 fqid,
2041 + const struct dpaa2_fd *fd)
2042 +{
2043 + struct qbman_eq_desc ed;
2044 +
2045 + d = service_select(d);
2046 + if (!d)
2047 + return -ENODEV;
2048 +
2049 + qbman_eq_desc_clear(&ed);
2050 + qbman_eq_desc_set_no_orp(&ed, 0);
2051 + qbman_eq_desc_set_fq(&ed, fqid);
2052 +
2053 + return qbman_swp_enqueue(d->swp, &ed, fd);
2054 +}
2055 +EXPORT_SYMBOL(dpaa2_io_service_enqueue_fq);
2056 +
2057 +/**
2058 + * dpaa2_io_service_enqueue_qd() - Enqueue a frame to a QD.
2059 + * @d: the given DPIO service.
2060 + * @qdid: the given queuing destination id.
2061 + * @prio: the given queuing priority.
2062 + * @qdbin: the given queuing destination bin.
2063 + * @fd: the frame descriptor which is enqueued.
2064 + *
2065 + * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
2066 + * or -ENODEV if there is no dpio service.
2067 + */
2068 +int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d,
2069 + u32 qdid, u8 prio, u16 qdbin,
2070 + const struct dpaa2_fd *fd)
2071 +{
2072 + struct qbman_eq_desc ed;
2073 +
2074 + d = service_select(d);
2075 + if (!d)
2076 + return -ENODEV;
2077 +
2078 + qbman_eq_desc_clear(&ed);
2079 + qbman_eq_desc_set_no_orp(&ed, 0);
2080 + qbman_eq_desc_set_qd(&ed, qdid, qdbin, prio);
2081 +
2082 + return qbman_swp_enqueue(d->swp, &ed, fd);
2083 +}
2084 +EXPORT_SYMBOL(dpaa2_io_service_enqueue_qd);
2085 +
2086 +/**
2087 + * dpaa2_io_service_release() - Release buffers to a buffer pool.
2088 + * @d: the given DPIO object.
2089 + * @bpid: the buffer pool id.
2090 + * @buffers: the buffers to be released.
2091 + * @num_buffers: the number of the buffers to be released.
2092 + *
2093 + * Return 0 for success, and negative error code for failure.
2094 + */
2095 +int dpaa2_io_service_release(struct dpaa2_io *d,
2096 + u32 bpid,
2097 + const u64 *buffers,
2098 + unsigned int num_buffers)
2099 +{
2100 + struct qbman_release_desc rd;
2101 +
2102 + d = service_select(d);
2103 + if (!d)
2104 + return -ENODEV;
2105 +
2106 + qbman_release_desc_clear(&rd);
2107 + qbman_release_desc_set_bpid(&rd, bpid);
2108 +
2109 + return qbman_swp_release(d->swp, &rd, buffers, num_buffers);
2110 +}
2111 +EXPORT_SYMBOL(dpaa2_io_service_release);
2112 +
2113 +/**
2114 + * dpaa2_io_service_acquire() - Acquire buffers from a buffer pool.
2115 + * @d: the given DPIO object.
2116 + * @bpid: the buffer pool id.
2117 + * @buffers: the buffer addresses for acquired buffers.
2118 + * @num_buffers: the expected number of the buffers to acquire.
2119 + *
2120 + * Return a negative error code if the command failed, otherwise it returns
2121 + * the number of buffers acquired, which may be less than the number requested.
2122 + * Eg. if the buffer pool is empty, this will return zero.
2123 + */
2124 +int dpaa2_io_service_acquire(struct dpaa2_io *d,
2125 + u32 bpid,
2126 + u64 *buffers,
2127 + unsigned int num_buffers)
2128 +{
2129 + unsigned long irqflags;
2130 + int err;
2131 +
2132 + d = service_select(d);
2133 + if (!d)
2134 + return -ENODEV;
2135 +
2136 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2137 + err = qbman_swp_acquire(d->swp, bpid, buffers, num_buffers);
2138 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2139 +
2140 + return err;
2141 +}
2142 +EXPORT_SYMBOL(dpaa2_io_service_acquire);
2143 +
2144 +/*
2145 + * 'Stores' are reusable memory blocks for holding dequeue results, and to
2146 + * assist with parsing those results.
2147 + */
2148 +
2149 +/**
2150 + * dpaa2_io_store_create() - Create the dma memory storage for dequeue result.
2151 + * @max_frames: the maximum number of dequeued result for frames, must be <= 16.
2152 + * @dev: the device to allow mapping/unmapping the DMAable region.
2153 + *
2154 + * The size of the storage is "max_frames*sizeof(struct dpaa2_dq)".
2155 + * The 'dpaa2_io_store' returned is a DPIO service managed object.
2156 + *
2157 + * Return pointer to dpaa2_io_store struct for successfuly created storage
2158 + * memory, or NULL on error.
2159 + */
2160 +struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
2161 + struct device *dev)
2162 +{
2163 + struct dpaa2_io_store *ret;
2164 + size_t size;
2165 +
2166 + if (!max_frames || (max_frames > 16))
2167 + return NULL;
2168 +
2169 + ret = kmalloc(sizeof(*ret), GFP_KERNEL);
2170 + if (!ret)
2171 + return NULL;
2172 +
2173 + ret->max = max_frames;
2174 + size = max_frames * sizeof(struct dpaa2_dq) + 64;
2175 + ret->alloced_addr = kzalloc(size, GFP_KERNEL);
2176 + if (!ret->alloced_addr) {
2177 + kfree(ret);
2178 + return NULL;
2179 + }
2180 +
2181 + ret->vaddr = PTR_ALIGN(ret->alloced_addr, 64);
2182 + ret->paddr = dma_map_single(dev, ret->vaddr,
2183 + sizeof(struct dpaa2_dq) * max_frames,
2184 + DMA_FROM_DEVICE);
2185 + if (dma_mapping_error(dev, ret->paddr)) {
2186 + kfree(ret->alloced_addr);
2187 + kfree(ret);
2188 + return NULL;
2189 + }
2190 +
2191 + ret->idx = 0;
2192 + ret->dev = dev;
2193 +
2194 + return ret;
2195 +}
2196 +EXPORT_SYMBOL(dpaa2_io_store_create);
2197 +
2198 +/**
2199 + * dpaa2_io_store_destroy() - Frees the dma memory storage for dequeue
2200 + * result.
2201 + * @s: the storage memory to be destroyed.
2202 + */
2203 +void dpaa2_io_store_destroy(struct dpaa2_io_store *s)
2204 +{
2205 + dma_unmap_single(s->dev, s->paddr, sizeof(struct dpaa2_dq) * s->max,
2206 + DMA_FROM_DEVICE);
2207 + kfree(s->alloced_addr);
2208 + kfree(s);
2209 +}
2210 +EXPORT_SYMBOL(dpaa2_io_store_destroy);
2211 +
2212 +/**
2213 + * dpaa2_io_store_next() - Determine when the next dequeue result is available.
2214 + * @s: the dpaa2_io_store object.
2215 + * @is_last: indicate whether this is the last frame in the pull command.
2216 + *
2217 + * When an object driver performs dequeues to a dpaa2_io_store, this function
2218 + * can be used to determine when the next frame result is available. Once
2219 + * this function returns non-NULL, a subsequent call to it will try to find
2220 + * the next dequeue result.
2221 + *
2222 + * Note that if a pull-dequeue has a NULL result because the target FQ/channel
2223 + * was empty, then this function will also return NULL (rather than expecting
2224 + * the caller to always check for this. As such, "is_last" can be used to
2225 + * differentiate between "end-of-empty-dequeue" and "still-waiting".
2226 + *
2227 + * Return dequeue result for a valid dequeue result, or NULL for empty dequeue.
2228 + */
2229 +struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last)
2230 +{
2231 + int match;
2232 + struct dpaa2_dq *ret = &s->vaddr[s->idx];
2233 +
2234 + match = qbman_result_has_new_result(s->swp, ret);
2235 + if (!match) {
2236 + *is_last = 0;
2237 + return NULL;
2238 + }
2239 +
2240 + s->idx++;
2241 +
2242 + if (dpaa2_dq_is_pull_complete(ret)) {
2243 + *is_last = 1;
2244 + s->idx = 0;
2245 + /*
2246 + * If we get an empty dequeue result to terminate a zero-results
2247 + * vdqcr, return NULL to the caller rather than expecting him to
2248 + * check non-NULL results every time.
2249 + */
2250 + if (!(dpaa2_dq_flags(ret) & DPAA2_DQ_STAT_VALIDFRAME))
2251 + ret = NULL;
2252 + } else {
2253 + *is_last = 0;
2254 + }
2255 +
2256 + return ret;
2257 +}
2258 +EXPORT_SYMBOL(dpaa2_io_store_next);
2259 +
2260 +#ifdef CONFIG_FSL_QBMAN_DEBUG
2261 +/**
2262 + * dpaa2_io_query_fq_count() - Get the frame and byte count for a given fq.
2263 + * @d: the given DPIO object.
2264 + * @fqid: the id of frame queue to be queried.
2265 + * @fcnt: the queried frame count.
2266 + * @bcnt: the queried byte count.
2267 + *
2268 + * Knowing the FQ count at run-time can be useful in debugging situations.
2269 + * The instantaneous frame- and byte-count are hereby returned.
2270 + *
2271 + * Return 0 for a successful query, and negative error code if query fails.
2272 + */
2273 +int dpaa2_io_query_fq_count(struct dpaa2_io *d, uint32_t fqid,
2274 + u32 *fcnt, u32 *bcnt)
2275 +{
2276 + struct qbman_attr state;
2277 + struct qbman_swp *swp;
2278 + unsigned long irqflags;
2279 + int ret;
2280 +
2281 + d = service_select(d);
2282 + if (!d)
2283 + return -ENODEV;
2284 +
2285 + swp = d->swp;
2286 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2287 + ret = qbman_fq_query_state(swp, fqid, &state);
2288 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2289 + if (ret)
2290 + return ret;
2291 + *fcnt = qbman_fq_state_frame_count(&state);
2292 + *bcnt = qbman_fq_state_byte_count(&state);
2293 +
2294 + return 0;
2295 +}
2296 +EXPORT_SYMBOL(dpaa2_io_query_fq_count);
2297 +
2298 +/**
2299 + * dpaa2_io_query_bp_count() - Query the number of buffers currenty in a
2300 + * buffer pool.
2301 + * @d: the given DPIO object.
2302 + * @bpid: the index of buffer pool to be queried.
2303 + * @num: the queried number of buffers in the buffer pool.
2304 + *
2305 + * Return 0 for a sucessful query, and negative error code if query fails.
2306 + */
2307 +int dpaa2_io_query_bp_count(struct dpaa2_io *d, uint32_t bpid, u32 *num)
2308 +{
2309 + struct qbman_attr state;
2310 + struct qbman_swp *swp;
2311 + unsigned long irqflags;
2312 + int ret;
2313 +
2314 + d = service_select(d);
2315 + if (!d)
2316 + return -ENODEV;
2317 +
2318 + swp = d->swp;
2319 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2320 + ret = qbman_bp_query(swp, bpid, &state);
2321 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2322 + if (ret)
2323 + return ret;
2324 + *num = qbman_bp_info_num_free_bufs(&state);
2325 + return 0;
2326 +}
2327 +EXPORT_SYMBOL(dpaa2_io_query_bp_count);
2328 +#endif
2329 --- /dev/null
2330 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c
2331 @@ -0,0 +1,224 @@
2332 +/*
2333 + * Copyright 2013-2016 Freescale Semiconductor Inc.
2334 + * Copyright 2016 NXP
2335 + *
2336 + * Redistribution and use in source and binary forms, with or without
2337 + * modification, are permitted provided that the following conditions are met:
2338 + * * Redistributions of source code must retain the above copyright
2339 + * notice, this list of conditions and the following disclaimer.
2340 + * * Redistributions in binary form must reproduce the above copyright
2341 + * notice, this list of conditions and the following disclaimer in the
2342 + * documentation and/or other materials provided with the distribution.
2343 + * * Neither the name of the above-listed copyright holders nor the
2344 + * names of any contributors may be used to endorse or promote products
2345 + * derived from this software without specific prior written permission.
2346 + *
2347 + * ALTERNATIVELY, this software may be distributed under the terms of the
2348 + * GNU General Public License ("GPL") as published by the Free Software
2349 + * Foundation, either version 2 of that License or (at your option) any
2350 + * later version.
2351 + *
2352 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2353 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2354 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2355 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
2356 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2357 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2358 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2359 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2360 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2361 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2362 + * POSSIBILITY OF SUCH DAMAGE.
2363 + */
2364 +#include "../../include/mc-sys.h"
2365 +#include "../../include/mc-cmd.h"
2366 +
2367 +#include "dpio.h"
2368 +#include "dpio-cmd.h"
2369 +
2370 +/*
2371 + * Data Path I/O Portal API
2372 + * Contains initialization APIs and runtime control APIs for DPIO
2373 + */
2374 +
2375 +/**
2376 + * dpio_open() - Open a control session for the specified object
2377 + * @mc_io: Pointer to MC portal's I/O object
2378 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2379 + * @dpio_id: DPIO unique ID
2380 + * @token: Returned token; use in subsequent API calls
2381 + *
2382 + * This function can be used to open a control session for an
2383 + * already created object; an object may have been declared in
2384 + * the DPL or by calling the dpio_create() function.
2385 + * This function returns a unique authentication token,
2386 + * associated with the specific object ID and the specific MC
2387 + * portal; this token must be used in all subsequent commands for
2388 + * this specific object.
2389 + *
2390 + * Return: '0' on Success; Error code otherwise.
2391 + */
2392 +int dpio_open(struct fsl_mc_io *mc_io,
2393 + u32 cmd_flags,
2394 + int dpio_id,
2395 + u16 *token)
2396 +{
2397 + struct mc_command cmd = { 0 };
2398 + struct dpio_cmd_open *dpio_cmd;
2399 + int err;
2400 +
2401 + /* prepare command */
2402 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN,
2403 + cmd_flags,
2404 + 0);
2405 + dpio_cmd = (struct dpio_cmd_open *)cmd.params;
2406 + dpio_cmd->dpio_id = cpu_to_le32(dpio_id);
2407 +
2408 + err = mc_send_command(mc_io, &cmd);
2409 + if (err)
2410 + return err;
2411 +
2412 + /* retrieve response parameters */
2413 + *token = mc_cmd_hdr_read_token(&cmd);
2414 +
2415 + return 0;
2416 +}
2417 +
2418 +/**
2419 + * dpio_close() - Close the control session of the object
2420 + * @mc_io: Pointer to MC portal's I/O object
2421 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2422 + * @token: Token of DPIO object
2423 + *
2424 + * Return: '0' on Success; Error code otherwise.
2425 + */
2426 +int dpio_close(struct fsl_mc_io *mc_io,
2427 + u32 cmd_flags,
2428 + u16 token)
2429 +{
2430 + struct mc_command cmd = { 0 };
2431 +
2432 + /* prepare command */
2433 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE,
2434 + cmd_flags,
2435 + token);
2436 +
2437 + return mc_send_command(mc_io, &cmd);
2438 +}
2439 +
2440 +/**
2441 + * dpio_enable() - Enable the DPIO, allow I/O portal operations.
2442 + * @mc_io: Pointer to MC portal's I/O object
2443 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2444 + * @token: Token of DPIO object
2445 + *
2446 + * Return: '0' on Success; Error code otherwise
2447 + */
2448 +int dpio_enable(struct fsl_mc_io *mc_io,
2449 + u32 cmd_flags,
2450 + u16 token)
2451 +{
2452 + struct mc_command cmd = { 0 };
2453 +
2454 + /* prepare command */
2455 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE,
2456 + cmd_flags,
2457 + token);
2458 +
2459 + return mc_send_command(mc_io, &cmd);
2460 +}
2461 +
2462 +/**
2463 + * dpio_disable() - Disable the DPIO, stop any I/O portal operation.
2464 + * @mc_io: Pointer to MC portal's I/O object
2465 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2466 + * @token: Token of DPIO object
2467 + *
2468 + * Return: '0' on Success; Error code otherwise
2469 + */
2470 +int dpio_disable(struct fsl_mc_io *mc_io,
2471 + u32 cmd_flags,
2472 + u16 token)
2473 +{
2474 + struct mc_command cmd = { 0 };
2475 +
2476 + /* prepare command */
2477 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE,
2478 + cmd_flags,
2479 + token);
2480 +
2481 + return mc_send_command(mc_io, &cmd);
2482 +}
2483 +
2484 +/**
2485 + * dpio_get_attributes() - Retrieve DPIO attributes
2486 + * @mc_io: Pointer to MC portal's I/O object
2487 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2488 + * @token: Token of DPIO object
2489 + * @attr: Returned object's attributes
2490 + *
2491 + * Return: '0' on Success; Error code otherwise
2492 + */
2493 +int dpio_get_attributes(struct fsl_mc_io *mc_io,
2494 + u32 cmd_flags,
2495 + u16 token,
2496 + struct dpio_attr *attr)
2497 +{
2498 + struct mc_command cmd = { 0 };
2499 + struct dpio_rsp_get_attr *dpio_rsp;
2500 + int err;
2501 +
2502 + /* prepare command */
2503 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR,
2504 + cmd_flags,
2505 + token);
2506 +
2507 + err = mc_send_command(mc_io, &cmd);
2508 + if (err)
2509 + return err;
2510 +
2511 + /* retrieve response parameters */
2512 + dpio_rsp = (struct dpio_rsp_get_attr *)cmd.params;
2513 + attr->id = le32_to_cpu(dpio_rsp->id);
2514 + attr->qbman_portal_id = le16_to_cpu(dpio_rsp->qbman_portal_id);
2515 + attr->num_priorities = dpio_rsp->num_priorities;
2516 + attr->channel_mode = dpio_rsp->channel_mode & DPIO_CHANNEL_MODE_MASK;
2517 + attr->qbman_portal_ce_offset =
2518 + le64_to_cpu(dpio_rsp->qbman_portal_ce_addr);
2519 + attr->qbman_portal_ci_offset =
2520 + le64_to_cpu(dpio_rsp->qbman_portal_ci_addr);
2521 + attr->qbman_version = le32_to_cpu(dpio_rsp->qbman_version);
2522 +
2523 + return 0;
2524 +}
2525 +
2526 +/**
2527 + * dpio_get_api_version - Get Data Path I/O API version
2528 + * @mc_io: Pointer to MC portal's DPIO object
2529 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2530 + * @major_ver: Major version of DPIO API
2531 + * @minor_ver: Minor version of DPIO API
2532 + *
2533 + * Return: '0' on Success; Error code otherwise
2534 + */
2535 +int dpio_get_api_version(struct fsl_mc_io *mc_io,
2536 + u32 cmd_flags,
2537 + u16 *major_ver,
2538 + u16 *minor_ver)
2539 +{
2540 + struct mc_command cmd = { 0 };
2541 + int err;
2542 +
2543 + /* prepare command */
2544 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION,
2545 + cmd_flags, 0);
2546 +
2547 + err = mc_send_command(mc_io, &cmd);
2548 + if (err)
2549 + return err;
2550 +
2551 + /* retrieve response parameters */
2552 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
2553 +
2554 + return 0;
2555 +}
2556 --- /dev/null
2557 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.h
2558 @@ -0,0 +1,109 @@
2559 +/*
2560 + * Copyright 2013-2016 Freescale Semiconductor Inc.
2561 + * Copyright 2016 NXP
2562 + *
2563 + * Redistribution and use in source and binary forms, with or without
2564 + * modification, are permitted provided that the following conditions are met:
2565 + * * Redistributions of source code must retain the above copyright
2566 + * notice, this list of conditions and the following disclaimer.
2567 + * * Redistributions in binary form must reproduce the above copyright
2568 + * notice, this list of conditions and the following disclaimer in the
2569 + * documentation and/or other materials provided with the distribution.
2570 + * * Neither the name of the above-listed copyright holders nor the
2571 + * names of any contributors may be used to endorse or promote products
2572 + * derived from this software without specific prior written permission.
2573 + *
2574 + * ALTERNATIVELY, this software may be distributed under the terms of the
2575 + * GNU General Public License ("GPL") as published by the Free Software
2576 + * Foundation, either version 2 of that License or (at your option) any
2577 + * later version.
2578 + *
2579 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2580 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2581 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2582 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
2583 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2584 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2585 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2586 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2587 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2588 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2589 + * POSSIBILITY OF SUCH DAMAGE.
2590 + */
2591 +#ifndef __FSL_DPIO_H
2592 +#define __FSL_DPIO_H
2593 +
2594 +struct fsl_mc_io;
2595 +
2596 +int dpio_open(struct fsl_mc_io *mc_io,
2597 + u32 cmd_flags,
2598 + int dpio_id,
2599 + u16 *token);
2600 +
2601 +int dpio_close(struct fsl_mc_io *mc_io,
2602 + u32 cmd_flags,
2603 + u16 token);
2604 +
2605 +/**
2606 + * enum dpio_channel_mode - DPIO notification channel mode
2607 + * @DPIO_NO_CHANNEL: No support for notification channel
2608 + * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a
2609 + * dedicated channel in the DPIO; user should point the queue's
2610 + * destination in the relevant interface to this DPIO
2611 + */
2612 +enum dpio_channel_mode {
2613 + DPIO_NO_CHANNEL = 0,
2614 + DPIO_LOCAL_CHANNEL = 1,
2615 +};
2616 +
2617 +/**
2618 + * struct dpio_cfg - Structure representing DPIO configuration
2619 + * @channel_mode: Notification channel mode
2620 + * @num_priorities: Number of priorities for the notification channel (1-8);
2621 + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
2622 + */
2623 +struct dpio_cfg {
2624 + enum dpio_channel_mode channel_mode;
2625 + u8 num_priorities;
2626 +};
2627 +
2628 +int dpio_enable(struct fsl_mc_io *mc_io,
2629 + u32 cmd_flags,
2630 + u16 token);
2631 +
2632 +int dpio_disable(struct fsl_mc_io *mc_io,
2633 + u32 cmd_flags,
2634 + u16 token);
2635 +
2636 +/**
2637 + * struct dpio_attr - Structure representing DPIO attributes
2638 + * @id: DPIO object ID
2639 + * @qbman_portal_ce_offset: offset of the software portal cache-enabled area
2640 + * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area
2641 + * @qbman_portal_id: Software portal ID
2642 + * @channel_mode: Notification channel mode
2643 + * @num_priorities: Number of priorities for the notification channel (1-8);
2644 + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
2645 + * @qbman_version: QBMAN version
2646 + */
2647 +struct dpio_attr {
2648 + int id;
2649 + u64 qbman_portal_ce_offset;
2650 + u64 qbman_portal_ci_offset;
2651 + u16 qbman_portal_id;
2652 + enum dpio_channel_mode channel_mode;
2653 + u8 num_priorities;
2654 + u32 qbman_version;
2655 +};
2656 +
2657 +int dpio_get_attributes(struct fsl_mc_io *mc_io,
2658 + u32 cmd_flags,
2659 + u16 token,
2660 + struct dpio_attr *attr);
2661 +
2662 +int dpio_get_api_version(struct fsl_mc_io *mc_io,
2663 + u32 cmd_flags,
2664 + u16 *major_ver,
2665 + u16 *minor_ver);
2666 +
2667 +#endif /* __FSL_DPIO_H */
2668 --- /dev/null
2669 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
2670 @@ -0,0 +1,1049 @@
2671 +/*
2672 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
2673 + * Copyright 2016 NXP
2674 + *
2675 + * Redistribution and use in source and binary forms, with or without
2676 + * modification, are permitted provided that the following conditions are met:
2677 + * * Redistributions of source code must retain the above copyright
2678 + * notice, this list of conditions and the following disclaimer.
2679 + * * Redistributions in binary form must reproduce the above copyright
2680 + * notice, this list of conditions and the following disclaimer in the
2681 + * documentation and/or other materials provided with the distribution.
2682 + * * Neither the name of Freescale Semiconductor nor the
2683 + * names of its contributors may be used to endorse or promote products
2684 + * derived from this software without specific prior written permission.
2685 + *
2686 + * ALTERNATIVELY, this software may be distributed under the terms of the
2687 + * GNU General Public License ("GPL") as published by the Free Software
2688 + * Foundation, either version 2 of that License or (at your option) any
2689 + * later version.
2690 + *
2691 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
2692 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
2693 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
2694 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
2695 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
2696 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
2697 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
2698 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2699 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
2700 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2701 + */
2702 +
2703 +#include <asm/cacheflush.h>
2704 +#include <linux/io.h>
2705 +#include <linux/slab.h>
2706 +#include "../../include/dpaa2-global.h"
2707 +
2708 +#include "qbman-portal.h"
2709 +
2710 +struct qb_attr_code code_generic_verb = QB_CODE(0, 0, 7);
2711 +struct qb_attr_code code_generic_rslt = QB_CODE(0, 8, 8);
2712 +
2713 +#define QMAN_REV_4000 0x04000000
2714 +#define QMAN_REV_4100 0x04010000
2715 +#define QMAN_REV_4101 0x04010001
2716 +#define QMAN_REV_MASK 0xffff0000
2717 +
2718 +/* All QBMan command and result structures use this "valid bit" encoding */
2719 +#define QB_VALID_BIT ((u32)0x80)
2720 +
2721 +/* QBMan portal management command codes */
2722 +#define QBMAN_MC_ACQUIRE 0x30
2723 +#define QBMAN_WQCHAN_CONFIGURE 0x46
2724 +
2725 +/* CINH register offsets */
2726 +#define QBMAN_CINH_SWP_EQAR 0x8c0
2727 +#define QBMAN_CINH_SWP_DQPI 0xa00
2728 +#define QBMAN_CINH_SWP_DCAP 0xac0
2729 +#define QBMAN_CINH_SWP_SDQCR 0xb00
2730 +#define QBMAN_CINH_SWP_RAR 0xcc0
2731 +#define QBMAN_CINH_SWP_ISR 0xe00
2732 +#define QBMAN_CINH_SWP_IER 0xe40
2733 +#define QBMAN_CINH_SWP_ISDR 0xe80
2734 +#define QBMAN_CINH_SWP_IIR 0xec0
2735 +
2736 +/* CENA register offsets */
2737 +#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((u32)(n) << 6))
2738 +#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((u32)(n) << 6))
2739 +#define QBMAN_CENA_SWP_RCR(n) (0x400 + ((u32)(n) << 6))
2740 +#define QBMAN_CENA_SWP_CR 0x600
2741 +#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((u32)(vb) >> 1))
2742 +#define QBMAN_CENA_SWP_VDQCR 0x780
2743 +
2744 +/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
2745 +#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)(p) & 0x1ff) >> 6)
2746 +
2747 +/* Define token used to determine if response written to memory is valid */
2748 +#define QMAN_DQ_TOKEN_VALID 1
2749 +
2750 +/* SDQCR attribute codes */
2751 +#define QB_SDQCR_FC_SHIFT 29
2752 +#define QB_SDQCR_FC_MASK 0x1
2753 +#define QB_SDQCR_DCT_SHIFT 24
2754 +#define QB_SDQCR_DCT_MASK 0x3
2755 +#define QB_SDQCR_TOK_SHIFT 16
2756 +#define QB_SDQCR_TOK_MASK 0xff
2757 +#define QB_SDQCR_SRC_SHIFT 0
2758 +#define QB_SDQCR_SRC_MASK 0xffff
2759 +
2760 +/* opaque token for static dequeues */
2761 +#define QMAN_SDQCR_TOKEN 0xbb
2762 +
2763 +enum qbman_sdqcr_dct {
2764 + qbman_sdqcr_dct_null = 0,
2765 + qbman_sdqcr_dct_prio_ics,
2766 + qbman_sdqcr_dct_active_ics,
2767 + qbman_sdqcr_dct_active
2768 +};
2769 +
2770 +enum qbman_sdqcr_fc {
2771 + qbman_sdqcr_fc_one = 0,
2772 + qbman_sdqcr_fc_up_to_3 = 1
2773 +};
2774 +
2775 +#define dccvac(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); }
2776 +#define dcivac(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); }
2777 +static inline void qbman_inval_prefetch(struct qbman_swp *p, uint32_t offset)
2778 +{
2779 + dcivac(p->addr_cena + offset);
2780 + prefetch(p->addr_cena + offset);
2781 +}
2782 +
2783 +/* Portal Access */
2784 +
2785 +static inline u32 qbman_read_register(struct qbman_swp *p, u32 offset)
2786 +{
2787 + return readl_relaxed(p->addr_cinh + offset);
2788 +}
2789 +
2790 +static inline void qbman_write_register(struct qbman_swp *p, u32 offset,
2791 + u32 value)
2792 +{
2793 + writel_relaxed(value, p->addr_cinh + offset);
2794 +}
2795 +
2796 +static inline void *qbman_get_cmd(struct qbman_swp *p, u32 offset)
2797 +{
2798 + return p->addr_cena + offset;
2799 +}
2800 +
2801 +#define QBMAN_CINH_SWP_CFG 0xd00
2802 +
2803 +#define SWP_CFG_DQRR_MF_SHIFT 20
2804 +#define SWP_CFG_EST_SHIFT 16
2805 +#define SWP_CFG_WN_SHIFT 14
2806 +#define SWP_CFG_RPM_SHIFT 12
2807 +#define SWP_CFG_DCM_SHIFT 10
2808 +#define SWP_CFG_EPM_SHIFT 8
2809 +#define SWP_CFG_SD_SHIFT 5
2810 +#define SWP_CFG_SP_SHIFT 4
2811 +#define SWP_CFG_SE_SHIFT 3
2812 +#define SWP_CFG_DP_SHIFT 2
2813 +#define SWP_CFG_DE_SHIFT 1
2814 +#define SWP_CFG_EP_SHIFT 0
2815 +
2816 +static inline u32 qbman_set_swp_cfg(u8 max_fill, u8 wn, u8 est, u8 rpm, u8 dcm,
2817 + u8 epm, int sd, int sp, int se,
2818 + int dp, int de, int ep)
2819 +{
2820 + return cpu_to_le32 (max_fill << SWP_CFG_DQRR_MF_SHIFT |
2821 + est << SWP_CFG_EST_SHIFT |
2822 + wn << SWP_CFG_WN_SHIFT |
2823 + rpm << SWP_CFG_RPM_SHIFT |
2824 + dcm << SWP_CFG_DCM_SHIFT |
2825 + epm << SWP_CFG_EPM_SHIFT |
2826 + sd << SWP_CFG_SD_SHIFT |
2827 + sp << SWP_CFG_SP_SHIFT |
2828 + se << SWP_CFG_SE_SHIFT |
2829 + dp << SWP_CFG_DP_SHIFT |
2830 + de << SWP_CFG_DE_SHIFT |
2831 + ep << SWP_CFG_EP_SHIFT);
2832 +}
2833 +
2834 +/**
2835 + * qbman_swp_init() - Create a functional object representing the given
2836 + * QBMan portal descriptor.
2837 + * @d: the given qbman swp descriptor
2838 + *
2839 + * Return qbman_swp portal for success, NULL if the object cannot
2840 + * be created.
2841 + */
2842 +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
2843 +{
2844 + struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL);
2845 + u32 reg;
2846 +
2847 + if (!p)
2848 + return NULL;
2849 + p->desc = d;
2850 + p->mc.valid_bit = QB_VALID_BIT;
2851 + p->sdq = 0;
2852 + p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT;
2853 + p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT;
2854 + p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT;
2855 +
2856 + atomic_set(&p->vdq.available, 1);
2857 + p->vdq.valid_bit = QB_VALID_BIT;
2858 + p->dqrr.next_idx = 0;
2859 + p->dqrr.valid_bit = QB_VALID_BIT;
2860 +
2861 + if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_4100) {
2862 + p->dqrr.dqrr_size = 4;
2863 + p->dqrr.reset_bug = 1;
2864 + } else {
2865 + p->dqrr.dqrr_size = 8;
2866 + p->dqrr.reset_bug = 0;
2867 + }
2868 +
2869 + p->addr_cena = d->cena_bar;
2870 + p->addr_cinh = d->cinh_bar;
2871 +
2872 + reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
2873 + 0, /* Writes cacheable */
2874 + 0, /* EQCR_CI stashing threshold */
2875 + 3, /* RPM: Valid bit mode, RCR in array mode */
2876 + 2, /* DCM: Discrete consumption ack mode */
2877 + 3, /* EPM: Valid bit mode, EQCR in array mode */
2878 + 0, /* mem stashing drop enable == FALSE */
2879 + 1, /* mem stashing priority == TRUE */
2880 + 0, /* mem stashing enable == FALSE */
2881 + 1, /* dequeue stashing priority == TRUE */
2882 + 0, /* dequeue stashing enable == FALSE */
2883 + 0); /* EQCR_CI stashing priority == FALSE */
2884 +
2885 + qbman_write_register(p, QBMAN_CINH_SWP_CFG, reg);
2886 + reg = qbman_read_register(p, QBMAN_CINH_SWP_CFG);
2887 + if (!reg) {
2888 + pr_err("qbman: the portal is not enabled!\n");
2889 + return NULL;
2890 + }
2891 +
2892 + /*
2893 + * SDQCR needs to be initialized to 0 when no channels are
2894 + * being dequeued from or else the QMan HW will indicate an
2895 + * error. The values that were calculated above will be
2896 + * applied when dequeues from a specific channel are enabled.
2897 + */
2898 + qbman_write_register(p, QBMAN_CINH_SWP_SDQCR, 0);
2899 + return p;
2900 +}
2901 +
2902 +/**
2903 + * qbman_swp_finish() - Create and destroy a functional object representing
2904 + * the given QBMan portal descriptor.
2905 + * @p: the qbman_swp object to be destroyed
2906 + */
2907 +void qbman_swp_finish(struct qbman_swp *p)
2908 +{
2909 + kfree(p);
2910 +}
2911 +
2912 +/**
2913 + * qbman_swp_interrupt_read_status()
2914 + * @p: the given software portal
2915 + *
2916 + * Return the value in the SWP_ISR register.
2917 + */
2918 +u32 qbman_swp_interrupt_read_status(struct qbman_swp *p)
2919 +{
2920 + return qbman_read_register(p, QBMAN_CINH_SWP_ISR);
2921 +}
2922 +
2923 +/**
2924 + * qbman_swp_interrupt_clear_status()
2925 + * @p: the given software portal
2926 + * @mask: The mask to clear in SWP_ISR register
2927 + */
2928 +void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask)
2929 +{
2930 + qbman_write_register(p, QBMAN_CINH_SWP_ISR, mask);
2931 +}
2932 +
2933 +/**
2934 + * qbman_swp_interrupt_get_trigger() - read interrupt enable register
2935 + * @p: the given software portal
2936 + *
2937 + * Return the value in the SWP_IER register.
2938 + */
2939 +u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
2940 +{
2941 + return qbman_read_register(p, QBMAN_CINH_SWP_IER);
2942 +}
2943 +
2944 +/**
2945 + * qbman_swp_interrupt_set_trigger() - enable interrupts for a swp
2946 + * @p: the given software portal
2947 + * @mask: The mask of bits to enable in SWP_IER
2948 + */
2949 +void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask)
2950 +{
2951 + qbman_write_register(p, QBMAN_CINH_SWP_IER, mask);
2952 +}
2953 +
2954 +/**
2955 + * qbman_swp_interrupt_get_inhibit() - read interrupt mask register
2956 + * @p: the given software portal object
2957 + *
2958 + * Return the value in the SWP_IIR register.
2959 + */
2960 +int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p)
2961 +{
2962 + return qbman_read_register(p, QBMAN_CINH_SWP_IIR);
2963 +}
2964 +
2965 +/**
2966 + * qbman_swp_interrupt_set_inhibit() - write interrupt mask register
2967 + * @p: the given software portal object
2968 + * @mask: The mask to set in SWP_IIR register
2969 + */
2970 +void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit)
2971 +{
2972 + qbman_write_register(p, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0);
2973 +}
2974 +
2975 +/*
2976 + * Different management commands all use this common base layer of code to issue
2977 + * commands and poll for results.
2978 + */
2979 +
2980 +/*
2981 + * Returns a pointer to where the caller should fill in their management command
2982 + * (caller should ignore the verb byte)
2983 + */
2984 +void *qbman_swp_mc_start(struct qbman_swp *p)
2985 +{
2986 + return qbman_get_cmd(p, QBMAN_CENA_SWP_CR);
2987 +}
2988 +
2989 +/*
2990 + * Commits merges in the caller-supplied command verb (which should not include
2991 + * the valid-bit) and submits the command to hardware
2992 + */
2993 +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb)
2994 +{
2995 + u8 *v = cmd;
2996 +
2997 + dma_wmb();
2998 + *v = cmd_verb | p->mc.valid_bit;
2999 + dccvac(cmd);
3000 +}
3001 +
3002 +/*
3003 + * Checks for a completed response (returns non-NULL if only if the response
3004 + * is complete).
3005 + */
3006 +void *qbman_swp_mc_result(struct qbman_swp *p)
3007 +{
3008 + u32 *ret, verb;
3009 +
3010 + qbman_inval_prefetch(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
3011 + ret = qbman_get_cmd(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
3012 +
3013 + /* Remove the valid-bit - command completed if the rest is non-zero */
3014 + verb = ret[0] & ~QB_VALID_BIT;
3015 + if (!verb)
3016 + return NULL;
3017 + p->mc.valid_bit ^= QB_VALID_BIT;
3018 + return ret;
3019 +}
3020 +
3021 +#define QB_ENQUEUE_CMD_OPTIONS_SHIFT 0
3022 +enum qb_enqueue_commands {
3023 + enqueue_empty = 0,
3024 + enqueue_response_always = 1,
3025 + enqueue_rejects_to_fq = 2
3026 +};
3027 +
3028 +#define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT 2
3029 +#define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3
3030 +#define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT 4
3031 +
3032 +/**
3033 + * qbman_eq_desc_clear() - Clear the contents of a descriptor to
3034 + * default/starting state.
3035 + */
3036 +void qbman_eq_desc_clear(struct qbman_eq_desc *d)
3037 +{
3038 + memset(d, 0, sizeof(*d));
3039 +}
3040 +
3041 +/**
3042 + * qbman_eq_desc_set_no_orp() - Set enqueue descriptor without orp
3043 + * @d: the enqueue descriptor.
3044 + * @response_success: 1 = enqueue with response always; 0 = enqueue with
3045 + * rejections returned on a FQ.
3046 + */
3047 +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
3048 +{
3049 + d->verb &= ~(1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
3050 + if (respond_success)
3051 + d->verb |= enqueue_response_always;
3052 + else
3053 + d->verb |= enqueue_rejects_to_fq;
3054 +}
3055 +
3056 +/*
3057 + * Exactly one of the following descriptor "targets" should be set. (Calling any
3058 + * one of these will replace the effect of any prior call to one of these.)
3059 + * -enqueue to a frame queue
3060 + * -enqueue to a queuing destination
3061 + */
3062 +
3063 +/**
3064 + * qbman_eq_desc_set_fq() - set the FQ for the enqueue command
3065 + * @d: the enqueue descriptor
3066 + * @fqid: the id of the frame queue to be enqueued
3067 + */
3068 +void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid)
3069 +{
3070 + d->verb &= ~(1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT);
3071 + d->tgtid = cpu_to_le32(fqid);
3072 +}
3073 +
3074 +/**
3075 + * qbman_eq_desc_set_qd() - Set Queuing Destination for the enqueue command
3076 + * @d: the enqueue descriptor
3077 + * @qdid: the id of the queuing destination to be enqueued
3078 + * @qd_bin: the queuing destination bin
3079 + * @qd_prio: the queuing destination priority
3080 + */
3081 +void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
3082 + u32 qd_bin, u32 qd_prio)
3083 +{
3084 + d->verb |= 1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT;
3085 + d->tgtid = cpu_to_le32(qdid);
3086 + d->qdbin = cpu_to_le16(qd_bin);
3087 + d->qpri = qd_prio;
3088 +}
3089 +
3090 +#define EQAR_IDX(eqar) ((eqar) & 0x7)
3091 +#define EQAR_VB(eqar) ((eqar) & 0x80)
3092 +#define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
3093 +
3094 +/**
3095 + * qbman_swp_enqueue() - Issue an enqueue command
3096 + * @s: the software portal used for enqueue
3097 + * @d: the enqueue descriptor
3098 + * @fd: the frame descriptor to be enqueued
3099 + *
3100 + * Please note that 'fd' should only be NULL if the "action" of the
3101 + * descriptor is "orp_hole" or "orp_nesn".
3102 + *
3103 + * Return 0 for successful enqueue, -EBUSY if the EQCR is not ready.
3104 + */
3105 +int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
3106 + const struct dpaa2_fd *fd)
3107 +{
3108 + struct qbman_eq_desc *p;
3109 + u32 eqar = qbman_read_register(s, QBMAN_CINH_SWP_EQAR);
3110 +
3111 + if (!EQAR_SUCCESS(eqar))
3112 + return -EBUSY;
3113 +
3114 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
3115 + memcpy(&p->dca, &d->dca, 31);
3116 + memcpy(&p->fd, fd, sizeof(*fd));
3117 +
3118 + /* Set the verb byte, have to substitute in the valid-bit */
3119 + dma_wmb();
3120 + p->verb = d->verb | EQAR_VB(eqar);
3121 + dccvac(p);
3122 +
3123 + return 0;
3124 +}
3125 +
3126 +/* Static (push) dequeue */
3127 +
3128 +/**
3129 + * qbman_swp_push_get() - Get the push dequeue setup
3130 + * @p: the software portal object
3131 + * @channel_idx: the channel index to query
3132 + * @enabled: returned boolean to show whether the push dequeue is enabled
3133 + * for the given channel
3134 + */
3135 +void qbman_swp_push_get(struct qbman_swp *s, u8 channel_idx, int *enabled)
3136 +{
3137 + u16 src = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
3138 +
3139 + WARN_ON(channel_idx > 15);
3140 + *enabled = src | (1 << channel_idx);
3141 +}
3142 +
3143 +/**
3144 + * qbman_swp_push_set() - Enable or disable push dequeue
3145 + * @p: the software portal object
3146 + * @channel_idx: the channel index (0 to 15)
3147 + * @enable: enable or disable push dequeue
3148 + */
3149 +void qbman_swp_push_set(struct qbman_swp *s, u8 channel_idx, int enable)
3150 +{
3151 + u16 dqsrc;
3152 +
3153 + WARN_ON(channel_idx > 15);
3154 + if (enable)
3155 + s->sdq |= 1 << channel_idx;
3156 + else
3157 + s->sdq &= ~(1 << channel_idx);
3158 +
3159 + /* Read make the complete src map. If no channels are enabled
3160 + * the SDQCR must be 0 or else QMan will assert errors
3161 + */
3162 + dqsrc = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
3163 + if (dqsrc != 0)
3164 + qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, s->sdq);
3165 + else
3166 + qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, 0);
3167 +}
3168 +
3169 +#define QB_VDQCR_VERB_DCT_SHIFT 0
3170 +#define QB_VDQCR_VERB_DT_SHIFT 2
3171 +#define QB_VDQCR_VERB_RLS_SHIFT 4
3172 +#define QB_VDQCR_VERB_WAE_SHIFT 5
3173 +
3174 +enum qb_pull_dt_e {
3175 + qb_pull_dt_channel,
3176 + qb_pull_dt_workqueue,
3177 + qb_pull_dt_framequeue
3178 +};
3179 +
3180 +/**
3181 + * qbman_pull_desc_clear() - Clear the contents of a descriptor to
3182 + * default/starting state
3183 + * @d: the pull dequeue descriptor to be cleared
3184 + */
3185 +void qbman_pull_desc_clear(struct qbman_pull_desc *d)
3186 +{
3187 + memset(d, 0, sizeof(*d));
3188 +}
3189 +
3190 +/**
3191 + * qbman_pull_desc_set_storage()- Set the pull dequeue storage
3192 + * @d: the pull dequeue descriptor to be set
3193 + * @storage: the pointer of the memory to store the dequeue result
3194 + * @storage_phys: the physical address of the storage memory
3195 + * @stash: to indicate whether write allocate is enabled
3196 + *
3197 + * If not called, or if called with 'storage' as NULL, the result pull dequeues
3198 + * will produce results to DQRR. If 'storage' is non-NULL, then results are
3199 + * produced to the given memory location (using the DMA address which
3200 + * the caller provides in 'storage_phys'), and 'stash' controls whether or not
3201 + * those writes to main-memory express a cache-warming attribute.
3202 + */
3203 +void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
3204 + struct dpaa2_dq *storage,
3205 + dma_addr_t storage_phys,
3206 + int stash)
3207 +{
3208 + /* save the virtual address */
3209 + d->rsp_addr_virt = (u64)storage;
3210 +
3211 + if (!storage) {
3212 + d->verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
3213 + return;
3214 + }
3215 + d->verb |= 1 << QB_VDQCR_VERB_RLS_SHIFT;
3216 + if (stash)
3217 + d->verb |= 1 << QB_VDQCR_VERB_WAE_SHIFT;
3218 + else
3219 + d->verb &= ~(1 << QB_VDQCR_VERB_WAE_SHIFT);
3220 +
3221 + d->rsp_addr = cpu_to_le64(storage_phys);
3222 +}
3223 +
3224 +/**
3225 + * qbman_pull_desc_set_numframes() - Set the number of frames to be dequeued
3226 + * @d: the pull dequeue descriptor to be set
3227 + * @numframes: number of frames to be set, must be between 1 and 16, inclusive
3228 + */
3229 +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes)
3230 +{
3231 + d->numf = numframes - 1;
3232 +}
3233 +
3234 +void qbman_pull_desc_set_token(struct qbman_pull_desc *d, u8 token)
3235 +{
3236 + d->tok = token;
3237 +}
3238 +
3239 +/*
3240 + * Exactly one of the following descriptor "actions" should be set. (Calling any
3241 + * one of these will replace the effect of any prior call to one of these.)
3242 + * - pull dequeue from the given frame queue (FQ)
3243 + * - pull dequeue from any FQ in the given work queue (WQ)
3244 + * - pull dequeue from any FQ in any WQ in the given channel
3245 + */
3246 +
3247 +/**
3248 + * qbman_pull_desc_set_fq() - Set fqid from which the dequeue command dequeues
3249 + * @fqid: the frame queue index of the given FQ
3250 + */
3251 +void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid)
3252 +{
3253 + d->verb |= 1 << QB_VDQCR_VERB_DCT_SHIFT;
3254 + d->verb |= qb_pull_dt_framequeue << QB_VDQCR_VERB_DT_SHIFT;
3255 + d->dq_src = cpu_to_le32(fqid);
3256 +}
3257 +
3258 +/**
3259 + * qbman_pull_desc_set_wq() - Set wqid from which the dequeue command dequeues
3260 + * @wqid: composed of channel id and wqid within the channel
3261 + * @dct: the dequeue command type
3262 + */
3263 +void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
3264 + enum qbman_pull_type_e dct)
3265 +{
3266 + d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
3267 + d->verb |= qb_pull_dt_workqueue << QB_VDQCR_VERB_DT_SHIFT;
3268 + d->dq_src = cpu_to_le32(wqid);
3269 +}
3270 +
3271 +/**
3272 + * qbman_pull_desc_set_channel() - Set channelid from which the dequeue command
3273 + * dequeues
3274 + * @chid: the channel id to be dequeued
3275 + * @dct: the dequeue command type
3276 + */
3277 +void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
3278 + enum qbman_pull_type_e dct)
3279 +{
3280 + d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
3281 + d->verb |= qb_pull_dt_channel << QB_VDQCR_VERB_DT_SHIFT;
3282 + d->dq_src = cpu_to_le32(chid);
3283 +}
3284 +
3285 +/**
3286 + * qbman_swp_pull() - Issue the pull dequeue command
3287 + * @s: the software portal object
3288 + * @d: the software portal descriptor which has been configured with
3289 + * the set of qbman_pull_desc_set_*() calls
3290 + *
3291 + * Return 0 for success, and -EBUSY if the software portal is not ready
3292 + * to do pull dequeue.
3293 + */
3294 +int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
3295 +{
3296 + struct qbman_pull_desc *p;
3297 +
3298 + if (!atomic_dec_and_test(&s->vdq.available)) {
3299 + atomic_inc(&s->vdq.available);
3300 + return -EBUSY;
3301 + }
3302 + s->vdq.storage = (void *)d->rsp_addr_virt;
3303 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_VDQCR);
3304 + p->numf = d->numf;
3305 + p->tok = QMAN_DQ_TOKEN_VALID;
3306 + p->dq_src = d->dq_src;
3307 + p->rsp_addr = d->rsp_addr;
3308 + p->rsp_addr_virt = d->rsp_addr_virt;
3309 + dma_wmb();
3310 +
3311 + /* Set the verb byte, have to substitute in the valid-bit */
3312 + p->verb = d->verb | s->vdq.valid_bit;
3313 + s->vdq.valid_bit ^= QB_VALID_BIT;
3314 + dccvac(p);
3315 +
3316 + return 0;
3317 +}
3318 +
3319 +#define QMAN_DQRR_PI_MASK 0xf
3320 +
3321 +/**
3322 + * qbman_swp_dqrr_next() - Get an valid DQRR entry
3323 + * @s: the software portal object
3324 + *
3325 + * Return NULL if there are no unconsumed DQRR entries. Return a DQRR entry
3326 + * only once, so repeated calls can return a sequence of DQRR entries, without
3327 + * requiring they be consumed immediately or in any particular order.
3328 + */
3329 +const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s)
3330 +{
3331 + u32 verb;
3332 + u32 response_verb;
3333 + u32 flags;
3334 + struct dpaa2_dq *p;
3335 +
3336 + /* Before using valid-bit to detect if something is there, we have to
3337 + * handle the case of the DQRR reset bug...
3338 + */
3339 + if (unlikely(s->dqrr.reset_bug)) {
3340 + /*
3341 + * We pick up new entries by cache-inhibited producer index,
3342 + * which means that a non-coherent mapping would require us to
3343 + * invalidate and read *only* once that PI has indicated that
3344 + * there's an entry here. The first trip around the DQRR ring
3345 + * will be much less efficient than all subsequent trips around
3346 + * it...
3347 + */
3348 + u8 pi = qbman_read_register(s, QBMAN_CINH_SWP_DQPI) &
3349 + QMAN_DQRR_PI_MASK;
3350 +
3351 + /* there are new entries if pi != next_idx */
3352 + if (pi == s->dqrr.next_idx)
3353 + return NULL;
3354 +
3355 + /*
3356 + * if next_idx is/was the last ring index, and 'pi' is
3357 + * different, we can disable the workaround as all the ring
3358 + * entries have now been DMA'd to so valid-bit checking is
3359 + * repaired. Note: this logic needs to be based on next_idx
3360 + * (which increments one at a time), rather than on pi (which
3361 + * can burst and wrap-around between our snapshots of it).
3362 + */
3363 + if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1)) {
3364 + pr_debug("next_idx=%d, pi=%d, clear reset bug\n",
3365 + s->dqrr.next_idx, pi);
3366 + s->dqrr.reset_bug = 0;
3367 + }
3368 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3369 + }
3370 +
3371 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3372 + verb = p->dq.verb;
3373 +
3374 + /*
3375 + * If the valid-bit isn't of the expected polarity, nothing there. Note,
3376 + * in the DQRR reset bug workaround, we shouldn't need to skip these
3377 + * check, because we've already determined that a new entry is available
3378 + * and we've invalidated the cacheline before reading it, so the
3379 + * valid-bit behaviour is repaired and should tell us what we already
3380 + * knew from reading PI.
3381 + */
3382 + if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
3383 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3384 + return NULL;
3385 + }
3386 + /*
3387 + * There's something there. Move "next_idx" attention to the next ring
3388 + * entry (and prefetch it) before returning what we found.
3389 + */
3390 + s->dqrr.next_idx++;
3391 + s->dqrr.next_idx &= s->dqrr.dqrr_size - 1; /* Wrap around */
3392 + if (!s->dqrr.next_idx)
3393 + s->dqrr.valid_bit ^= QB_VALID_BIT;
3394 +
3395 + /*
3396 + * If this is the final response to a volatile dequeue command
3397 + * indicate that the vdq is available
3398 + */
3399 + flags = p->dq.stat;
3400 + response_verb = verb & QBMAN_RESULT_MASK;
3401 + if ((response_verb == QBMAN_RESULT_DQ) &&
3402 + (flags & DPAA2_DQ_STAT_VOLATILE) &&
3403 + (flags & DPAA2_DQ_STAT_EXPIRED))
3404 + atomic_inc(&s->vdq.available);
3405 +
3406 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3407 +
3408 + return p;
3409 +}
3410 +
3411 +/**
3412 + * qbman_swp_dqrr_consume() - Consume DQRR entries previously returned from
3413 + * qbman_swp_dqrr_next().
3414 + * @s: the software portal object
3415 + * @dq: the DQRR entry to be consumed
3416 + */
3417 +void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq)
3418 +{
3419 + qbman_write_register(s, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
3420 +}
3421 +
3422 +/**
3423 + * qbman_result_has_new_result() - Check and get the dequeue response from the
3424 + * dq storage memory set in pull dequeue command
3425 + * @s: the software portal object
3426 + * @dq: the dequeue result read from the memory
3427 + *
3428 + * Return 1 for getting a valid dequeue result, or 0 for not getting a valid
3429 + * dequeue result.
3430 + *
3431 + * Only used for user-provided storage of dequeue results, not DQRR. For
3432 + * efficiency purposes, the driver will perform any required endianness
3433 + * conversion to ensure that the user's dequeue result storage is in host-endian
3434 + * format. As such, once the user has called qbman_result_has_new_result() and
3435 + * been returned a valid dequeue result, they should not call it again on
3436 + * the same memory location (except of course if another dequeue command has
3437 + * been executed to produce a new result to that location).
3438 + */
3439 +int qbman_result_has_new_result(struct qbman_swp *s, const struct dpaa2_dq *dq)
3440 +{
3441 + if (dq->dq.tok != QMAN_DQ_TOKEN_VALID)
3442 + return 0;
3443 +
3444 + /*
3445 + * Set token to be 0 so we will detect change back to 1
3446 + * next time the looping is traversed. Const is cast away here
3447 + * as we want users to treat the dequeue responses as read only.
3448 + */
3449 + ((struct dpaa2_dq *)dq)->dq.tok = 0;
3450 +
3451 + /*
3452 + * Determine whether VDQCR is available based on whether the
3453 + * current result is sitting in the first storage location of
3454 + * the busy command.
3455 + */
3456 + if (s->vdq.storage == dq) {
3457 + s->vdq.storage = NULL;
3458 + atomic_inc(&s->vdq.available);
3459 + }
3460 +
3461 + return 1;
3462 +}
3463 +
3464 +/**
3465 + * qbman_release_desc_clear() - Clear the contents of a descriptor to
3466 + * default/starting state.
3467 + */
3468 +void qbman_release_desc_clear(struct qbman_release_desc *d)
3469 +{
3470 + memset(d, 0, sizeof(*d));
3471 + d->verb = 1 << 5; /* Release Command Valid */
3472 +}
3473 +
3474 +/**
3475 + * qbman_release_desc_set_bpid() - Set the ID of the buffer pool to release to
3476 + */
3477 +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid)
3478 +{
3479 + d->bpid = cpu_to_le16(bpid);
3480 +}
3481 +
3482 +/**
3483 + * qbman_release_desc_set_rcdi() - Determines whether or not the portal's RCDI
3484 + * interrupt source should be asserted after the release command is completed.
3485 + */
3486 +void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable)
3487 +{
3488 + if (enable)
3489 + d->verb |= 1 << 6;
3490 + else
3491 + d->verb &= ~(1 << 6);
3492 +}
3493 +
3494 +#define RAR_IDX(rar) ((rar) & 0x7)
3495 +#define RAR_VB(rar) ((rar) & 0x80)
3496 +#define RAR_SUCCESS(rar) ((rar) & 0x100)
3497 +
3498 +/**
3499 + * qbman_swp_release() - Issue a buffer release command
3500 + * @s: the software portal object
3501 + * @d: the release descriptor
3502 + * @buffers: a pointer pointing to the buffer address to be released
3503 + * @num_buffers: number of buffers to be released, must be less than 8
3504 + *
3505 + * Return 0 for success, -EBUSY if the release command ring is not ready.
3506 + */
3507 +int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
3508 + const u64 *buffers, unsigned int num_buffers)
3509 +{
3510 + int i;
3511 + struct qbman_release_desc *p;
3512 + u32 rar;
3513 +
3514 + if (!num_buffers || (num_buffers > 7))
3515 + return -EINVAL;
3516 +
3517 + rar = qbman_read_register(s, QBMAN_CINH_SWP_RAR);
3518 + if (!RAR_SUCCESS(rar))
3519 + return -EBUSY;
3520 +
3521 + /* Start the release command */
3522 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
3523 + /* Copy the caller's buffer pointers to the command */
3524 + for (i = 0; i < num_buffers; i++)
3525 + p->buf[i] = cpu_to_le64(buffers[i]);
3526 + p->bpid = d->bpid;
3527 +
3528 + /*
3529 + * Set the verb byte, have to substitute in the valid-bit and the number
3530 + * of buffers.
3531 + */
3532 + dma_wmb();
3533 + p->verb = d->verb | RAR_VB(rar) | num_buffers;
3534 + dccvac(p);
3535 +
3536 + return 0;
3537 +}
3538 +
3539 +struct qbman_acquire_desc {
3540 + u8 verb;
3541 + u8 reserved;
3542 + u16 bpid;
3543 + u8 num;
3544 + u8 reserved2[59];
3545 +};
3546 +
3547 +struct qbman_acquire_rslt {
3548 + u8 verb;
3549 + u8 rslt;
3550 + u16 reserved;
3551 + u8 num;
3552 + u8 reserved2[3];
3553 + u64 buf[7];
3554 +};
3555 +
3556 +/**
3557 + * qbman_swp_acquire() - Issue a buffer acquire command
3558 + * @s: the software portal object
3559 + * @bpid: the buffer pool index
3560 + * @buffers: a pointer pointing to the acquired buffer addresses
3561 + * @num_buffers: number of buffers to be acquired, must be less than 8
3562 + *
3563 + * Return 0 for success, or negative error code if the acquire command
3564 + * fails.
3565 + */
3566 +int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
3567 + unsigned int num_buffers)
3568 +{
3569 + struct qbman_acquire_desc *p;
3570 + struct qbman_acquire_rslt *r;
3571 + int i;
3572 +
3573 + if (!num_buffers || (num_buffers > 7))
3574 + return -EINVAL;
3575 +
3576 + /* Start the management command */
3577 + p = qbman_swp_mc_start(s);
3578 +
3579 + if (!p)
3580 + return -EBUSY;
3581 +
3582 + /* Encode the caller-provided attributes */
3583 + p->bpid = cpu_to_le16(bpid);
3584 + p->num = num_buffers;
3585 +
3586 + /* Complete the management command */
3587 + r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE);
3588 + if (unlikely(!r)) {
3589 + pr_err("qbman: acquire from BPID %d failed, no response\n",
3590 + bpid);
3591 + return -EIO;
3592 + }
3593 +
3594 + /* Decode the outcome */
3595 + WARN_ON((r->verb & 0x7f) != QBMAN_MC_ACQUIRE);
3596 +
3597 + /* Determine success or failure */
3598 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3599 + pr_err("qbman: acquire from BPID 0x%x failed, code=0x%02x\n",
3600 + bpid, r->rslt);
3601 + return -EIO;
3602 + }
3603 +
3604 + WARN_ON(r->num > num_buffers);
3605 +
3606 + /* Copy the acquired buffers to the caller's array */
3607 + for (i = 0; i < r->num; i++)
3608 + buffers[i] = le64_to_cpu(r->buf[i]);
3609 +
3610 + return (int)r->num;
3611 +}
3612 +
3613 +struct qbman_alt_fq_state_desc {
3614 + u8 verb;
3615 + u8 reserved[3];
3616 + u32 fqid;
3617 + u8 reserved2[56];
3618 +};
3619 +
3620 +struct qbman_alt_fq_state_rslt {
3621 + u8 verb;
3622 + u8 rslt;
3623 + u8 reserved[62];
3624 +};
3625 +
3626 +#define ALT_FQ_FQID_MASK 0x00FFFFFF
3627 +
3628 +int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
3629 + u8 alt_fq_verb)
3630 +{
3631 + struct qbman_alt_fq_state_desc *p;
3632 + struct qbman_alt_fq_state_rslt *r;
3633 +
3634 + /* Start the management command */
3635 + p = qbman_swp_mc_start(s);
3636 + if (!p)
3637 + return -EBUSY;
3638 +
3639 + p->fqid = cpu_to_le32(fqid) & ALT_FQ_FQID_MASK;
3640 +
3641 + /* Complete the management command */
3642 + r = qbman_swp_mc_complete(s, p, alt_fq_verb);
3643 + if (unlikely(!r)) {
3644 + pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n",
3645 + alt_fq_verb);
3646 + return -EIO;
3647 + }
3648 +
3649 + /* Decode the outcome */
3650 + WARN_ON((r->verb & QBMAN_RESULT_MASK) != alt_fq_verb);
3651 +
3652 + /* Determine success or failure */
3653 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3654 + pr_err("qbman: ALT FQID %d failed: verb = 0x%08x code = 0x%02x\n",
3655 + fqid, r->verb, r->rslt);
3656 + return -EIO;
3657 + }
3658 +
3659 + return 0;
3660 +}
3661 +
3662 +struct qbman_cdan_ctrl_desc {
3663 + u8 verb;
3664 + u8 reserved;
3665 + u16 ch;
3666 + u8 we;
3667 + u8 ctrl;
3668 + u16 reserved2;
3669 + u64 cdan_ctx;
3670 + u8 reserved3[48];
3671 +
3672 +};
3673 +
3674 +struct qbman_cdan_ctrl_rslt {
3675 + u8 verb;
3676 + u8 rslt;
3677 + u16 ch;
3678 + u8 reserved[60];
3679 +};
3680 +
3681 +int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
3682 + u8 we_mask, u8 cdan_en,
3683 + u64 ctx)
3684 +{
3685 + struct qbman_cdan_ctrl_desc *p = NULL;
3686 + struct qbman_cdan_ctrl_rslt *r = NULL;
3687 +
3688 + /* Start the management command */
3689 + p = qbman_swp_mc_start(s);
3690 + if (!p)
3691 + return -EBUSY;
3692 +
3693 + /* Encode the caller-provided attributes */
3694 + p->ch = cpu_to_le16(channelid);
3695 + p->we = we_mask;
3696 + if (cdan_en)
3697 + p->ctrl = 1;
3698 + else
3699 + p->ctrl = 0;
3700 + p->cdan_ctx = cpu_to_le64(ctx);
3701 +
3702 + /* Complete the management command */
3703 + r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE);
3704 + if (unlikely(!r)) {
3705 + pr_err("qbman: wqchan config failed, no response\n");
3706 + return -EIO;
3707 + }
3708 +
3709 + WARN_ON((r->verb & 0x7f) != QBMAN_WQCHAN_CONFIGURE);
3710 +
3711 + /* Determine success or failure */
3712 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3713 + pr_err("qbman: CDAN cQID %d failed: code = 0x%02x\n",
3714 + channelid, r->rslt);
3715 + return -EIO;
3716 + }
3717 +
3718 + return 0;
3719 +}
3720 --- /dev/null
3721 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
3722 @@ -0,0 +1,662 @@
3723 +/*
3724 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3725 + * Copyright 2016 NXP
3726 + *
3727 + * Redistribution and use in source and binary forms, with or without
3728 + * modification, are permitted provided that the following conditions are met:
3729 + * * Redistributions of source code must retain the above copyright
3730 + * notice, this list of conditions and the following disclaimer.
3731 + * * Redistributions in binary form must reproduce the above copyright
3732 + * notice, this list of conditions and the following disclaimer in the
3733 + * documentation and/or other materials provided with the distribution.
3734 + * * Neither the name of Freescale Semiconductor nor the
3735 + * names of its contributors may be used to endorse or promote products
3736 + * derived from this software without specific prior written permission.
3737 + *
3738 + * ALTERNATIVELY, this software may be distributed under the terms of the
3739 + * GNU General Public License ("GPL") as published by the Free Software
3740 + * Foundation, either version 2 of that License or (at your option) any
3741 + * later version.
3742 + *
3743 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
3744 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
3745 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
3746 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
3747 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
3748 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
3749 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
3750 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3751 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
3752 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3753 + */
3754 +#ifndef __FSL_QBMAN_PORTAL_H
3755 +#define __FSL_QBMAN_PORTAL_H
3756 +
3757 +#include "qbman_private.h"
3758 +#include "../../include/dpaa2-fd.h"
3759 +
3760 +struct dpaa2_dq;
3761 +struct qbman_swp;
3762 +
3763 +/* qbman software portal descriptor structure */
3764 +struct qbman_swp_desc {
3765 + void *cena_bar; /* Cache-enabled portal base address */
3766 + void *cinh_bar; /* Cache-inhibited portal base address */
3767 + u32 qman_version;
3768 +};
3769 +
3770 +#define QBMAN_SWP_INTERRUPT_EQRI 0x01
3771 +#define QBMAN_SWP_INTERRUPT_EQDI 0x02
3772 +#define QBMAN_SWP_INTERRUPT_DQRI 0x04
3773 +#define QBMAN_SWP_INTERRUPT_RCRI 0x08
3774 +#define QBMAN_SWP_INTERRUPT_RCDI 0x10
3775 +#define QBMAN_SWP_INTERRUPT_VDCI 0x20
3776 +
3777 +/* the structure for pull dequeue descriptor */
3778 +struct qbman_pull_desc {
3779 + u8 verb;
3780 + u8 numf;
3781 + u8 tok;
3782 + u8 reserved;
3783 + u32 dq_src;
3784 + u64 rsp_addr;
3785 + u64 rsp_addr_virt;
3786 + u8 padding[40];
3787 +};
3788 +
3789 +enum qbman_pull_type_e {
3790 + /* dequeue with priority precedence, respect intra-class scheduling */
3791 + qbman_pull_type_prio = 1,
3792 + /* dequeue with active FQ precedence, respect ICS */
3793 + qbman_pull_type_active,
3794 + /* dequeue with active FQ precedence, no ICS */
3795 + qbman_pull_type_active_noics
3796 +};
3797 +
3798 +/* Definitions for parsing dequeue entries */
3799 +#define QBMAN_RESULT_MASK 0x7f
3800 +#define QBMAN_RESULT_DQ 0x60
3801 +#define QBMAN_RESULT_FQRN 0x21
3802 +#define QBMAN_RESULT_FQRNI 0x22
3803 +#define QBMAN_RESULT_FQPN 0x24
3804 +#define QBMAN_RESULT_FQDAN 0x25
3805 +#define QBMAN_RESULT_CDAN 0x26
3806 +#define QBMAN_RESULT_CSCN_MEM 0x27
3807 +#define QBMAN_RESULT_CGCU 0x28
3808 +#define QBMAN_RESULT_BPSCN 0x29
3809 +#define QBMAN_RESULT_CSCN_WQ 0x2a
3810 +
3811 +/* QBMan FQ management command codes */
3812 +#define QBMAN_FQ_SCHEDULE 0x48
3813 +#define QBMAN_FQ_FORCE 0x49
3814 +#define QBMAN_FQ_XON 0x4d
3815 +#define QBMAN_FQ_XOFF 0x4e
3816 +
3817 +/* structure of enqueue descriptor */
3818 +struct qbman_eq_desc {
3819 + u8 verb;
3820 + u8 dca;
3821 + u16 seqnum;
3822 + u16 orpid;
3823 + u16 reserved1;
3824 + u32 tgtid;
3825 + u32 tag;
3826 + u16 qdbin;
3827 + u8 qpri;
3828 + u8 reserved[3];
3829 + u8 wae;
3830 + u8 rspid;
3831 + u64 rsp_addr;
3832 + u8 fd[32];
3833 +};
3834 +
3835 +/* buffer release descriptor */
3836 +struct qbman_release_desc {
3837 + u8 verb;
3838 + u8 reserved;
3839 + u16 bpid;
3840 + u32 reserved2;
3841 + u64 buf[7];
3842 +};
3843 +
3844 +/* Management command result codes */
3845 +#define QBMAN_MC_RSLT_OK 0xf0
3846 +
3847 +#define CODE_CDAN_WE_EN 0x1
3848 +#define CODE_CDAN_WE_CTX 0x4
3849 +
3850 +/* portal data structure */
3851 +struct qbman_swp {
3852 + const struct qbman_swp_desc *desc;
3853 + void __iomem *addr_cena;
3854 + void __iomem *addr_cinh;
3855 +
3856 + /* Management commands */
3857 + struct {
3858 + u32 valid_bit; /* 0x00 or 0x80 */
3859 + } mc;
3860 +
3861 + /* Push dequeues */
3862 + u32 sdq;
3863 +
3864 + /* Volatile dequeues */
3865 + struct {
3866 + atomic_t available; /* indicates if a command can be sent */
3867 + u32 valid_bit; /* 0x00 or 0x80 */
3868 + struct dpaa2_dq *storage; /* NULL if DQRR */
3869 + } vdq;
3870 +
3871 + /* DQRR */
3872 + struct {
3873 + u32 next_idx;
3874 + u32 valid_bit;
3875 + u8 dqrr_size;
3876 + int reset_bug; /* indicates dqrr reset workaround is needed */
3877 + } dqrr;
3878 +};
3879 +
3880 +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d);
3881 +void qbman_swp_finish(struct qbman_swp *p);
3882 +u32 qbman_swp_interrupt_read_status(struct qbman_swp *p);
3883 +void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask);
3884 +u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p);
3885 +void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask);
3886 +int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p);
3887 +void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit);
3888 +
3889 +void qbman_swp_push_get(struct qbman_swp *p, u8 channel_idx, int *enabled);
3890 +void qbman_swp_push_set(struct qbman_swp *p, u8 channel_idx, int enable);
3891 +
3892 +void qbman_pull_desc_clear(struct qbman_pull_desc *d);
3893 +void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
3894 + struct dpaa2_dq *storage,
3895 + dma_addr_t storage_phys,
3896 + int stash);
3897 +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes);
3898 +void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid);
3899 +void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
3900 + enum qbman_pull_type_e dct);
3901 +void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
3902 + enum qbman_pull_type_e dct);
3903 +
3904 +int qbman_swp_pull(struct qbman_swp *p, struct qbman_pull_desc *d);
3905 +
3906 +const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s);
3907 +void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq);
3908 +
3909 +int qbman_result_has_new_result(struct qbman_swp *p, const struct dpaa2_dq *dq);
3910 +
3911 +void qbman_eq_desc_clear(struct qbman_eq_desc *d);
3912 +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success);
3913 +void qbman_eq_desc_set_token(struct qbman_eq_desc *d, u8 token);
3914 +void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid);
3915 +void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
3916 + u32 qd_bin, u32 qd_prio);
3917 +
3918 +int qbman_swp_enqueue(struct qbman_swp *p, const struct qbman_eq_desc *d,
3919 + const struct dpaa2_fd *fd);
3920 +
3921 +void qbman_release_desc_clear(struct qbman_release_desc *d);
3922 +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid);
3923 +void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable);
3924 +
3925 +int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
3926 + const u64 *buffers, unsigned int num_buffers);
3927 +int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
3928 + unsigned int num_buffers);
3929 +int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
3930 + u8 alt_fq_verb);
3931 +int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
3932 + u8 we_mask, u8 cdan_en,
3933 + u64 ctx);
3934 +
3935 +void *qbman_swp_mc_start(struct qbman_swp *p);
3936 +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb);
3937 +void *qbman_swp_mc_result(struct qbman_swp *p);
3938 +
3939 +/**
3940 + * qbman_result_is_DQ() - check if the dequeue result is a dequeue response
3941 + * @dq: the dequeue result to be checked
3942 + *
3943 + * DQRR entries may contain non-dequeue results, ie. notifications
3944 + */
3945 +static inline int qbman_result_is_DQ(const struct dpaa2_dq *dq)
3946 +{
3947 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_DQ);
3948 +}
3949 +
3950 +/**
3951 + * qbman_result_is_SCN() - Check the dequeue result is notification or not
3952 + * @dq: the dequeue result to be checked
3953 + *
3954 + */
3955 +static inline int qbman_result_is_SCN(const struct dpaa2_dq *dq)
3956 +{
3957 + return !qbman_result_is_DQ(dq);
3958 +}
3959 +
3960 +/* FQ Data Availability */
3961 +static inline int qbman_result_is_FQDAN(const struct dpaa2_dq *dq)
3962 +{
3963 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQDAN);
3964 +}
3965 +
3966 +/* Channel Data Availability */
3967 +static inline int qbman_result_is_CDAN(const struct dpaa2_dq *dq)
3968 +{
3969 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CDAN);
3970 +}
3971 +
3972 +/* Congestion State Change */
3973 +static inline int qbman_result_is_CSCN(const struct dpaa2_dq *dq)
3974 +{
3975 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CSCN_WQ);
3976 +}
3977 +
3978 +/* Buffer Pool State Change */
3979 +static inline int qbman_result_is_BPSCN(const struct dpaa2_dq *dq)
3980 +{
3981 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_BPSCN);
3982 +}
3983 +
3984 +/* Congestion Group Count Update */
3985 +static inline int qbman_result_is_CGCU(const struct dpaa2_dq *dq)
3986 +{
3987 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CGCU);
3988 +}
3989 +
3990 +/* Retirement */
3991 +static inline int qbman_result_is_FQRN(const struct dpaa2_dq *dq)
3992 +{
3993 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRN);
3994 +}
3995 +
3996 +/* Retirement Immediate */
3997 +static inline int qbman_result_is_FQRNI(const struct dpaa2_dq *dq)
3998 +{
3999 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRNI);
4000 +}
4001 +
4002 + /* Park */
4003 +static inline int qbman_result_is_FQPN(const struct dpaa2_dq *dq)
4004 +{
4005 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQPN);
4006 +}
4007 +
4008 +/**
4009 + * qbman_result_SCN_state() - Get the state field in State-change notification
4010 + */
4011 +static inline u8 qbman_result_SCN_state(const struct dpaa2_dq *scn)
4012 +{
4013 + return scn->scn.state;
4014 +}
4015 +
4016 +#define SCN_RID_MASK 0x00FFFFFF
4017 +
4018 +/**
4019 + * qbman_result_SCN_rid() - Get the resource id in State-change notification
4020 + */
4021 +static inline u32 qbman_result_SCN_rid(const struct dpaa2_dq *scn)
4022 +{
4023 + return le32_to_cpu(scn->scn.rid_tok) & SCN_RID_MASK;
4024 +}
4025 +
4026 +/**
4027 + * qbman_result_SCN_ctx() - Get the context data in State-change notification
4028 + */
4029 +static inline u64 qbman_result_SCN_ctx(const struct dpaa2_dq *scn)
4030 +{
4031 + return le64_to_cpu(scn->scn.ctx);
4032 +}
4033 +
4034 +/**
4035 + * qbman_swp_fq_schedule() - Move the fq to the scheduled state
4036 + * @s: the software portal object
4037 + * @fqid: the index of frame queue to be scheduled
4038 + *
4039 + * There are a couple of different ways that a FQ can end up parked state,
4040 + * This schedules it.
4041 + *
4042 + * Return 0 for success, or negative error code for failure.
4043 + */
4044 +static inline int qbman_swp_fq_schedule(struct qbman_swp *s, u32 fqid)
4045 +{
4046 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE);
4047 +}
4048 +
4049 +/**
4050 + * qbman_swp_fq_force() - Force the FQ to fully scheduled state
4051 + * @s: the software portal object
4052 + * @fqid: the index of frame queue to be forced
4053 + *
4054 + * Force eligible will force a tentatively-scheduled FQ to be fully-scheduled
4055 + * and thus be available for selection by any channel-dequeuing behaviour (push
4056 + * or pull). If the FQ is subsequently "dequeued" from the channel and is still
4057 + * empty at the time this happens, the resulting dq_entry will have no FD.
4058 + * (qbman_result_DQ_fd() will return NULL.)
4059 + *
4060 + * Return 0 for success, or negative error code for failure.
4061 + */
4062 +static inline int qbman_swp_fq_force(struct qbman_swp *s, u32 fqid)
4063 +{
4064 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE);
4065 +}
4066 +
4067 +/**
4068 + * qbman_swp_fq_xon() - sets FQ flow-control to XON
4069 + * @s: the software portal object
4070 + * @fqid: the index of frame queue
4071 + *
4072 + * This setting doesn't affect enqueues to the FQ, just dequeues.
4073 + *
4074 + * Return 0 for success, or negative error code for failure.
4075 + */
4076 +static inline int qbman_swp_fq_xon(struct qbman_swp *s, u32 fqid)
4077 +{
4078 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON);
4079 +}
4080 +
4081 +/**
4082 + * qbman_swp_fq_xoff() - sets FQ flow-control to XOFF
4083 + * @s: the software portal object
4084 + * @fqid: the index of frame queue
4085 + *
4086 + * This setting doesn't affect enqueues to the FQ, just dequeues.
4087 + * XOFF FQs will remain in the tenatively-scheduled state, even when
4088 + * non-empty, meaning they won't be selected for scheduled dequeuing.
4089 + * If a FQ is changed to XOFF after it had already become truly-scheduled
4090 + * to a channel, and a pull dequeue of that channel occurs that selects
4091 + * that FQ for dequeuing, then the resulting dq_entry will have no FD.
4092 + * (qbman_result_DQ_fd() will return NULL.)
4093 + *
4094 + * Return 0 for success, or negative error code for failure.
4095 + */
4096 +static inline int qbman_swp_fq_xoff(struct qbman_swp *s, u32 fqid)
4097 +{
4098 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF);
4099 +}
4100 +
4101 +/* If the user has been allocated a channel object that is going to generate
4102 + * CDANs to another channel, then the qbman_swp_CDAN* functions will be
4103 + * necessary.
4104 + *
4105 + * CDAN-enabled channels only generate a single CDAN notification, after which
4106 + * they need to be reenabled before they'll generate another. The idea is
4107 + * that pull dequeuing will occur in reaction to the CDAN, followed by a
4108 + * reenable step. Each function generates a distinct command to hardware, so a
4109 + * combination function is provided if the user wishes to modify the "context"
4110 + * (which shows up in each CDAN message) each time they reenable, as a single
4111 + * command to hardware.
4112 + */
4113 +
4114 +/**
4115 + * qbman_swp_CDAN_set_context() - Set CDAN context
4116 + * @s: the software portal object
4117 + * @channelid: the channel index
4118 + * @ctx: the context to be set in CDAN
4119 + *
4120 + * Return 0 for success, or negative error code for failure.
4121 + */
4122 +static inline int qbman_swp_CDAN_set_context(struct qbman_swp *s, u16 channelid,
4123 + u64 ctx)
4124 +{
4125 + return qbman_swp_CDAN_set(s, channelid,
4126 + CODE_CDAN_WE_CTX,
4127 + 0, ctx);
4128 +}
4129 +
4130 +/**
4131 + * qbman_swp_CDAN_enable() - Enable CDAN for the channel
4132 + * @s: the software portal object
4133 + * @channelid: the index of the channel to generate CDAN
4134 + *
4135 + * Return 0 for success, or negative error code for failure.
4136 + */
4137 +static inline int qbman_swp_CDAN_enable(struct qbman_swp *s, u16 channelid)
4138 +{
4139 + return qbman_swp_CDAN_set(s, channelid,
4140 + CODE_CDAN_WE_EN,
4141 + 1, 0);
4142 +}
4143 +
4144 +/**
4145 + * qbman_swp_CDAN_disable() - disable CDAN for the channel
4146 + * @s: the software portal object
4147 + * @channelid: the index of the channel to generate CDAN
4148 + *
4149 + * Return 0 for success, or negative error code for failure.
4150 + */
4151 +static inline int qbman_swp_CDAN_disable(struct qbman_swp *s, u16 channelid)
4152 +{
4153 + return qbman_swp_CDAN_set(s, channelid,
4154 + CODE_CDAN_WE_EN,
4155 + 0, 0);
4156 +}
4157 +
4158 +/**
4159 + * qbman_swp_CDAN_set_context_enable() - Set CDAN contest and enable CDAN
4160 + * @s: the software portal object
4161 + * @channelid: the index of the channel to generate CDAN
4162 + * @ctx:i the context set in CDAN
4163 + *
4164 + * Return 0 for success, or negative error code for failure.
4165 + */
4166 +static inline int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s,
4167 + u16 channelid,
4168 + u64 ctx)
4169 +{
4170 + return qbman_swp_CDAN_set(s, channelid,
4171 + CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX,
4172 + 1, ctx);
4173 +}
4174 +
4175 +/* Wraps up submit + poll-for-result */
4176 +static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
4177 + u8 cmd_verb)
4178 +{
4179 + int loopvar = 1000;
4180 +
4181 + qbman_swp_mc_submit(swp, cmd, cmd_verb);
4182 +
4183 + do {
4184 + cmd = qbman_swp_mc_result(swp);
4185 + } while (!cmd && loopvar--);
4186 +
4187 + WARN_ON(!loopvar);
4188 +
4189 + return cmd;
4190 +}
4191 +
4192 +/* ------------ */
4193 +/* qb_attr_code */
4194 +/* ------------ */
4195 +
4196 +/* This struct locates a sub-field within a QBMan portal (CENA) cacheline which
4197 + * is either serving as a configuration command or a query result. The
4198 + * representation is inherently little-endian, as the indexing of the words is
4199 + * itself little-endian in nature and layerscape is little endian for anything
4200 + * that crosses a word boundary too (64-bit fields are the obvious examples).
4201 + */
4202 +struct qb_attr_code {
4203 + unsigned int word; /* which u32[] array member encodes the field */
4204 + unsigned int lsoffset; /* encoding offset from ls-bit */
4205 + unsigned int width; /* encoding width. (bool must be 1.) */
4206 +};
4207 +
4208 +/* Some pre-defined codes */
4209 +extern struct qb_attr_code code_generic_verb;
4210 +extern struct qb_attr_code code_generic_rslt;
4211 +
4212 +/* Macros to define codes */
4213 +#define QB_CODE(a, b, c) { a, b, c}
4214 +#define QB_CODE_NULL \
4215 + QB_CODE((unsigned int)-1, (unsigned int)-1, (unsigned int)-1)
4216 +
4217 +/* Rotate a code "ms", meaning that it moves from less-significant bytes to
4218 + * more-significant, from less-significant words to more-significant, etc. The
4219 + * "ls" version does the inverse, from more-significant towards
4220 + * less-significant.
4221 + */
4222 +static inline void qb_attr_code_rotate_ms(struct qb_attr_code *code,
4223 + unsigned int bits)
4224 +{
4225 + code->lsoffset += bits;
4226 + while (code->lsoffset > 31) {
4227 + code->word++;
4228 + code->lsoffset -= 32;
4229 + }
4230 +}
4231 +
4232 +static inline void qb_attr_code_rotate_ls(struct qb_attr_code *code,
4233 + unsigned int bits)
4234 +{
4235 + /* Don't be fooled, this trick should work because the types are
4236 + * unsigned. So the case that interests the while loop (the rotate has
4237 + * gone too far and the word count needs to compensate for it), is
4238 + * manifested when lsoffset is negative. But that equates to a really
4239 + * large unsigned value, starting with lots of "F"s. As such, we can
4240 + * continue adding 32 back to it until it wraps back round above zero,
4241 + * to a value of 31 or less...
4242 + */
4243 + code->lsoffset -= bits;
4244 + while (code->lsoffset > 31) {
4245 + code->word--;
4246 + code->lsoffset += 32;
4247 + }
4248 +}
4249 +
4250 +/* Implement a loop of code rotations until 'expr' evaluates to FALSE (0). */
4251 +#define qb_attr_code_for_ms(code, bits, expr) \
4252 + for (; expr; qb_attr_code_rotate_ms(code, bits))
4253 +#define qb_attr_code_for_ls(code, bits, expr) \
4254 + for (; expr; qb_attr_code_rotate_ls(code, bits))
4255 +
4256 +static inline void word_copy(void *d, const void *s, unsigned int cnt)
4257 +{
4258 + u32 *dd = d;
4259 + const u32 *ss = s;
4260 +
4261 + while (cnt--)
4262 + *(dd++) = *(ss++);
4263 +}
4264 +
4265 +/*
4266 + * Currently, the CENA support code expects each 32-bit word to be written in
4267 + * host order, and these are converted to hardware (little-endian) order on
4268 + * command submission. However, 64-bit quantities are must be written (and read)
4269 + * as two 32-bit words with the least-significant word first, irrespective of
4270 + * host endianness.
4271 + */
4272 +static inline void u64_to_le32_copy(void *d, const u64 *s,
4273 + unsigned int cnt)
4274 +{
4275 + u32 *dd = d;
4276 + const u32 *ss = (const u32 *)s;
4277 +
4278 + while (cnt--) {
4279 + /*
4280 + * TBD: the toolchain was choking on the use of 64-bit types up
4281 + * until recently so this works entirely with 32-bit variables.
4282 + * When 64-bit types become usable again, investigate better
4283 + * ways of doing this.
4284 + */
4285 +#if defined(__BIG_ENDIAN)
4286 + *(dd++) = ss[1];
4287 + *(dd++) = ss[0];
4288 + ss += 2;
4289 +#else
4290 + *(dd++) = *(ss++);
4291 + *(dd++) = *(ss++);
4292 +#endif
4293 + }
4294 +}
4295 +
4296 +static inline void u64_from_le32_copy(u64 *d, const void *s,
4297 + unsigned int cnt)
4298 +{
4299 + const u32 *ss = s;
4300 + u32 *dd = (u32 *)d;
4301 +
4302 + while (cnt--) {
4303 +#if defined(__BIG_ENDIAN)
4304 + dd[1] = *(ss++);
4305 + dd[0] = *(ss++);
4306 + dd += 2;
4307 +#else
4308 + *(dd++) = *(ss++);
4309 + *(dd++) = *(ss++);
4310 +#endif
4311 + }
4312 +}
4313 +
4314 +/* decode a field from a cacheline */
4315 +static inline u32 qb_attr_code_decode(const struct qb_attr_code *code,
4316 + const u32 *cacheline)
4317 +{
4318 + return d32_u32(code->lsoffset, code->width, cacheline[code->word]);
4319 +}
4320 +
4321 +static inline u64 qb_attr_code_decode_64(const struct qb_attr_code *code,
4322 + const u64 *cacheline)
4323 +{
4324 + u64 res;
4325 +
4326 + u64_from_le32_copy(&res, &cacheline[code->word / 2], 1);
4327 + return res;
4328 +}
4329 +
4330 +/* encode a field to a cacheline */
4331 +static inline void qb_attr_code_encode(const struct qb_attr_code *code,
4332 + u32 *cacheline, u32 val)
4333 +{
4334 + cacheline[code->word] =
4335 + r32_u32(code->lsoffset, code->width, cacheline[code->word])
4336 + | e32_u32(code->lsoffset, code->width, val);
4337 +}
4338 +
4339 +static inline void qb_attr_code_encode_64(const struct qb_attr_code *code,
4340 + u64 *cacheline, u64 val)
4341 +{
4342 + u64_to_le32_copy(&cacheline[code->word / 2], &val, 1);
4343 +}
4344 +
4345 +/* Small-width signed values (two's-complement) will decode into medium-width
4346 + * positives. (Eg. for an 8-bit signed field, which stores values from -128 to
4347 + * +127, a setting of -7 would appear to decode to the 32-bit unsigned value
4348 + * 249. Likewise -120 would decode as 136.) This function allows the caller to
4349 + * "re-sign" such fields to 32-bit signed. (Eg. -7, which was 249 with an 8-bit
4350 + * encoding, will become 0xfffffff9 if you cast the return value to u32).
4351 + */
4352 +static inline int32_t qb_attr_code_makesigned(const struct qb_attr_code *code,
4353 + u32 val)
4354 +{
4355 + WARN_ON(val >= (1 << code->width));
4356 + /* If the high bit was set, it was encoding a negative */
4357 + if (val >= (1 << (code->width - 1)))
4358 + return (int32_t)0 - (int32_t)(((u32)1 << code->width) -
4359 + val);
4360 + /* Otherwise, it was encoding a positive */
4361 + return (int32_t)val;
4362 +}
4363 +
4364 +/* ---------------------- */
4365 +/* Descriptors/cachelines */
4366 +/* ---------------------- */
4367 +
4368 +/* To avoid needless dynamic allocation, the driver API often gives the caller
4369 + * a "descriptor" type that the caller can instantiate however they like.
4370 + * Ultimately though, it is just a cacheline of binary storage (or something
4371 + * smaller when it is known that the descriptor doesn't need all 64 bytes) for
4372 + * holding pre-formatted pieces of hardware commands. The performance-critical
4373 + * code can then copy these descriptors directly into hardware command
4374 + * registers more efficiently than trying to construct/format commands
4375 + * on-the-fly. The API user sees the descriptor as an array of 32-bit words in
4376 + * order for the compiler to know its size, but the internal details are not
4377 + * exposed. The following macro is used within the driver for converting *any*
4378 + * descriptor pointer to a usable array pointer. The use of a macro (instead of
4379 + * an inline) is necessary to work with different descriptor types and to work
4380 + * correctly with const and non-const inputs (and similarly-qualified outputs).
4381 + */
4382 +#define qb_cl(d) (&(d)->dont_manipulate_directly[0])
4383 +
4384 +#endif /* __FSL_QBMAN_PORTAL_H */
4385 --- /dev/null
4386 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.c
4387 @@ -0,0 +1,853 @@
4388 +/* Copyright (C) 2015 Freescale Semiconductor, Inc.
4389 + *
4390 + * Redistribution and use in source and binary forms, with or without
4391 + * modification, are permitted provided that the following conditions are met:
4392 + * * Redistributions of source code must retain the above copyright
4393 + * notice, this list of conditions and the following disclaimer.
4394 + * * Redistributions in binary form must reproduce the above copyright
4395 + * notice, this list of conditions and the following disclaimer in the
4396 + * documentation and/or other materials provided with the distribution.
4397 + * * Neither the name of Freescale Semiconductor nor the
4398 + * names of its contributors may be used to endorse or promote products
4399 + * derived from this software without specific prior written permission.
4400 + *
4401 + *
4402 + * ALTERNATIVELY, this software may be distributed under the terms of the
4403 + * GNU General Public License ("GPL") as published by the Free Software
4404 + * Foundation, either version 2 of that License or (at your option) any
4405 + * later version.
4406 + *
4407 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
4408 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
4409 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
4410 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
4411 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
4412 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
4413 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
4414 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4415 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
4416 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4417 + */
4418 +
4419 +#include <linux/errno.h>
4420 +
4421 +#include "../../include/dpaa2-global.h"
4422 +#include "qbman-portal.h"
4423 +#include "qbman_debug.h"
4424 +
4425 +/* QBMan portal management command code */
4426 +#define QBMAN_BP_QUERY 0x32
4427 +#define QBMAN_FQ_QUERY 0x44
4428 +#define QBMAN_FQ_QUERY_NP 0x45
4429 +#define QBMAN_CGR_QUERY 0x51
4430 +#define QBMAN_WRED_QUERY 0x54
4431 +#define QBMAN_CGR_STAT_QUERY 0x55
4432 +#define QBMAN_CGR_STAT_QUERY_CLR 0x56
4433 +
4434 +enum qbman_attr_usage_e {
4435 + qbman_attr_usage_fq,
4436 + qbman_attr_usage_bpool,
4437 + qbman_attr_usage_cgr,
4438 +};
4439 +
4440 +struct int_qbman_attr {
4441 + u32 words[32];
4442 + enum qbman_attr_usage_e usage;
4443 +};
4444 +
4445 +#define attr_type_set(a, e) \
4446 +{ \
4447 + struct qbman_attr *__attr = a; \
4448 + enum qbman_attr_usage_e __usage = e; \
4449 + ((struct int_qbman_attr *)__attr)->usage = __usage; \
4450 +}
4451 +
4452 +#define ATTR32(d) (&(d)->dont_manipulate_directly[0])
4453 +#define ATTR32_1(d) (&(d)->dont_manipulate_directly[16])
4454 +
4455 +static struct qb_attr_code code_bp_bpid = QB_CODE(0, 16, 16);
4456 +static struct qb_attr_code code_bp_bdi = QB_CODE(1, 16, 1);
4457 +static struct qb_attr_code code_bp_va = QB_CODE(1, 17, 1);
4458 +static struct qb_attr_code code_bp_wae = QB_CODE(1, 18, 1);
4459 +static struct qb_attr_code code_bp_swdet = QB_CODE(4, 0, 16);
4460 +static struct qb_attr_code code_bp_swdxt = QB_CODE(4, 16, 16);
4461 +static struct qb_attr_code code_bp_hwdet = QB_CODE(5, 0, 16);
4462 +static struct qb_attr_code code_bp_hwdxt = QB_CODE(5, 16, 16);
4463 +static struct qb_attr_code code_bp_swset = QB_CODE(6, 0, 16);
4464 +static struct qb_attr_code code_bp_swsxt = QB_CODE(6, 16, 16);
4465 +static struct qb_attr_code code_bp_vbpid = QB_CODE(7, 0, 14);
4466 +static struct qb_attr_code code_bp_icid = QB_CODE(7, 16, 15);
4467 +static struct qb_attr_code code_bp_pl = QB_CODE(7, 31, 1);
4468 +static struct qb_attr_code code_bp_bpscn_addr_lo = QB_CODE(8, 0, 32);
4469 +static struct qb_attr_code code_bp_bpscn_addr_hi = QB_CODE(9, 0, 32);
4470 +static struct qb_attr_code code_bp_bpscn_ctx_lo = QB_CODE(10, 0, 32);
4471 +static struct qb_attr_code code_bp_bpscn_ctx_hi = QB_CODE(11, 0, 32);
4472 +static struct qb_attr_code code_bp_hw_targ = QB_CODE(12, 0, 16);
4473 +static struct qb_attr_code code_bp_state = QB_CODE(1, 24, 3);
4474 +static struct qb_attr_code code_bp_fill = QB_CODE(2, 0, 32);
4475 +static struct qb_attr_code code_bp_hdptr = QB_CODE(3, 0, 32);
4476 +static struct qb_attr_code code_bp_sdcnt = QB_CODE(13, 0, 8);
4477 +static struct qb_attr_code code_bp_hdcnt = QB_CODE(13, 1, 8);
4478 +static struct qb_attr_code code_bp_sscnt = QB_CODE(13, 2, 8);
4479 +
4480 +void qbman_bp_attr_clear(struct qbman_attr *a)
4481 +{
4482 + memset(a, 0, sizeof(*a));
4483 + attr_type_set(a, qbman_attr_usage_bpool);
4484 +}
4485 +
4486 +int qbman_bp_query(struct qbman_swp *s, u32 bpid,
4487 + struct qbman_attr *a)
4488 +{
4489 + u32 *p;
4490 + u32 verb, rslt;
4491 + u32 *attr = ATTR32(a);
4492 +
4493 + qbman_bp_attr_clear(a);
4494 +
4495 + /* Start the management command */
4496 + p = qbman_swp_mc_start(s);
4497 + if (!p)
4498 + return -EBUSY;
4499 +
4500 + /* Encode the caller-provided attributes */
4501 + qb_attr_code_encode(&code_bp_bpid, p, bpid);
4502 +
4503 + /* Complete the management command */
4504 + p = qbman_swp_mc_complete(s, p, QBMAN_BP_QUERY);
4505 +
4506 + /* Decode the outcome */
4507 + verb = qb_attr_code_decode(&code_generic_verb, p);
4508 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
4509 + WARN_ON(verb != QBMAN_BP_QUERY);
4510 +
4511 + /* Determine success or failure */
4512 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
4513 + pr_err("Query of BPID 0x%x failed, code=0x%02x\n", bpid, rslt);
4514 + return -EIO;
4515 + }
4516 +
4517 + /* For the query, word[0] of the result contains only the
4518 + * verb/rslt fields, so skip word[0].
4519 + */
4520 + word_copy(&attr[1], &p[1], 15);
4521 + return 0;
4522 +}
4523 +
4524 +void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae)
4525 +{
4526 + u32 *p = ATTR32(a);
4527 +
4528 + *bdi = !!qb_attr_code_decode(&code_bp_bdi, p);
4529 + *va = !!qb_attr_code_decode(&code_bp_va, p);
4530 + *wae = !!qb_attr_code_decode(&code_bp_wae, p);
4531 +}
4532 +
4533 +static u32 qbman_bp_thresh_to_value(u32 val)
4534 +{
4535 + return (val & 0xff) << ((val & 0xf00) >> 8);
4536 +}
4537 +
4538 +void qbman_bp_attr_get_swdet(struct qbman_attr *a, u32 *swdet)
4539 +{
4540 + u32 *p = ATTR32(a);
4541 +
4542 + *swdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdet,
4543 + p));
4544 +}
4545 +
4546 +void qbman_bp_attr_get_swdxt(struct qbman_attr *a, u32 *swdxt)
4547 +{
4548 + u32 *p = ATTR32(a);
4549 +
4550 + *swdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdxt,
4551 + p));
4552 +}
4553 +
4554 +void qbman_bp_attr_get_hwdet(struct qbman_attr *a, u32 *hwdet)
4555 +{
4556 + u32 *p = ATTR32(a);
4557 +
4558 + *hwdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdet,
4559 + p));
4560 +}
4561 +
4562 +void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, u32 *hwdxt)
4563 +{
4564 + u32 *p = ATTR32(a);
4565 +
4566 + *hwdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdxt,
4567 + p));
4568 +}
4569 +
4570 +void qbman_bp_attr_get_swset(struct qbman_attr *a, u32 *swset)
4571 +{
4572 + u32 *p = ATTR32(a);
4573 +
4574 + *swset = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swset,
4575 + p));
4576 +}
4577 +
4578 +void qbman_bp_attr_get_swsxt(struct qbman_attr *a, u32 *swsxt)
4579 +{
4580 + u32 *p = ATTR32(a);
4581 +
4582 + *swsxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swsxt,
4583 + p));
4584 +}
4585 +
4586 +void qbman_bp_attr_get_vbpid(struct qbman_attr *a, u32 *vbpid)
4587 +{
4588 + u32 *p = ATTR32(a);
4589 +
4590 + *vbpid = qb_attr_code_decode(&code_bp_vbpid, p);
4591 +}
4592 +
4593 +void qbman_bp_attr_get_icid(struct qbman_attr *a, u32 *icid, int *pl)
4594 +{
4595 + u32 *p = ATTR32(a);
4596 +
4597 + *icid = qb_attr_code_decode(&code_bp_icid, p);
4598 + *pl = !!qb_attr_code_decode(&code_bp_pl, p);
4599 +}
4600 +
4601 +void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, u64 *bpscn_addr)
4602 +{
4603 + u32 *p = ATTR32(a);
4604 +
4605 + *bpscn_addr = ((u64)qb_attr_code_decode(&code_bp_bpscn_addr_hi,
4606 + p) << 32) |
4607 + (u64)qb_attr_code_decode(&code_bp_bpscn_addr_lo,
4608 + p);
4609 +}
4610 +
4611 +void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, u64 *bpscn_ctx)
4612 +{
4613 + u32 *p = ATTR32(a);
4614 +
4615 + *bpscn_ctx = ((u64)qb_attr_code_decode(&code_bp_bpscn_ctx_hi, p)
4616 + << 32) |
4617 + (u64)qb_attr_code_decode(&code_bp_bpscn_ctx_lo,
4618 + p);
4619 +}
4620 +
4621 +void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, u32 *hw_targ)
4622 +{
4623 + u32 *p = ATTR32(a);
4624 +
4625 + *hw_targ = qb_attr_code_decode(&code_bp_hw_targ, p);
4626 +}
4627 +
4628 +int qbman_bp_info_has_free_bufs(struct qbman_attr *a)
4629 +{
4630 + u32 *p = ATTR32(a);
4631 +
4632 + return !(int)(qb_attr_code_decode(&code_bp_state, p) & 0x1);
4633 +}
4634 +
4635 +int qbman_bp_info_is_depleted(struct qbman_attr *a)
4636 +{
4637 + u32 *p = ATTR32(a);
4638 +
4639 + return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x2);
4640 +}
4641 +
4642 +int qbman_bp_info_is_surplus(struct qbman_attr *a)
4643 +{
4644 + u32 *p = ATTR32(a);
4645 +
4646 + return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x4);
4647 +}
4648 +
4649 +u32 qbman_bp_info_num_free_bufs(struct qbman_attr *a)
4650 +{
4651 + u32 *p = ATTR32(a);
4652 +
4653 + return qb_attr_code_decode(&code_bp_fill, p);
4654 +}
4655 +
4656 +u32 qbman_bp_info_hdptr(struct qbman_attr *a)
4657 +{
4658 + u32 *p = ATTR32(a);
4659 +
4660 + return qb_attr_code_decode(&code_bp_hdptr, p);
4661 +}
4662 +
4663 +u32 qbman_bp_info_sdcnt(struct qbman_attr *a)
4664 +{
4665 + u32 *p = ATTR32(a);
4666 +
4667 + return qb_attr_code_decode(&code_bp_sdcnt, p);
4668 +}
4669 +
4670 +u32 qbman_bp_info_hdcnt(struct qbman_attr *a)
4671 +{
4672 + u32 *p = ATTR32(a);
4673 +
4674 + return qb_attr_code_decode(&code_bp_hdcnt, p);
4675 +}
4676 +
4677 +u32 qbman_bp_info_sscnt(struct qbman_attr *a)
4678 +{
4679 + u32 *p = ATTR32(a);
4680 +
4681 + return qb_attr_code_decode(&code_bp_sscnt, p);
4682 +}
4683 +
4684 +static struct qb_attr_code code_fq_fqid = QB_CODE(1, 0, 24);
4685 +static struct qb_attr_code code_fq_cgrid = QB_CODE(2, 16, 16);
4686 +static struct qb_attr_code code_fq_destwq = QB_CODE(3, 0, 15);
4687 +static struct qb_attr_code code_fq_fqctrl = QB_CODE(3, 24, 8);
4688 +static struct qb_attr_code code_fq_icscred = QB_CODE(4, 0, 15);
4689 +static struct qb_attr_code code_fq_tdthresh = QB_CODE(4, 16, 13);
4690 +static struct qb_attr_code code_fq_oa_len = QB_CODE(5, 0, 12);
4691 +static struct qb_attr_code code_fq_oa_ics = QB_CODE(5, 14, 1);
4692 +static struct qb_attr_code code_fq_oa_cgr = QB_CODE(5, 15, 1);
4693 +static struct qb_attr_code code_fq_mctl_bdi = QB_CODE(5, 24, 1);
4694 +static struct qb_attr_code code_fq_mctl_ff = QB_CODE(5, 25, 1);
4695 +static struct qb_attr_code code_fq_mctl_va = QB_CODE(5, 26, 1);
4696 +static struct qb_attr_code code_fq_mctl_ps = QB_CODE(5, 27, 1);
4697 +static struct qb_attr_code code_fq_ctx_lower32 = QB_CODE(6, 0, 32);
4698 +static struct qb_attr_code code_fq_ctx_upper32 = QB_CODE(7, 0, 32);
4699 +static struct qb_attr_code code_fq_icid = QB_CODE(8, 0, 15);
4700 +static struct qb_attr_code code_fq_pl = QB_CODE(8, 15, 1);
4701 +static struct qb_attr_code code_fq_vfqid = QB_CODE(9, 0, 24);
4702 +static struct qb_attr_code code_fq_erfqid = QB_CODE(10, 0, 24);
4703 +
4704 +void qbman_fq_attr_clear(struct qbman_attr *a)
4705 +{
4706 + memset(a, 0, sizeof(*a));
4707 + attr_type_set(a, qbman_attr_usage_fq);
4708 +}
4709 +
4710 +/* FQ query function for programmable fields */
4711 +int qbman_fq_query(struct qbman_swp *s, u32 fqid, struct qbman_attr *desc)
4712 +{
4713 + u32 *p;
4714 + u32 verb, rslt;
4715 + u32 *d = ATTR32(desc);
4716 +
4717 + qbman_fq_attr_clear(desc);
4718 +
4719 + p = qbman_swp_mc_start(s);
4720 + if (!p)
4721 + return -EBUSY;
4722 + qb_attr_code_encode(&code_fq_fqid, p, fqid);
4723 + p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY);
4724 +
4725 + /* Decode the outcome */
4726 + verb = qb_attr_code_decode(&code_generic_verb, p);
4727 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
4728 + WARN_ON(verb != QBMAN_FQ_QUERY);
4729 +
4730 + /* Determine success or failure */
4731 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
4732 + pr_err("Query of FQID 0x%x failed, code=0x%02x\n",
4733 + fqid, rslt);
4734 + return -EIO;
4735 + }
4736 + /*
4737 + * For the configure, word[0] of the command contains only the WE-mask.
4738 + * For the query, word[0] of the result contains only the verb/rslt
4739 + * fields. Skip word[0] in the latter case.
4740 + */
4741 + word_copy(&d[1], &p[1], 15);
4742 + return 0;
4743 +}
4744 +
4745 +void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, u32 *fqctrl)
4746 +{
4747 + u32 *p = ATTR32(d);
4748 +
4749 + *fqctrl = qb_attr_code_decode(&code_fq_fqctrl, p);
4750 +}
4751 +
4752 +void qbman_fq_attr_get_cgrid(struct qbman_attr *d, u32 *cgrid)
4753 +{
4754 + u32 *p = ATTR32(d);
4755 +
4756 + *cgrid = qb_attr_code_decode(&code_fq_cgrid, p);
4757 +}
4758 +
4759 +void qbman_fq_attr_get_destwq(struct qbman_attr *d, u32 *destwq)
4760 +{
4761 + u32 *p = ATTR32(d);
4762 +
4763 + *destwq = qb_attr_code_decode(&code_fq_destwq, p);
4764 +}
4765 +
4766 +void qbman_fq_attr_get_icscred(struct qbman_attr *d, u32 *icscred)
4767 +{
4768 + u32 *p = ATTR32(d);
4769 +
4770 + *icscred = qb_attr_code_decode(&code_fq_icscred, p);
4771 +}
4772 +
4773 +static struct qb_attr_code code_tdthresh_exp = QB_CODE(0, 0, 5);
4774 +static struct qb_attr_code code_tdthresh_mant = QB_CODE(0, 5, 8);
4775 +static u32 qbman_thresh_to_value(u32 val)
4776 +{
4777 + u32 m, e;
4778 +
4779 + m = qb_attr_code_decode(&code_tdthresh_mant, &val);
4780 + e = qb_attr_code_decode(&code_tdthresh_exp, &val);
4781 + return m << e;
4782 +}
4783 +
4784 +void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, u32 *tdthresh)
4785 +{
4786 + u32 *p = ATTR32(d);
4787 +
4788 + *tdthresh = qbman_thresh_to_value(qb_attr_code_decode(&code_fq_tdthresh,
4789 + p));
4790 +}
4791 +
4792 +void qbman_fq_attr_get_oa(struct qbman_attr *d,
4793 + int *oa_ics, int *oa_cgr, int32_t *oa_len)
4794 +{
4795 + u32 *p = ATTR32(d);
4796 +
4797 + *oa_ics = !!qb_attr_code_decode(&code_fq_oa_ics, p);
4798 + *oa_cgr = !!qb_attr_code_decode(&code_fq_oa_cgr, p);
4799 + *oa_len = qb_attr_code_makesigned(&code_fq_oa_len,
4800 + qb_attr_code_decode(&code_fq_oa_len, p));
4801 +}
4802 +
4803 +void qbman_fq_attr_get_mctl(struct qbman_attr *d,
4804 + int *bdi, int *ff, int *va, int *ps)
4805 +{
4806 + u32 *p = ATTR32(d);
4807 +
4808 + *bdi = !!qb_attr_code_decode(&code_fq_mctl_bdi, p);
4809 + *ff = !!qb_attr_code_decode(&code_fq_mctl_ff, p);
4810 + *va = !!qb_attr_code_decode(&code_fq_mctl_va, p);
4811 + *ps = !!qb_attr_code_decode(&code_fq_mctl_ps, p);
4812 +}
4813 +
4814 +void qbman_fq_attr_get_ctx(struct qbman_attr *d, u32 *hi, u32 *lo)
4815 +{
4816 + u32 *p = ATTR32(d);
4817 +
4818 + *hi = qb_attr_code_decode(&code_fq_ctx_upper32, p);
4819 + *lo = qb_attr_code_decode(&code_fq_ctx_lower32, p);
4820 +}
4821 +
4822 +void qbman_fq_attr_get_icid(struct qbman_attr *d, u32 *icid, int *pl)
4823 +{
4824 + u32 *p = ATTR32(d);
4825 +
4826 + *icid = qb_attr_code_decode(&code_fq_icid, p);
4827 + *pl = !!qb_attr_code_decode(&code_fq_pl, p);
4828 +}
4829 +
4830 +void qbman_fq_attr_get_vfqid(struct qbman_attr *d, u32 *vfqid)
4831 +{
4832 + u32 *p = ATTR32(d);
4833 +
4834 + *vfqid = qb_attr_code_decode(&code_fq_vfqid, p);
4835 +}
4836 +
4837 +void qbman_fq_attr_get_erfqid(struct qbman_attr *d, u32 *erfqid)
4838 +{
4839 + u32 *p = ATTR32(d);
4840 +
4841 + *erfqid = qb_attr_code_decode(&code_fq_erfqid, p);
4842 +}
4843 +
4844 +/* Query FQ Non-Programmalbe Fields */
4845 +static struct qb_attr_code code_fq_np_state = QB_CODE(0, 16, 3);
4846 +static struct qb_attr_code code_fq_np_fe = QB_CODE(0, 19, 1);
4847 +static struct qb_attr_code code_fq_np_x = QB_CODE(0, 20, 1);
4848 +static struct qb_attr_code code_fq_np_r = QB_CODE(0, 21, 1);
4849 +static struct qb_attr_code code_fq_np_oe = QB_CODE(0, 22, 1);
4850 +static struct qb_attr_code code_fq_np_frm_cnt = QB_CODE(6, 0, 24);
4851 +static struct qb_attr_code code_fq_np_byte_cnt = QB_CODE(7, 0, 32);
4852 +
4853 +int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
4854 + struct qbman_attr *state)
4855 +{
4856 + u32 *p;
4857 + u32 verb, rslt;
4858 + u32 *d = ATTR32(state);
4859 +
4860 + qbman_fq_attr_clear(state);
4861 +
4862 + p = qbman_swp_mc_start(s);
4863 + if (!p)
4864 + return -EBUSY;
4865 + qb_attr_code_encode(&code_fq_fqid, p, fqid);
4866 + p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY_NP);
4867 +
4868 + /* Decode the outcome */
4869 + verb = qb_attr_code_decode(&code_generic_verb, p);
4870 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
4871 + WARN_ON(verb != QBMAN_FQ_QUERY_NP);
4872 +
4873 + /* Determine success or failure */
4874 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
4875 + pr_err("Query NP fields of FQID 0x%x failed, code=0x%02x\n",
4876 + fqid, rslt);
4877 + return -EIO;
4878 + }
4879 + word_copy(&d[0], &p[0], 16);
4880 + return 0;
4881 +}
4882 +
4883 +u32 qbman_fq_state_schedstate(const struct qbman_attr *state)
4884 +{
4885 + const u32 *p = ATTR32(state);
4886 +
4887 + return qb_attr_code_decode(&code_fq_np_state, p);
4888 +}
4889 +
4890 +int qbman_fq_state_force_eligible(const struct qbman_attr *state)
4891 +{
4892 + const u32 *p = ATTR32(state);
4893 +
4894 + return !!qb_attr_code_decode(&code_fq_np_fe, p);
4895 +}
4896 +
4897 +int qbman_fq_state_xoff(const struct qbman_attr *state)
4898 +{
4899 + const u32 *p = ATTR32(state);
4900 +
4901 + return !!qb_attr_code_decode(&code_fq_np_x, p);
4902 +}
4903 +
4904 +int qbman_fq_state_retirement_pending(const struct qbman_attr *state)
4905 +{
4906 + const u32 *p = ATTR32(state);
4907 +
4908 + return !!qb_attr_code_decode(&code_fq_np_r, p);
4909 +}
4910 +
4911 +int qbman_fq_state_overflow_error(const struct qbman_attr *state)
4912 +{
4913 + const u32 *p = ATTR32(state);
4914 +
4915 + return !!qb_attr_code_decode(&code_fq_np_oe, p);
4916 +}
4917 +
4918 +u32 qbman_fq_state_frame_count(const struct qbman_attr *state)
4919 +{
4920 + const u32 *p = ATTR32(state);
4921 +
4922 + return qb_attr_code_decode(&code_fq_np_frm_cnt, p);
4923 +}
4924 +
4925 +u32 qbman_fq_state_byte_count(const struct qbman_attr *state)
4926 +{
4927 + const u32 *p = ATTR32(state);
4928 +
4929 + return qb_attr_code_decode(&code_fq_np_byte_cnt, p);
4930 +}
4931 +
4932 +/* Query CGR */
4933 +static struct qb_attr_code code_cgr_cgid = QB_CODE(0, 16, 16);
4934 +static struct qb_attr_code code_cgr_cscn_wq_en_enter = QB_CODE(2, 0, 1);
4935 +static struct qb_attr_code code_cgr_cscn_wq_en_exit = QB_CODE(2, 1, 1);
4936 +static struct qb_attr_code code_cgr_cscn_wq_icd = QB_CODE(2, 2, 1);
4937 +static struct qb_attr_code code_cgr_mode = QB_CODE(3, 16, 2);
4938 +static struct qb_attr_code code_cgr_rej_cnt_mode = QB_CODE(3, 18, 1);
4939 +static struct qb_attr_code code_cgr_cscn_bdi = QB_CODE(3, 19, 1);
4940 +static struct qb_attr_code code_cgr_cscn_wr_en_enter = QB_CODE(3, 24, 1);
4941 +static struct qb_attr_code code_cgr_cscn_wr_en_exit = QB_CODE(3, 25, 1);
4942 +static struct qb_attr_code code_cgr_cg_wr_ae = QB_CODE(3, 26, 1);
4943 +static struct qb_attr_code code_cgr_cscn_dcp_en = QB_CODE(3, 27, 1);
4944 +static struct qb_attr_code code_cgr_cg_wr_va = QB_CODE(3, 28, 1);
4945 +static struct qb_attr_code code_cgr_i_cnt_wr_en = QB_CODE(4, 0, 1);
4946 +static struct qb_attr_code code_cgr_i_cnt_wr_bnd = QB_CODE(4, 1, 5);
4947 +static struct qb_attr_code code_cgr_td_en = QB_CODE(4, 8, 1);
4948 +static struct qb_attr_code code_cgr_cs_thres = QB_CODE(4, 16, 13);
4949 +static struct qb_attr_code code_cgr_cs_thres_x = QB_CODE(5, 0, 13);
4950 +static struct qb_attr_code code_cgr_td_thres = QB_CODE(5, 16, 13);
4951 +static struct qb_attr_code code_cgr_cscn_tdcp = QB_CODE(6, 0, 16);
4952 +static struct qb_attr_code code_cgr_cscn_wqid = QB_CODE(6, 16, 16);
4953 +static struct qb_attr_code code_cgr_cscn_vcgid = QB_CODE(7, 0, 16);
4954 +static struct qb_attr_code code_cgr_cg_icid = QB_CODE(7, 16, 15);
4955 +static struct qb_attr_code code_cgr_cg_pl = QB_CODE(7, 31, 1);
4956 +static struct qb_attr_code code_cgr_cg_wr_addr_lo = QB_CODE(8, 0, 32);
4957 +static struct qb_attr_code code_cgr_cg_wr_addr_hi = QB_CODE(9, 0, 32);
4958 +static struct qb_attr_code code_cgr_cscn_ctx_lo = QB_CODE(10, 0, 32);
4959 +static struct qb_attr_code code_cgr_cscn_ctx_hi = QB_CODE(11, 0, 32);
4960 +
4961 +void qbman_cgr_attr_clear(struct qbman_attr *a)
4962 +{
4963 + memset(a, 0, sizeof(*a));
4964 + attr_type_set(a, qbman_attr_usage_cgr);
4965 +}
4966 +
4967 +int qbman_cgr_query(struct qbman_swp *s, u32 cgid, struct qbman_attr *attr)
4968 +{
4969 + u32 *p;
4970 + u32 verb, rslt;
4971 + u32 *d[2];
4972 + int i;
4973 + u32 query_verb;
4974 +
4975 + d[0] = ATTR32(attr);
4976 + d[1] = ATTR32_1(attr);
4977 +
4978 + qbman_cgr_attr_clear(attr);
4979 +
4980 + for (i = 0; i < 2; i++) {
4981 + p = qbman_swp_mc_start(s);
4982 + if (!p)
4983 + return -EBUSY;
4984 + query_verb = i ? QBMAN_WRED_QUERY : QBMAN_CGR_QUERY;
4985 +
4986 + qb_attr_code_encode(&code_cgr_cgid, p, cgid);
4987 + p = qbman_swp_mc_complete(s, p, p[0] | query_verb);
4988 +
4989 + /* Decode the outcome */
4990 + verb = qb_attr_code_decode(&code_generic_verb, p);
4991 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
4992 + WARN_ON(verb != query_verb);
4993 +
4994 + /* Determine success or failure */
4995 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
4996 + pr_err("Query CGID 0x%x failed,", cgid);
4997 + pr_err(" verb=0x%02x, code=0x%02x\n", verb, rslt);
4998 + return -EIO;
4999 + }
5000 + /* For the configure, word[0] of the command contains only the
5001 + * verb/cgid. For the query, word[0] of the result contains
5002 + * only the verb/rslt fields. Skip word[0] in the latter case.
5003 + */
5004 + word_copy(&d[i][1], &p[1], 15);
5005 + }
5006 + return 0;
5007 +}
5008 +
5009 +void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter,
5010 + int *cscn_wq_en_exit, int *cscn_wq_icd)
5011 + {
5012 + u32 *p = ATTR32(d);
5013 + *cscn_wq_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_enter,
5014 + p);
5015 + *cscn_wq_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_exit, p);
5016 + *cscn_wq_icd = !!qb_attr_code_decode(&code_cgr_cscn_wq_icd, p);
5017 +}
5018 +
5019 +void qbman_cgr_attr_get_mode(struct qbman_attr *d, u32 *mode,
5020 + int *rej_cnt_mode, int *cscn_bdi)
5021 +{
5022 + u32 *p = ATTR32(d);
5023 + *mode = qb_attr_code_decode(&code_cgr_mode, p);
5024 + *rej_cnt_mode = !!qb_attr_code_decode(&code_cgr_rej_cnt_mode, p);
5025 + *cscn_bdi = !!qb_attr_code_decode(&code_cgr_cscn_bdi, p);
5026 +}
5027 +
5028 +void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter,
5029 + int *cscn_wr_en_exit, int *cg_wr_ae,
5030 + int *cscn_dcp_en, int *cg_wr_va)
5031 +{
5032 + u32 *p = ATTR32(d);
5033 + *cscn_wr_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_enter,
5034 + p);
5035 + *cscn_wr_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_exit, p);
5036 + *cg_wr_ae = !!qb_attr_code_decode(&code_cgr_cg_wr_ae, p);
5037 + *cscn_dcp_en = !!qb_attr_code_decode(&code_cgr_cscn_dcp_en, p);
5038 + *cg_wr_va = !!qb_attr_code_decode(&code_cgr_cg_wr_va, p);
5039 +}
5040 +
5041 +void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en,
5042 + u32 *i_cnt_wr_bnd)
5043 +{
5044 + u32 *p = ATTR32(d);
5045 + *i_cnt_wr_en = !!qb_attr_code_decode(&code_cgr_i_cnt_wr_en, p);
5046 + *i_cnt_wr_bnd = qb_attr_code_decode(&code_cgr_i_cnt_wr_bnd, p);
5047 +}
5048 +
5049 +void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en)
5050 +{
5051 + u32 *p = ATTR32(d);
5052 + *td_en = !!qb_attr_code_decode(&code_cgr_td_en, p);
5053 +}
5054 +
5055 +void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, u32 *cs_thres)
5056 +{
5057 + u32 *p = ATTR32(d);
5058 + *cs_thres = qbman_thresh_to_value(qb_attr_code_decode(
5059 + &code_cgr_cs_thres, p));
5060 +}
5061 +
5062 +void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d,
5063 + u32 *cs_thres_x)
5064 +{
5065 + u32 *p = ATTR32(d);
5066 + *cs_thres_x = qbman_thresh_to_value(qb_attr_code_decode(
5067 + &code_cgr_cs_thres_x, p));
5068 +}
5069 +
5070 +void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, u32 *td_thres)
5071 +{
5072 + u32 *p = ATTR32(d);
5073 + *td_thres = qbman_thresh_to_value(qb_attr_code_decode(
5074 + &code_cgr_td_thres, p));
5075 +}
5076 +
5077 +void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, u32 *cscn_tdcp)
5078 +{
5079 + u32 *p = ATTR32(d);
5080 + *cscn_tdcp = qb_attr_code_decode(&code_cgr_cscn_tdcp, p);
5081 +}
5082 +
5083 +void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, u32 *cscn_wqid)
5084 +{
5085 + u32 *p = ATTR32(d);
5086 + *cscn_wqid = qb_attr_code_decode(&code_cgr_cscn_wqid, p);
5087 +}
5088 +
5089 +void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d,
5090 + u32 *cscn_vcgid)
5091 +{
5092 + u32 *p = ATTR32(d);
5093 + *cscn_vcgid = qb_attr_code_decode(&code_cgr_cscn_vcgid, p);
5094 +}
5095 +
5096 +void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, u32 *icid,
5097 + int *pl)
5098 +{
5099 + u32 *p = ATTR32(d);
5100 + *icid = qb_attr_code_decode(&code_cgr_cg_icid, p);
5101 + *pl = !!qb_attr_code_decode(&code_cgr_cg_pl, p);
5102 +}
5103 +
5104 +void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d,
5105 + u64 *cg_wr_addr)
5106 +{
5107 + u32 *p = ATTR32(d);
5108 + *cg_wr_addr = ((u64)qb_attr_code_decode(&code_cgr_cg_wr_addr_hi,
5109 + p) << 32) |
5110 + (u64)qb_attr_code_decode(&code_cgr_cg_wr_addr_lo,
5111 + p);
5112 +}
5113 +
5114 +void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, u64 *cscn_ctx)
5115 +{
5116 + u32 *p = ATTR32(d);
5117 + *cscn_ctx = ((u64)qb_attr_code_decode(&code_cgr_cscn_ctx_hi, p)
5118 + << 32) |
5119 + (u64)qb_attr_code_decode(&code_cgr_cscn_ctx_lo, p);
5120 +}
5121 +
5122 +#define WRED_EDP_WORD(n) (18 + (n) / 4)
5123 +#define WRED_EDP_OFFSET(n) (8 * ((n) % 4))
5124 +#define WRED_PARM_DP_WORD(n) ((n) + 20)
5125 +#define WRED_WE_EDP(n) (16 + (n) * 2)
5126 +#define WRED_WE_PARM_DP(n) (17 + (n) * 2)
5127 +void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, u32 idx,
5128 + int *edp)
5129 +{
5130 + u32 *p = ATTR32(d);
5131 + struct qb_attr_code code_wred_edp = QB_CODE(WRED_EDP_WORD(idx),
5132 + WRED_EDP_OFFSET(idx), 8);
5133 + *edp = (int)qb_attr_code_decode(&code_wred_edp, p);
5134 +}
5135 +
5136 +void qbman_cgr_attr_wred_dp_decompose(u32 dp, u64 *minth,
5137 + u64 *maxth, u8 *maxp)
5138 +{
5139 + u8 ma, mn, step_i, step_s, pn;
5140 +
5141 + ma = (u8)(dp >> 24);
5142 + mn = (u8)(dp >> 19) & 0x1f;
5143 + step_i = (u8)(dp >> 11);
5144 + step_s = (u8)(dp >> 6) & 0x1f;
5145 + pn = (u8)dp & 0x3f;
5146 +
5147 + *maxp = ((pn << 2) * 100) / 256;
5148 +
5149 + if (mn == 0)
5150 + *maxth = ma;
5151 + else
5152 + *maxth = ((ma + 256) * (1 << (mn - 1)));
5153 +
5154 + if (step_s == 0)
5155 + *minth = *maxth - step_i;
5156 + else
5157 + *minth = *maxth - (256 + step_i) * (1 << (step_s - 1));
5158 +}
5159 +
5160 +void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, u32 idx,
5161 + u32 *dp)
5162 +{
5163 + u32 *p = ATTR32(d);
5164 + struct qb_attr_code code_wred_parm_dp = QB_CODE(WRED_PARM_DP_WORD(idx),
5165 + 0, 8);
5166 + *dp = qb_attr_code_decode(&code_wred_parm_dp, p);
5167 +}
5168 +
5169 +/* Query CGR/CCGR/CQ statistics */
5170 +static struct qb_attr_code code_cgr_stat_ct = QB_CODE(4, 0, 32);
5171 +static struct qb_attr_code code_cgr_stat_frame_cnt_lo = QB_CODE(4, 0, 32);
5172 +static struct qb_attr_code code_cgr_stat_frame_cnt_hi = QB_CODE(5, 0, 8);
5173 +static struct qb_attr_code code_cgr_stat_byte_cnt_lo = QB_CODE(6, 0, 32);
5174 +static struct qb_attr_code code_cgr_stat_byte_cnt_hi = QB_CODE(7, 0, 16);
5175 +static int qbman_cgr_statistics_query(struct qbman_swp *s, u32 cgid,
5176 + int clear, u32 command_type,
5177 + u64 *frame_cnt, u64 *byte_cnt)
5178 +{
5179 + u32 *p;
5180 + u32 verb, rslt;
5181 + u32 query_verb;
5182 + u32 hi, lo;
5183 +
5184 + p = qbman_swp_mc_start(s);
5185 + if (!p)
5186 + return -EBUSY;
5187 +
5188 + qb_attr_code_encode(&code_cgr_cgid, p, cgid);
5189 + if (command_type < 2)
5190 + qb_attr_code_encode(&code_cgr_stat_ct, p, command_type);
5191 + query_verb = clear ?
5192 + QBMAN_CGR_STAT_QUERY_CLR : QBMAN_CGR_STAT_QUERY;
5193 + p = qbman_swp_mc_complete(s, p, p[0] | query_verb);
5194 +
5195 + /* Decode the outcome */
5196 + verb = qb_attr_code_decode(&code_generic_verb, p);
5197 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
5198 + WARN_ON(verb != query_verb);
5199 +
5200 + /* Determine success or failure */
5201 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
5202 + pr_err("Query statistics of CGID 0x%x failed,", cgid);
5203 + pr_err(" verb=0x%02x code=0x%02x\n", verb, rslt);
5204 + return -EIO;
5205 + }
5206 +
5207 + if (*frame_cnt) {
5208 + hi = qb_attr_code_decode(&code_cgr_stat_frame_cnt_hi, p);
5209 + lo = qb_attr_code_decode(&code_cgr_stat_frame_cnt_lo, p);
5210 + *frame_cnt = ((u64)hi << 32) | (u64)lo;
5211 + }
5212 + if (*byte_cnt) {
5213 + hi = qb_attr_code_decode(&code_cgr_stat_byte_cnt_hi, p);
5214 + lo = qb_attr_code_decode(&code_cgr_stat_byte_cnt_lo, p);
5215 + *byte_cnt = ((u64)hi << 32) | (u64)lo;
5216 + }
5217 +
5218 + return 0;
5219 +}
5220 +
5221 +int qbman_cgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5222 + u64 *frame_cnt, u64 *byte_cnt)
5223 +{
5224 + return qbman_cgr_statistics_query(s, cgid, clear, 0xff,
5225 + frame_cnt, byte_cnt);
5226 +}
5227 +
5228 +int qbman_ccgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5229 + u64 *frame_cnt, u64 *byte_cnt)
5230 +{
5231 + return qbman_cgr_statistics_query(s, cgid, clear, 1,
5232 + frame_cnt, byte_cnt);
5233 +}
5234 +
5235 +int qbman_cq_dequeue_statistics(struct qbman_swp *s, u32 cgid, int clear,
5236 + u64 *frame_cnt, u64 *byte_cnt)
5237 +{
5238 + return qbman_cgr_statistics_query(s, cgid, clear, 0,
5239 + frame_cnt, byte_cnt);
5240 +}
5241 --- /dev/null
5242 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.h
5243 @@ -0,0 +1,136 @@
5244 +/* Copyright (C) 2015 Freescale Semiconductor, Inc.
5245 + *
5246 + * Redistribution and use in source and binary forms, with or without
5247 + * modification, are permitted provided that the following conditions are met:
5248 + * * Redistributions of source code must retain the above copyright
5249 + * notice, this list of conditions and the following disclaimer.
5250 + * * Redistributions in binary form must reproduce the above copyright
5251 + * notice, this list of conditions and the following disclaimer in the
5252 + * documentation and/or other materials provided with the distribution.
5253 + * * Neither the name of Freescale Semiconductor nor the
5254 + * names of its contributors may be used to endorse or promote products
5255 + * derived from this software without specific prior written permission.
5256 + *
5257 + *
5258 + * ALTERNATIVELY, this software may be distributed under the terms of the
5259 + * GNU General Public License ("GPL") as published by the Free Software
5260 + * Foundation, either version 2 of that License or (at your option) any
5261 + * later version.
5262 + *
5263 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
5264 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
5265 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
5266 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
5267 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5268 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
5269 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
5270 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5271 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
5272 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5273 + */
5274 +
5275 +struct qbman_attr {
5276 + u32 dont_manipulate_directly[40];
5277 +};
5278 +
5279 +/* Buffer pool query commands */
5280 +int qbman_bp_query(struct qbman_swp *s, u32 bpid,
5281 + struct qbman_attr *a);
5282 +void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae);
5283 +void qbman_bp_attr_get_swdet(struct qbman_attr *a, u32 *swdet);
5284 +void qbman_bp_attr_get_swdxt(struct qbman_attr *a, u32 *swdxt);
5285 +void qbman_bp_attr_get_hwdet(struct qbman_attr *a, u32 *hwdet);
5286 +void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, u32 *hwdxt);
5287 +void qbman_bp_attr_get_swset(struct qbman_attr *a, u32 *swset);
5288 +void qbman_bp_attr_get_swsxt(struct qbman_attr *a, u32 *swsxt);
5289 +void qbman_bp_attr_get_vbpid(struct qbman_attr *a, u32 *vbpid);
5290 +void qbman_bp_attr_get_icid(struct qbman_attr *a, u32 *icid, int *pl);
5291 +void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, u64 *bpscn_addr);
5292 +void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, u64 *bpscn_ctx);
5293 +void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, u32 *hw_targ);
5294 +int qbman_bp_info_has_free_bufs(struct qbman_attr *a);
5295 +int qbman_bp_info_is_depleted(struct qbman_attr *a);
5296 +int qbman_bp_info_is_surplus(struct qbman_attr *a);
5297 +u32 qbman_bp_info_num_free_bufs(struct qbman_attr *a);
5298 +u32 qbman_bp_info_hdptr(struct qbman_attr *a);
5299 +u32 qbman_bp_info_sdcnt(struct qbman_attr *a);
5300 +u32 qbman_bp_info_hdcnt(struct qbman_attr *a);
5301 +u32 qbman_bp_info_sscnt(struct qbman_attr *a);
5302 +
5303 +/* FQ query function for programmable fields */
5304 +int qbman_fq_query(struct qbman_swp *s, u32 fqid,
5305 + struct qbman_attr *desc);
5306 +void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, u32 *fqctrl);
5307 +void qbman_fq_attr_get_cgrid(struct qbman_attr *d, u32 *cgrid);
5308 +void qbman_fq_attr_get_destwq(struct qbman_attr *d, u32 *destwq);
5309 +void qbman_fq_attr_get_icscred(struct qbman_attr *d, u32 *icscred);
5310 +void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, u32 *tdthresh);
5311 +void qbman_fq_attr_get_oa(struct qbman_attr *d,
5312 + int *oa_ics, int *oa_cgr, int32_t *oa_len);
5313 +void qbman_fq_attr_get_mctl(struct qbman_attr *d,
5314 + int *bdi, int *ff, int *va, int *ps);
5315 +void qbman_fq_attr_get_ctx(struct qbman_attr *d, u32 *hi, u32 *lo);
5316 +void qbman_fq_attr_get_icid(struct qbman_attr *d, u32 *icid, int *pl);
5317 +void qbman_fq_attr_get_vfqid(struct qbman_attr *d, u32 *vfqid);
5318 +void qbman_fq_attr_get_erfqid(struct qbman_attr *d, u32 *erfqid);
5319 +
5320 +/* FQ query command for non-programmable fields*/
5321 +enum qbman_fq_schedstate_e {
5322 + qbman_fq_schedstate_oos = 0,
5323 + qbman_fq_schedstate_retired,
5324 + qbman_fq_schedstate_tentatively_scheduled,
5325 + qbman_fq_schedstate_truly_scheduled,
5326 + qbman_fq_schedstate_parked,
5327 + qbman_fq_schedstate_held_active,
5328 +};
5329 +
5330 +int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
5331 + struct qbman_attr *state);
5332 +u32 qbman_fq_state_schedstate(const struct qbman_attr *state);
5333 +int qbman_fq_state_force_eligible(const struct qbman_attr *state);
5334 +int qbman_fq_state_xoff(const struct qbman_attr *state);
5335 +int qbman_fq_state_retirement_pending(const struct qbman_attr *state);
5336 +int qbman_fq_state_overflow_error(const struct qbman_attr *state);
5337 +u32 qbman_fq_state_frame_count(const struct qbman_attr *state);
5338 +u32 qbman_fq_state_byte_count(const struct qbman_attr *state);
5339 +
5340 +/* CGR query */
5341 +int qbman_cgr_query(struct qbman_swp *s, u32 cgid,
5342 + struct qbman_attr *attr);
5343 +void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter,
5344 + int *cscn_wq_en_exit, int *cscn_wq_icd);
5345 +void qbman_cgr_attr_get_mode(struct qbman_attr *d, u32 *mode,
5346 + int *rej_cnt_mode, int *cscn_bdi);
5347 +void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter,
5348 + int *cscn_wr_en_exit, int *cg_wr_ae,
5349 + int *cscn_dcp_en, int *cg_wr_va);
5350 +void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en,
5351 + u32 *i_cnt_wr_bnd);
5352 +void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en);
5353 +void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, u32 *cs_thres);
5354 +void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d,
5355 + u32 *cs_thres_x);
5356 +void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, u32 *td_thres);
5357 +void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, u32 *cscn_tdcp);
5358 +void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, u32 *cscn_wqid);
5359 +void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d,
5360 + u32 *cscn_vcgid);
5361 +void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, u32 *icid,
5362 + int *pl);
5363 +void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d,
5364 + u64 *cg_wr_addr);
5365 +void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, u64 *cscn_ctx);
5366 +void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, u32 idx,
5367 + int *edp);
5368 +void qbman_cgr_attr_wred_dp_decompose(u32 dp, u64 *minth,
5369 + u64 *maxth, u8 *maxp);
5370 +void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, u32 idx,
5371 + u32 *dp);
5372 +
5373 +/* CGR/CCGR/CQ statistics query */
5374 +int qbman_cgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5375 + u64 *frame_cnt, u64 *byte_cnt);
5376 +int qbman_ccgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5377 + u64 *frame_cnt, u64 *byte_cnt);
5378 +int qbman_cq_dequeue_statistics(struct qbman_swp *s, u32 cgid, int clear,
5379 + u64 *frame_cnt, u64 *byte_cnt);
5380 --- /dev/null
5381 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_private.h
5382 @@ -0,0 +1,171 @@
5383 +/* Copyright (C) 2014 Freescale Semiconductor, Inc.
5384 + *
5385 + * Redistribution and use in source and binary forms, with or without
5386 + * modification, are permitted provided that the following conditions are met:
5387 + * * Redistributions of source code must retain the above copyright
5388 + * notice, this list of conditions and the following disclaimer.
5389 + * * Redistributions in binary form must reproduce the above copyright
5390 + * notice, this list of conditions and the following disclaimer in the
5391 + * documentation and/or other materials provided with the distribution.
5392 + * * Neither the name of Freescale Semiconductor nor the
5393 + * names of its contributors may be used to endorse or promote products
5394 + * derived from this software without specific prior written permission.
5395 + *
5396 + *
5397 + * ALTERNATIVELY, this software may be distributed under the terms of the
5398 + * GNU General Public License ("GPL") as published by the Free Software
5399 + * Foundation, either version 2 of that License or (at your option) any
5400 + * later version.
5401 + *
5402 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
5403 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
5404 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
5405 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
5406 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5407 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
5408 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
5409 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5410 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
5411 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5412 + */
5413 +
5414 +/* Perform extra checking */
5415 +#define QBMAN_CHECKING
5416 +
5417 +/* To maximise the amount of logic that is common between the Linux driver and
5418 + * other targets (such as the embedded MC firmware), we pivot here between the
5419 + * inclusion of two platform-specific headers.
5420 + *
5421 + * The first, qbman_sys_decl.h, includes any and all required system headers as
5422 + * well as providing any definitions for the purposes of compatibility. The
5423 + * second, qbman_sys.h, is where platform-specific routines go.
5424 + *
5425 + * The point of the split is that the platform-independent code (including this
5426 + * header) may depend on platform-specific declarations, yet other
5427 + * platform-specific routines may depend on platform-independent definitions.
5428 + */
5429 +
5430 +#define QMAN_REV_4000 0x04000000
5431 +#define QMAN_REV_4100 0x04010000
5432 +#define QMAN_REV_4101 0x04010001
5433 +
5434 +/* When things go wrong, it is a convenient trick to insert a few FOO()
5435 + * statements in the code to trace progress. TODO: remove this once we are
5436 + * hacking the code less actively.
5437 + */
5438 +#define FOO() fsl_os_print("FOO: %s:%d\n", __FILE__, __LINE__)
5439 +
5440 +/* Any time there is a register interface which we poll on, this provides a
5441 + * "break after x iterations" scheme for it. It's handy for debugging, eg.
5442 + * where you don't want millions of lines of log output from a polling loop
5443 + * that won't, because such things tend to drown out the earlier log output
5444 + * that might explain what caused the problem. (NB: put ";" after each macro!)
5445 + * TODO: we should probably remove this once we're done sanitising the
5446 + * simulator...
5447 + */
5448 +#define DBG_POLL_START(loopvar) (loopvar = 1000)
5449 +#define DBG_POLL_CHECK(loopvar) \
5450 + do {if (!((loopvar)--)) WARN_ON(1); } while (0)
5451 +
5452 +/* For CCSR or portal-CINH registers that contain fields at arbitrary offsets
5453 + * and widths, these macro-generated encode/decode/isolate/remove inlines can
5454 + * be used.
5455 + *
5456 + * Eg. to "d"ecode a 14-bit field out of a register (into a "u16" type),
5457 + * where the field is located 3 bits "up" from the least-significant bit of the
5458 + * register (ie. the field location within the 32-bit register corresponds to a
5459 + * mask of 0x0001fff8), you would do;
5460 + * u16 field = d32_u16(3, 14, reg_value);
5461 + *
5462 + * Or to "e"ncode a 1-bit boolean value (input type is "int", zero is FALSE,
5463 + * non-zero is TRUE, so must convert all non-zero inputs to 1, hence the "!!"
5464 + * operator) into a register at bit location 0x00080000 (19 bits "in" from the
5465 + * LS bit), do;
5466 + * reg_value |= e32_int(19, 1, !!field);
5467 + *
5468 + * If you wish to read-modify-write a register, such that you leave the 14-bit
5469 + * field as-is but have all other fields set to zero, then "i"solate the 14-bit
5470 + * value using;
5471 + * reg_value = i32_u16(3, 14, reg_value);
5472 + *
5473 + * Alternatively, you could "r"emove the 1-bit boolean field (setting it to
5474 + * zero) but leaving all other fields as-is;
5475 + * reg_val = r32_int(19, 1, reg_value);
5476 + *
5477 + */
5478 +#define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \
5479 + (u32)((1 << width) - 1))
5480 +#define DECLARE_CODEC32(t) \
5481 +static inline u32 e32_##t(u32 lsoffset, u32 width, t val) \
5482 +{ \
5483 + WARN_ON(width > (sizeof(t) * 8)); \
5484 + return ((u32)val & MAKE_MASK32(width)) << lsoffset; \
5485 +} \
5486 +static inline t d32_##t(u32 lsoffset, u32 width, u32 val) \
5487 +{ \
5488 + WARN_ON(width > (sizeof(t) * 8)); \
5489 + return (t)((val >> lsoffset) & MAKE_MASK32(width)); \
5490 +} \
5491 +static inline u32 i32_##t(u32 lsoffset, u32 width, \
5492 + u32 val) \
5493 +{ \
5494 + WARN_ON(width > (sizeof(t) * 8)); \
5495 + return e32_##t(lsoffset, width, d32_##t(lsoffset, width, val)); \
5496 +} \
5497 +static inline u32 r32_##t(u32 lsoffset, u32 width, \
5498 + u32 val) \
5499 +{ \
5500 + WARN_ON(width > (sizeof(t) * 8)); \
5501 + return ~(MAKE_MASK32(width) << lsoffset) & val; \
5502 +}
5503 +DECLARE_CODEC32(u32)
5504 +DECLARE_CODEC32(u16)
5505 +DECLARE_CODEC32(u8)
5506 +DECLARE_CODEC32(int)
5507 +
5508 + /*********************/
5509 + /* Debugging assists */
5510 + /*********************/
5511 +
5512 +static inline void __hexdump(unsigned long start, unsigned long end,
5513 + unsigned long p, size_t sz,
5514 + const unsigned char *c)
5515 +{
5516 + while (start < end) {
5517 + unsigned int pos = 0;
5518 + char buf[64];
5519 + int nl = 0;
5520 +
5521 + pos += sprintf(buf + pos, "%08lx: ", start);
5522 + do {
5523 + if ((start < p) || (start >= (p + sz)))
5524 + pos += sprintf(buf + pos, "..");
5525 + else
5526 + pos += sprintf(buf + pos, "%02x", *(c++));
5527 + if (!(++start & 15)) {
5528 + buf[pos++] = '\n';
5529 + nl = 1;
5530 + } else {
5531 + nl = 0;
5532 + if (!(start & 1))
5533 + buf[pos++] = ' ';
5534 + if (!(start & 3))
5535 + buf[pos++] = ' ';
5536 + }
5537 + } while (start & 15);
5538 + if (!nl)
5539 + buf[pos++] = '\n';
5540 + buf[pos] = '\0';
5541 + pr_info("%s", buf);
5542 + }
5543 +}
5544 +
5545 +static inline void hexdump(const void *ptr, size_t sz)
5546 +{
5547 + unsigned long p = (unsigned long)ptr;
5548 + unsigned long start = p & ~15ul;
5549 + unsigned long end = (p + sz + 15) & ~15ul;
5550 + const unsigned char *c = ptr;
5551 +
5552 + __hexdump(start, end, p, sz, c);
5553 +}
5554 --- a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
5555 +++ b/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
5556 @@ -1,4 +1,5 @@
5557 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
5558 +/*
5559 + * Copyright 2013-2016 Freescale Semiconductor Inc.
5560 *
5561 * Redistribution and use in source and binary forms, with or without
5562 * modification, are permitted provided that the following conditions are met:
5563 @@ -11,7 +12,6 @@
5564 * names of any contributors may be used to endorse or promote products
5565 * derived from this software without specific prior written permission.
5566 *
5567 - *
5568 * ALTERNATIVELY, this software may be distributed under the terms of the
5569 * GNU General Public License ("GPL") as published by the Free Software
5570 * Foundation, either version 2 of that License or (at your option) any
5571 @@ -33,108 +33,24 @@
5572 #define _FSL_DPMCP_CMD_H
5573  
5574 /* Minimal supported DPMCP Version */
5575 -#define DPMCP_MIN_VER_MAJOR 3
5576 -#define DPMCP_MIN_VER_MINOR 0
5577 -
5578 -/* Command IDs */
5579 -#define DPMCP_CMDID_CLOSE 0x800
5580 -#define DPMCP_CMDID_OPEN 0x80b
5581 -#define DPMCP_CMDID_CREATE 0x90b
5582 -#define DPMCP_CMDID_DESTROY 0x900
5583 -
5584 -#define DPMCP_CMDID_GET_ATTR 0x004
5585 -#define DPMCP_CMDID_RESET 0x005
5586 -
5587 -#define DPMCP_CMDID_SET_IRQ 0x010
5588 -#define DPMCP_CMDID_GET_IRQ 0x011
5589 -#define DPMCP_CMDID_SET_IRQ_ENABLE 0x012
5590 -#define DPMCP_CMDID_GET_IRQ_ENABLE 0x013
5591 -#define DPMCP_CMDID_SET_IRQ_MASK 0x014
5592 -#define DPMCP_CMDID_GET_IRQ_MASK 0x015
5593 -#define DPMCP_CMDID_GET_IRQ_STATUS 0x016
5594 -
5595 -struct dpmcp_cmd_open {
5596 - __le32 dpmcp_id;
5597 -};
5598 -
5599 -struct dpmcp_cmd_create {
5600 - __le32 portal_id;
5601 -};
5602 -
5603 -struct dpmcp_cmd_set_irq {
5604 - /* cmd word 0 */
5605 - u8 irq_index;
5606 - u8 pad[3];
5607 - __le32 irq_val;
5608 - /* cmd word 1 */
5609 - __le64 irq_addr;
5610 - /* cmd word 2 */
5611 - __le32 irq_num;
5612 -};
5613 -
5614 -struct dpmcp_cmd_get_irq {
5615 - __le32 pad;
5616 - u8 irq_index;
5617 -};
5618 -
5619 -struct dpmcp_rsp_get_irq {
5620 - /* cmd word 0 */
5621 - __le32 irq_val;
5622 - __le32 pad;
5623 - /* cmd word 1 */
5624 - __le64 irq_paddr;
5625 - /* cmd word 2 */
5626 - __le32 irq_num;
5627 - __le32 type;
5628 -};
5629 +#define DPMCP_MIN_VER_MAJOR 3
5630 +#define DPMCP_MIN_VER_MINOR 0
5631  
5632 -#define DPMCP_ENABLE 0x1
5633 +/* Command versioning */
5634 +#define DPMCP_CMD_BASE_VERSION 1
5635 +#define DPMCP_CMD_ID_OFFSET 4
5636  
5637 -struct dpmcp_cmd_set_irq_enable {
5638 - u8 enable;
5639 - u8 pad[3];
5640 - u8 irq_index;
5641 -};
5642 +#define DPMCP_CMD(id) ((id << DPMCP_CMD_ID_OFFSET) | DPMCP_CMD_BASE_VERSION)
5643  
5644 -struct dpmcp_cmd_get_irq_enable {
5645 - __le32 pad;
5646 - u8 irq_index;
5647 -};
5648 -
5649 -struct dpmcp_rsp_get_irq_enable {
5650 - u8 enabled;
5651 -};
5652 -
5653 -struct dpmcp_cmd_set_irq_mask {
5654 - __le32 mask;
5655 - u8 irq_index;
5656 -};
5657 -
5658 -struct dpmcp_cmd_get_irq_mask {
5659 - __le32 pad;
5660 - u8 irq_index;
5661 -};
5662 -
5663 -struct dpmcp_rsp_get_irq_mask {
5664 - __le32 mask;
5665 -};
5666 +/* Command IDs */
5667 +#define DPMCP_CMDID_CLOSE DPMCP_CMD(0x800)
5668 +#define DPMCP_CMDID_OPEN DPMCP_CMD(0x80b)
5669 +#define DPMCP_CMDID_GET_API_VERSION DPMCP_CMD(0xa0b)
5670  
5671 -struct dpmcp_cmd_get_irq_status {
5672 - __le32 status;
5673 - u8 irq_index;
5674 -};
5675 +#define DPMCP_CMDID_RESET DPMCP_CMD(0x005)
5676  
5677 -struct dpmcp_rsp_get_irq_status {
5678 - __le32 status;
5679 -};
5680 -
5681 -struct dpmcp_rsp_get_attributes {
5682 - /* response word 0 */
5683 - __le32 pad;
5684 - __le32 id;
5685 - /* response word 1 */
5686 - __le16 version_major;
5687 - __le16 version_minor;
5688 +struct dpmcp_cmd_open {
5689 + __le32 dpmcp_id;
5690 };
5691  
5692 #endif /* _FSL_DPMCP_CMD_H */
5693 --- a/drivers/staging/fsl-mc/bus/dpmcp.c
5694 +++ b/drivers/staging/fsl-mc/bus/dpmcp.c
5695 @@ -1,4 +1,5 @@
5696 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
5697 +/*
5698 + * Copyright 2013-2016 Freescale Semiconductor Inc.
5699 *
5700 * Redistribution and use in source and binary forms, with or without
5701 * modification, are permitted provided that the following conditions are met:
5702 @@ -11,7 +12,6 @@
5703 * names of any contributors may be used to endorse or promote products
5704 * derived from this software without specific prior written permission.
5705 *
5706 - *
5707 * ALTERNATIVELY, this software may be distributed under the terms of the
5708 * GNU General Public License ("GPL") as published by the Free Software
5709 * Foundation, either version 2 of that License or (at your option) any
5710 @@ -104,76 +104,6 @@ int dpmcp_close(struct fsl_mc_io *mc_io,
5711 }
5712  
5713 /**
5714 - * dpmcp_create() - Create the DPMCP object.
5715 - * @mc_io: Pointer to MC portal's I/O object
5716 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5717 - * @cfg: Configuration structure
5718 - * @token: Returned token; use in subsequent API calls
5719 - *
5720 - * Create the DPMCP object, allocate required resources and
5721 - * perform required initialization.
5722 - *
5723 - * The object can be created either by declaring it in the
5724 - * DPL file, or by calling this function.
5725 - * This function returns a unique authentication token,
5726 - * associated with the specific object ID and the specific MC
5727 - * portal; this token must be used in all subsequent calls to
5728 - * this specific object. For objects that are created using the
5729 - * DPL file, call dpmcp_open function to get an authentication
5730 - * token first.
5731 - *
5732 - * Return: '0' on Success; Error code otherwise.
5733 - */
5734 -int dpmcp_create(struct fsl_mc_io *mc_io,
5735 - u32 cmd_flags,
5736 - const struct dpmcp_cfg *cfg,
5737 - u16 *token)
5738 -{
5739 - struct mc_command cmd = { 0 };
5740 - struct dpmcp_cmd_create *cmd_params;
5741 -
5742 - int err;
5743 -
5744 - /* prepare command */
5745 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CREATE,
5746 - cmd_flags, 0);
5747 - cmd_params = (struct dpmcp_cmd_create *)cmd.params;
5748 - cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
5749 -
5750 - /* send command to mc*/
5751 - err = mc_send_command(mc_io, &cmd);
5752 - if (err)
5753 - return err;
5754 -
5755 - /* retrieve response parameters */
5756 - *token = mc_cmd_hdr_read_token(&cmd);
5757 -
5758 - return 0;
5759 -}
5760 -
5761 -/**
5762 - * dpmcp_destroy() - Destroy the DPMCP object and release all its resources.
5763 - * @mc_io: Pointer to MC portal's I/O object
5764 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5765 - * @token: Token of DPMCP object
5766 - *
5767 - * Return: '0' on Success; error code otherwise.
5768 - */
5769 -int dpmcp_destroy(struct fsl_mc_io *mc_io,
5770 - u32 cmd_flags,
5771 - u16 token)
5772 -{
5773 - struct mc_command cmd = { 0 };
5774 -
5775 - /* prepare command */
5776 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_DESTROY,
5777 - cmd_flags, token);
5778 -
5779 - /* send command to mc*/
5780 - return mc_send_command(mc_io, &cmd);
5781 -}
5782 -
5783 -/**
5784 * dpmcp_reset() - Reset the DPMCP, returns the object to initial state.
5785 * @mc_io: Pointer to MC portal's I/O object
5786 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5787 @@ -196,309 +126,33 @@ int dpmcp_reset(struct fsl_mc_io *mc_io,
5788 }
5789  
5790 /**
5791 - * dpmcp_set_irq() - Set IRQ information for the DPMCP to trigger an interrupt.
5792 - * @mc_io: Pointer to MC portal's I/O object
5793 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5794 - * @token: Token of DPMCP object
5795 - * @irq_index: Identifies the interrupt index to configure
5796 - * @irq_cfg: IRQ configuration
5797 - *
5798 - * Return: '0' on Success; Error code otherwise.
5799 - */
5800 -int dpmcp_set_irq(struct fsl_mc_io *mc_io,
5801 - u32 cmd_flags,
5802 - u16 token,
5803 - u8 irq_index,
5804 - struct dpmcp_irq_cfg *irq_cfg)
5805 -{
5806 - struct mc_command cmd = { 0 };
5807 - struct dpmcp_cmd_set_irq *cmd_params;
5808 -
5809 - /* prepare command */
5810 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ,
5811 - cmd_flags, token);
5812 - cmd_params = (struct dpmcp_cmd_set_irq *)cmd.params;
5813 - cmd_params->irq_index = irq_index;
5814 - cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
5815 - cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr);
5816 - cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
5817 -
5818 - /* send command to mc*/
5819 - return mc_send_command(mc_io, &cmd);
5820 -}
5821 -
5822 -/**
5823 - * dpmcp_get_irq() - Get IRQ information from the DPMCP.
5824 - * @mc_io: Pointer to MC portal's I/O object
5825 + * dpmcp_get_api_version - Get Data Path Management Command Portal API version
5826 + * @mc_io: Pointer to Mc portal's I/O object
5827 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5828 - * @token: Token of DPMCP object
5829 - * @irq_index: The interrupt index to configure
5830 - * @type: Interrupt type: 0 represents message interrupt
5831 - * type (both irq_addr and irq_val are valid)
5832 - * @irq_cfg: IRQ attributes
5833 + * @major_ver: Major version of Data Path Management Command Portal API
5834 + * @minor_ver: Minor version of Data Path Management Command Portal API
5835 *
5836 * Return: '0' on Success; Error code otherwise.
5837 */
5838 -int dpmcp_get_irq(struct fsl_mc_io *mc_io,
5839 - u32 cmd_flags,
5840 - u16 token,
5841 - u8 irq_index,
5842 - int *type,
5843 - struct dpmcp_irq_cfg *irq_cfg)
5844 +int dpmcp_get_api_version(struct fsl_mc_io *mc_io,
5845 + u32 cmd_flags,
5846 + u16 *major_ver,
5847 + u16 *minor_ver)
5848 {
5849 struct mc_command cmd = { 0 };
5850 - struct dpmcp_cmd_get_irq *cmd_params;
5851 - struct dpmcp_rsp_get_irq *rsp_params;
5852 int err;
5853  
5854 /* prepare command */
5855 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ,
5856 - cmd_flags, token);
5857 - cmd_params = (struct dpmcp_cmd_get_irq *)cmd.params;
5858 - cmd_params->irq_index = irq_index;
5859 -
5860 - /* send command to mc*/
5861 - err = mc_send_command(mc_io, &cmd);
5862 - if (err)
5863 - return err;
5864 -
5865 - /* retrieve response parameters */
5866 - rsp_params = (struct dpmcp_rsp_get_irq *)cmd.params;
5867 - irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
5868 - irq_cfg->paddr = le64_to_cpu(rsp_params->irq_paddr);
5869 - irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
5870 - *type = le32_to_cpu(rsp_params->type);
5871 - return 0;
5872 -}
5873 -
5874 -/**
5875 - * dpmcp_set_irq_enable() - Set overall interrupt state.
5876 - * @mc_io: Pointer to MC portal's I/O object
5877 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5878 - * @token: Token of DPMCP object
5879 - * @irq_index: The interrupt index to configure
5880 - * @en: Interrupt state - enable = 1, disable = 0
5881 - *
5882 - * Allows GPP software to control when interrupts are generated.
5883 - * Each interrupt can have up to 32 causes. The enable/disable control's the
5884 - * overall interrupt state. if the interrupt is disabled no causes will cause
5885 - * an interrupt.
5886 - *
5887 - * Return: '0' on Success; Error code otherwise.
5888 - */
5889 -int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
5890 - u32 cmd_flags,
5891 - u16 token,
5892 - u8 irq_index,
5893 - u8 en)
5894 -{
5895 - struct mc_command cmd = { 0 };
5896 - struct dpmcp_cmd_set_irq_enable *cmd_params;
5897 -
5898 - /* prepare command */
5899 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_ENABLE,
5900 - cmd_flags, token);
5901 - cmd_params = (struct dpmcp_cmd_set_irq_enable *)cmd.params;
5902 - cmd_params->enable = en & DPMCP_ENABLE;
5903 - cmd_params->irq_index = irq_index;
5904 -
5905 - /* send command to mc*/
5906 - return mc_send_command(mc_io, &cmd);
5907 -}
5908 -
5909 -/**
5910 - * dpmcp_get_irq_enable() - Get overall interrupt state
5911 - * @mc_io: Pointer to MC portal's I/O object
5912 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5913 - * @token: Token of DPMCP object
5914 - * @irq_index: The interrupt index to configure
5915 - * @en: Returned interrupt state - enable = 1, disable = 0
5916 - *
5917 - * Return: '0' on Success; Error code otherwise.
5918 - */
5919 -int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
5920 - u32 cmd_flags,
5921 - u16 token,
5922 - u8 irq_index,
5923 - u8 *en)
5924 -{
5925 - struct mc_command cmd = { 0 };
5926 - struct dpmcp_cmd_get_irq_enable *cmd_params;
5927 - struct dpmcp_rsp_get_irq_enable *rsp_params;
5928 - int err;
5929 -
5930 - /* prepare command */
5931 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_ENABLE,
5932 - cmd_flags, token);
5933 - cmd_params = (struct dpmcp_cmd_get_irq_enable *)cmd.params;
5934 - cmd_params->irq_index = irq_index;
5935 -
5936 - /* send command to mc*/
5937 - err = mc_send_command(mc_io, &cmd);
5938 - if (err)
5939 - return err;
5940 -
5941 - /* retrieve response parameters */
5942 - rsp_params = (struct dpmcp_rsp_get_irq_enable *)cmd.params;
5943 - *en = rsp_params->enabled & DPMCP_ENABLE;
5944 - return 0;
5945 -}
5946 -
5947 -/**
5948 - * dpmcp_set_irq_mask() - Set interrupt mask.
5949 - * @mc_io: Pointer to MC portal's I/O object
5950 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5951 - * @token: Token of DPMCP object
5952 - * @irq_index: The interrupt index to configure
5953 - * @mask: Event mask to trigger interrupt;
5954 - * each bit:
5955 - * 0 = ignore event
5956 - * 1 = consider event for asserting IRQ
5957 - *
5958 - * Every interrupt can have up to 32 causes and the interrupt model supports
5959 - * masking/unmasking each cause independently
5960 - *
5961 - * Return: '0' on Success; Error code otherwise.
5962 - */
5963 -int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
5964 - u32 cmd_flags,
5965 - u16 token,
5966 - u8 irq_index,
5967 - u32 mask)
5968 -{
5969 - struct mc_command cmd = { 0 };
5970 - struct dpmcp_cmd_set_irq_mask *cmd_params;
5971 -
5972 - /* prepare command */
5973 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_MASK,
5974 - cmd_flags, token);
5975 - cmd_params = (struct dpmcp_cmd_set_irq_mask *)cmd.params;
5976 - cmd_params->mask = cpu_to_le32(mask);
5977 - cmd_params->irq_index = irq_index;
5978 -
5979 - /* send command to mc*/
5980 - return mc_send_command(mc_io, &cmd);
5981 -}
5982 -
5983 -/**
5984 - * dpmcp_get_irq_mask() - Get interrupt mask.
5985 - * @mc_io: Pointer to MC portal's I/O object
5986 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5987 - * @token: Token of DPMCP object
5988 - * @irq_index: The interrupt index to configure
5989 - * @mask: Returned event mask to trigger interrupt
5990 - *
5991 - * Every interrupt can have up to 32 causes and the interrupt model supports
5992 - * masking/unmasking each cause independently
5993 - *
5994 - * Return: '0' on Success; Error code otherwise.
5995 - */
5996 -int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
5997 - u32 cmd_flags,
5998 - u16 token,
5999 - u8 irq_index,
6000 - u32 *mask)
6001 -{
6002 - struct mc_command cmd = { 0 };
6003 - struct dpmcp_cmd_get_irq_mask *cmd_params;
6004 - struct dpmcp_rsp_get_irq_mask *rsp_params;
6005 -
6006 - int err;
6007 -
6008 - /* prepare command */
6009 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_MASK,
6010 - cmd_flags, token);
6011 - cmd_params = (struct dpmcp_cmd_get_irq_mask *)cmd.params;
6012 - cmd_params->irq_index = irq_index;
6013 -
6014 - /* send command to mc*/
6015 - err = mc_send_command(mc_io, &cmd);
6016 - if (err)
6017 - return err;
6018 -
6019 - /* retrieve response parameters */
6020 - rsp_params = (struct dpmcp_rsp_get_irq_mask *)cmd.params;
6021 - *mask = le32_to_cpu(rsp_params->mask);
6022 -
6023 - return 0;
6024 -}
6025 -
6026 -/**
6027 - * dpmcp_get_irq_status() - Get the current status of any pending interrupts.
6028 - *
6029 - * @mc_io: Pointer to MC portal's I/O object
6030 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6031 - * @token: Token of DPMCP object
6032 - * @irq_index: The interrupt index to configure
6033 - * @status: Returned interrupts status - one bit per cause:
6034 - * 0 = no interrupt pending
6035 - * 1 = interrupt pending
6036 - *
6037 - * Return: '0' on Success; Error code otherwise.
6038 - */
6039 -int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
6040 - u32 cmd_flags,
6041 - u16 token,
6042 - u8 irq_index,
6043 - u32 *status)
6044 -{
6045 - struct mc_command cmd = { 0 };
6046 - struct dpmcp_cmd_get_irq_status *cmd_params;
6047 - struct dpmcp_rsp_get_irq_status *rsp_params;
6048 - int err;
6049 -
6050 - /* prepare command */
6051 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_STATUS,
6052 - cmd_flags, token);
6053 - cmd_params = (struct dpmcp_cmd_get_irq_status *)cmd.params;
6054 - cmd_params->status = cpu_to_le32(*status);
6055 - cmd_params->irq_index = irq_index;
6056 -
6057 - /* send command to mc*/
6058 - err = mc_send_command(mc_io, &cmd);
6059 - if (err)
6060 - return err;
6061 -
6062 - /* retrieve response parameters */
6063 - rsp_params = (struct dpmcp_rsp_get_irq_status *)cmd.params;
6064 - *status = le32_to_cpu(rsp_params->status);
6065 -
6066 - return 0;
6067 -}
6068 -
6069 -/**
6070 - * dpmcp_get_attributes - Retrieve DPMCP attributes.
6071 - *
6072 - * @mc_io: Pointer to MC portal's I/O object
6073 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6074 - * @token: Token of DPMCP object
6075 - * @attr: Returned object's attributes
6076 - *
6077 - * Return: '0' on Success; Error code otherwise.
6078 - */
6079 -int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
6080 - u32 cmd_flags,
6081 - u16 token,
6082 - struct dpmcp_attr *attr)
6083 -{
6084 - struct mc_command cmd = { 0 };
6085 - struct dpmcp_rsp_get_attributes *rsp_params;
6086 - int err;
6087 -
6088 - /* prepare command */
6089 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_ATTR,
6090 - cmd_flags, token);
6091 + cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_API_VERSION,
6092 + cmd_flags, 0);
6093  
6094 - /* send command to mc*/
6095 + /* send command to mc */
6096 err = mc_send_command(mc_io, &cmd);
6097 if (err)
6098 return err;
6099  
6100 /* retrieve response parameters */
6101 - rsp_params = (struct dpmcp_rsp_get_attributes *)cmd.params;
6102 - attr->id = le32_to_cpu(rsp_params->id);
6103 - attr->version.major = le16_to_cpu(rsp_params->version_major);
6104 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
6105 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
6106  
6107 return 0;
6108 }
6109 --- a/drivers/staging/fsl-mc/bus/dpmcp.h
6110 +++ b/drivers/staging/fsl-mc/bus/dpmcp.h
6111 @@ -1,4 +1,5 @@
6112 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
6113 +/*
6114 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6115 *
6116 * Redistribution and use in source and binary forms, with or without
6117 * modification, are permitted provided that the following conditions are met:
6118 @@ -11,7 +12,6 @@
6119 * names of any contributors may be used to endorse or promote products
6120 * derived from this software without specific prior written permission.
6121 *
6122 - *
6123 * ALTERNATIVELY, this software may be distributed under the terms of the
6124 * GNU General Public License ("GPL") as published by the Free Software
6125 * Foundation, either version 2 of that License or (at your option) any
6126 @@ -32,128 +32,29 @@
6127 #ifndef __FSL_DPMCP_H
6128 #define __FSL_DPMCP_H
6129  
6130 -/* Data Path Management Command Portal API
6131 +/*
6132 + * Data Path Management Command Portal API
6133 * Contains initialization APIs and runtime control APIs for DPMCP
6134 */
6135  
6136 struct fsl_mc_io;
6137  
6138 int dpmcp_open(struct fsl_mc_io *mc_io,
6139 - uint32_t cmd_flags,
6140 + u32 cmd_flags,
6141 int dpmcp_id,
6142 - uint16_t *token);
6143 -
6144 -/* Get portal ID from pool */
6145 -#define DPMCP_GET_PORTAL_ID_FROM_POOL (-1)
6146 + u16 *token);
6147  
6148 int dpmcp_close(struct fsl_mc_io *mc_io,
6149 - uint32_t cmd_flags,
6150 - uint16_t token);
6151 + u32 cmd_flags,
6152 + u16 token);
6153  
6154 -/**
6155 - * struct dpmcp_cfg - Structure representing DPMCP configuration
6156 - * @portal_id: Portal ID; 'DPMCP_GET_PORTAL_ID_FROM_POOL' to get the portal ID
6157 - * from pool
6158 - */
6159 -struct dpmcp_cfg {
6160 - int portal_id;
6161 -};
6162 -
6163 -int dpmcp_create(struct fsl_mc_io *mc_io,
6164 - uint32_t cmd_flags,
6165 - const struct dpmcp_cfg *cfg,
6166 - uint16_t *token);
6167 -
6168 -int dpmcp_destroy(struct fsl_mc_io *mc_io,
6169 - uint32_t cmd_flags,
6170 - uint16_t token);
6171 +int dpmcp_get_api_version(struct fsl_mc_io *mc_io,
6172 + u32 cmd_flags,
6173 + u16 *major_ver,
6174 + u16 *minor_ver);
6175  
6176 int dpmcp_reset(struct fsl_mc_io *mc_io,
6177 - uint32_t cmd_flags,
6178 - uint16_t token);
6179 -
6180 -/* IRQ */
6181 -/* IRQ Index */
6182 -#define DPMCP_IRQ_INDEX 0
6183 -/* irq event - Indicates that the link state changed */
6184 -#define DPMCP_IRQ_EVENT_CMD_DONE 0x00000001
6185 -
6186 -/**
6187 - * struct dpmcp_irq_cfg - IRQ configuration
6188 - * @paddr: Address that must be written to signal a message-based interrupt
6189 - * @val: Value to write into irq_addr address
6190 - * @irq_num: A user defined number associated with this IRQ
6191 - */
6192 -struct dpmcp_irq_cfg {
6193 - uint64_t paddr;
6194 - uint32_t val;
6195 - int irq_num;
6196 -};
6197 -
6198 -int dpmcp_set_irq(struct fsl_mc_io *mc_io,
6199 - uint32_t cmd_flags,
6200 - uint16_t token,
6201 - uint8_t irq_index,
6202 - struct dpmcp_irq_cfg *irq_cfg);
6203 -
6204 -int dpmcp_get_irq(struct fsl_mc_io *mc_io,
6205 - uint32_t cmd_flags,
6206 - uint16_t token,
6207 - uint8_t irq_index,
6208 - int *type,
6209 - struct dpmcp_irq_cfg *irq_cfg);
6210 -
6211 -int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
6212 - uint32_t cmd_flags,
6213 - uint16_t token,
6214 - uint8_t irq_index,
6215 - uint8_t en);
6216 -
6217 -int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
6218 - uint32_t cmd_flags,
6219 - uint16_t token,
6220 - uint8_t irq_index,
6221 - uint8_t *en);
6222 -
6223 -int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
6224 - uint32_t cmd_flags,
6225 - uint16_t token,
6226 - uint8_t irq_index,
6227 - uint32_t mask);
6228 -
6229 -int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
6230 - uint32_t cmd_flags,
6231 - uint16_t token,
6232 - uint8_t irq_index,
6233 - uint32_t *mask);
6234 -
6235 -int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
6236 - uint32_t cmd_flags,
6237 - uint16_t token,
6238 - uint8_t irq_index,
6239 - uint32_t *status);
6240 -
6241 -/**
6242 - * struct dpmcp_attr - Structure representing DPMCP attributes
6243 - * @id: DPMCP object ID
6244 - * @version: DPMCP version
6245 - */
6246 -struct dpmcp_attr {
6247 - int id;
6248 - /**
6249 - * struct version - Structure representing DPMCP version
6250 - * @major: DPMCP major version
6251 - * @minor: DPMCP minor version
6252 - */
6253 - struct {
6254 - uint16_t major;
6255 - uint16_t minor;
6256 - } version;
6257 -};
6258 -
6259 -int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
6260 - uint32_t cmd_flags,
6261 - uint16_t token,
6262 - struct dpmcp_attr *attr);
6263 + u32 cmd_flags,
6264 + u16 token);
6265  
6266 #endif /* __FSL_DPMCP_H */
6267 --- a/drivers/staging/fsl-mc/bus/dpmng-cmd.h
6268 +++ b/drivers/staging/fsl-mc/bus/dpmng-cmd.h
6269 @@ -12,7 +12,6 @@
6270 * names of any contributors may be used to endorse or promote products
6271 * derived from this software without specific prior written permission.
6272 *
6273 - *
6274 * ALTERNATIVELY, this software may be distributed under the terms of the
6275 * GNU General Public License ("GPL") as published by the Free Software
6276 * Foundation, either version 2 of that License or (at your option) any
6277 @@ -41,13 +40,14 @@
6278 #ifndef __FSL_DPMNG_CMD_H
6279 #define __FSL_DPMNG_CMD_H
6280  
6281 -/* Command IDs */
6282 -#define DPMNG_CMDID_GET_CONT_ID 0x830
6283 -#define DPMNG_CMDID_GET_VERSION 0x831
6284 +/* Command versioning */
6285 +#define DPMNG_CMD_BASE_VERSION 1
6286 +#define DPMNG_CMD_ID_OFFSET 4
6287  
6288 -struct dpmng_rsp_get_container_id {
6289 - __le32 container_id;
6290 -};
6291 +#define DPMNG_CMD(id) ((id << DPMNG_CMD_ID_OFFSET) | DPMNG_CMD_BASE_VERSION)
6292 +
6293 +/* Command IDs */
6294 +#define DPMNG_CMDID_GET_VERSION DPMNG_CMD(0x831)
6295  
6296 struct dpmng_rsp_get_version {
6297 __le32 revision;
6298 --- a/drivers/staging/fsl-mc/bus/dpmng.c
6299 +++ b/drivers/staging/fsl-mc/bus/dpmng.c
6300 @@ -1,4 +1,5 @@
6301 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
6302 +/*
6303 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6304 *
6305 * Redistribution and use in source and binary forms, with or without
6306 * modification, are permitted provided that the following conditions are met:
6307 @@ -11,7 +12,6 @@
6308 * names of any contributors may be used to endorse or promote products
6309 * derived from this software without specific prior written permission.
6310 *
6311 - *
6312 * ALTERNATIVELY, this software may be distributed under the terms of the
6313 * GNU General Public License ("GPL") as published by the Free Software
6314 * Foundation, either version 2 of that License or (at your option) any
6315 @@ -72,36 +72,3 @@ int mc_get_version(struct fsl_mc_io *mc_
6316 }
6317 EXPORT_SYMBOL(mc_get_version);
6318  
6319 -/**
6320 - * dpmng_get_container_id() - Get container ID associated with a given portal.
6321 - * @mc_io: Pointer to MC portal's I/O object
6322 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6323 - * @container_id: Requested container ID
6324 - *
6325 - * Return: '0' on Success; Error code otherwise.
6326 - */
6327 -int dpmng_get_container_id(struct fsl_mc_io *mc_io,
6328 - u32 cmd_flags,
6329 - int *container_id)
6330 -{
6331 - struct mc_command cmd = { 0 };
6332 - struct dpmng_rsp_get_container_id *rsp_params;
6333 - int err;
6334 -
6335 - /* prepare command */
6336 - cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_CONT_ID,
6337 - cmd_flags,
6338 - 0);
6339 -
6340 - /* send command to mc*/
6341 - err = mc_send_command(mc_io, &cmd);
6342 - if (err)
6343 - return err;
6344 -
6345 - /* retrieve response parameters */
6346 - rsp_params = (struct dpmng_rsp_get_container_id *)cmd.params;
6347 - *container_id = le32_to_cpu(rsp_params->container_id);
6348 -
6349 - return 0;
6350 -}
6351 -
6352 --- a/drivers/staging/fsl-mc/bus/dprc-cmd.h
6353 +++ b/drivers/staging/fsl-mc/bus/dprc-cmd.h
6354 @@ -12,7 +12,6 @@
6355 * names of any contributors may be used to endorse or promote products
6356 * derived from this software without specific prior written permission.
6357 *
6358 - *
6359 * ALTERNATIVELY, this software may be distributed under the terms of the
6360 * GNU General Public License ("GPL") as published by the Free Software
6361 * Foundation, either version 2 of that License or (at your option) any
6362 @@ -42,48 +41,39 @@
6363 #define _FSL_DPRC_CMD_H
6364  
6365 /* Minimal supported DPRC Version */
6366 -#define DPRC_MIN_VER_MAJOR 5
6367 +#define DPRC_MIN_VER_MAJOR 6
6368 #define DPRC_MIN_VER_MINOR 0
6369  
6370 -/* Command IDs */
6371 -#define DPRC_CMDID_CLOSE 0x800
6372 -#define DPRC_CMDID_OPEN 0x805
6373 -#define DPRC_CMDID_CREATE 0x905
6374 -
6375 -#define DPRC_CMDID_GET_ATTR 0x004
6376 -#define DPRC_CMDID_RESET_CONT 0x005
6377 -
6378 -#define DPRC_CMDID_SET_IRQ 0x010
6379 -#define DPRC_CMDID_GET_IRQ 0x011
6380 -#define DPRC_CMDID_SET_IRQ_ENABLE 0x012
6381 -#define DPRC_CMDID_GET_IRQ_ENABLE 0x013
6382 -#define DPRC_CMDID_SET_IRQ_MASK 0x014
6383 -#define DPRC_CMDID_GET_IRQ_MASK 0x015
6384 -#define DPRC_CMDID_GET_IRQ_STATUS 0x016
6385 -#define DPRC_CMDID_CLEAR_IRQ_STATUS 0x017
6386 -
6387 -#define DPRC_CMDID_CREATE_CONT 0x151
6388 -#define DPRC_CMDID_DESTROY_CONT 0x152
6389 -#define DPRC_CMDID_SET_RES_QUOTA 0x155
6390 -#define DPRC_CMDID_GET_RES_QUOTA 0x156
6391 -#define DPRC_CMDID_ASSIGN 0x157
6392 -#define DPRC_CMDID_UNASSIGN 0x158
6393 -#define DPRC_CMDID_GET_OBJ_COUNT 0x159
6394 -#define DPRC_CMDID_GET_OBJ 0x15A
6395 -#define DPRC_CMDID_GET_RES_COUNT 0x15B
6396 -#define DPRC_CMDID_GET_RES_IDS 0x15C
6397 -#define DPRC_CMDID_GET_OBJ_REG 0x15E
6398 -#define DPRC_CMDID_SET_OBJ_IRQ 0x15F
6399 -#define DPRC_CMDID_GET_OBJ_IRQ 0x160
6400 -#define DPRC_CMDID_SET_OBJ_LABEL 0x161
6401 -#define DPRC_CMDID_GET_OBJ_DESC 0x162
6402 -
6403 -#define DPRC_CMDID_CONNECT 0x167
6404 -#define DPRC_CMDID_DISCONNECT 0x168
6405 -#define DPRC_CMDID_GET_POOL 0x169
6406 -#define DPRC_CMDID_GET_POOL_COUNT 0x16A
6407 +/* Command versioning */
6408 +#define DPRC_CMD_BASE_VERSION 1
6409 +#define DPRC_CMD_ID_OFFSET 4
6410  
6411 -#define DPRC_CMDID_GET_CONNECTION 0x16C
6412 +#define DPRC_CMD(id) ((id << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION)
6413 +
6414 +/* Command IDs */
6415 +#define DPRC_CMDID_CLOSE DPRC_CMD(0x800)
6416 +#define DPRC_CMDID_OPEN DPRC_CMD(0x805)
6417 +#define DPRC_CMDID_GET_API_VERSION DPRC_CMD(0xa05)
6418 +
6419 +#define DPRC_CMDID_GET_ATTR DPRC_CMD(0x004)
6420 +#define DPRC_CMDID_RESET_CONT DPRC_CMD(0x005)
6421 +
6422 +#define DPRC_CMDID_SET_IRQ DPRC_CMD(0x010)
6423 +#define DPRC_CMDID_GET_IRQ DPRC_CMD(0x011)
6424 +#define DPRC_CMDID_SET_IRQ_ENABLE DPRC_CMD(0x012)
6425 +#define DPRC_CMDID_GET_IRQ_ENABLE DPRC_CMD(0x013)
6426 +#define DPRC_CMDID_SET_IRQ_MASK DPRC_CMD(0x014)
6427 +#define DPRC_CMDID_GET_IRQ_MASK DPRC_CMD(0x015)
6428 +#define DPRC_CMDID_GET_IRQ_STATUS DPRC_CMD(0x016)
6429 +#define DPRC_CMDID_CLEAR_IRQ_STATUS DPRC_CMD(0x017)
6430 +
6431 +#define DPRC_CMDID_GET_CONT_ID DPRC_CMD(0x830)
6432 +#define DPRC_CMDID_GET_OBJ_COUNT DPRC_CMD(0x159)
6433 +#define DPRC_CMDID_GET_OBJ DPRC_CMD(0x15A)
6434 +#define DPRC_CMDID_GET_RES_COUNT DPRC_CMD(0x15B)
6435 +#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD(0x15E)
6436 +#define DPRC_CMDID_SET_OBJ_IRQ DPRC_CMD(0x15F)
6437 +#define DPRC_CMDID_GET_OBJ_IRQ DPRC_CMD(0x160)
6438  
6439 struct dprc_cmd_open {
6440 __le32 container_id;
6441 @@ -199,9 +189,6 @@ struct dprc_rsp_get_attributes {
6442 /* response word 1 */
6443 __le32 options;
6444 __le32 portal_id;
6445 - /* response word 2 */
6446 - __le16 version_major;
6447 - __le16 version_minor;
6448 };
6449  
6450 struct dprc_cmd_set_res_quota {
6451 @@ -367,11 +354,16 @@ struct dprc_cmd_get_obj_region {
6452  
6453 struct dprc_rsp_get_obj_region {
6454 /* response word 0 */
6455 - __le64 pad;
6456 + __le64 pad0;
6457 /* response word 1 */
6458 - __le64 base_addr;
6459 + __le32 base_addr;
6460 + __le32 pad1;
6461 /* response word 2 */
6462 __le32 size;
6463 + u8 type;
6464 + u8 pad2[3];
6465 + /* response word 3 */
6466 + __le32 flags;
6467 };
6468  
6469 struct dprc_cmd_set_obj_label {
6470 --- a/drivers/staging/fsl-mc/bus/dprc-driver.c
6471 +++ b/drivers/staging/fsl-mc/bus/dprc-driver.c
6472 @@ -1,7 +1,7 @@
6473 /*
6474 * Freescale data path resource container (DPRC) driver
6475 *
6476 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
6477 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
6478 * Author: German Rivera <German.Rivera@freescale.com>
6479 *
6480 * This file is licensed under the terms of the GNU General Public
6481 @@ -160,6 +160,8 @@ static void check_plugged_state_change(s
6482 * dprc_add_new_devices - Adds devices to the logical bus for a DPRC
6483 *
6484 * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object
6485 + * @driver_override: driver override to apply to new objects found in the
6486 + * DPRC, or NULL, if none.
6487 * @obj_desc_array: array of device descriptors for child devices currently
6488 * present in the physical DPRC.
6489 * @num_child_objects_in_mc: number of entries in obj_desc_array
6490 @@ -169,6 +171,7 @@ static void check_plugged_state_change(s
6491 * in the physical DPRC.
6492 */
6493 static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev,
6494 + const char *driver_override,
6495 struct dprc_obj_desc *obj_desc_array,
6496 int num_child_objects_in_mc)
6497 {
6498 @@ -188,11 +191,12 @@ static void dprc_add_new_devices(struct
6499 child_dev = fsl_mc_device_lookup(obj_desc, mc_bus_dev);
6500 if (child_dev) {
6501 check_plugged_state_change(child_dev, obj_desc);
6502 + put_device(&child_dev->dev);
6503 continue;
6504 }
6505  
6506 error = fsl_mc_device_add(obj_desc, NULL, &mc_bus_dev->dev,
6507 - &child_dev);
6508 + driver_override, &child_dev);
6509 if (error < 0)
6510 continue;
6511 }
6512 @@ -202,6 +206,8 @@ static void dprc_add_new_devices(struct
6513 * dprc_scan_objects - Discover objects in a DPRC
6514 *
6515 * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object
6516 + * @driver_override: driver override to apply to new objects found in the
6517 + * DPRC, or NULL, if none.
6518 * @total_irq_count: total number of IRQs needed by objects in the DPRC.
6519 *
6520 * Detects objects added and removed from a DPRC and synchronizes the
6521 @@ -217,6 +223,7 @@ static void dprc_add_new_devices(struct
6522 * of the device drivers for the non-allocatable devices.
6523 */
6524 int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
6525 + const char *driver_override,
6526 unsigned int *total_irq_count)
6527 {
6528 int num_child_objects;
6529 @@ -297,7 +304,7 @@ int dprc_scan_objects(struct fsl_mc_devi
6530 dprc_remove_devices(mc_bus_dev, child_obj_desc_array,
6531 num_child_objects);
6532  
6533 - dprc_add_new_devices(mc_bus_dev, child_obj_desc_array,
6534 + dprc_add_new_devices(mc_bus_dev, driver_override, child_obj_desc_array,
6535 num_child_objects);
6536  
6537 if (child_obj_desc_array)
6538 @@ -328,7 +335,7 @@ int dprc_scan_container(struct fsl_mc_de
6539 * Discover objects in the DPRC:
6540 */
6541 mutex_lock(&mc_bus->scan_mutex);
6542 - error = dprc_scan_objects(mc_bus_dev, &irq_count);
6543 + error = dprc_scan_objects(mc_bus_dev, NULL, &irq_count);
6544 mutex_unlock(&mc_bus->scan_mutex);
6545 if (error < 0)
6546 goto error;
6547 @@ -415,7 +422,7 @@ static irqreturn_t dprc_irq0_handler_thr
6548 DPRC_IRQ_EVENT_OBJ_CREATED)) {
6549 unsigned int irq_count;
6550  
6551 - error = dprc_scan_objects(mc_dev, &irq_count);
6552 + error = dprc_scan_objects(mc_dev, NULL, &irq_count);
6553 if (error < 0) {
6554 /*
6555 * If the error is -ENXIO, we ignore it, as it indicates
6556 @@ -505,7 +512,7 @@ static int register_dprc_irq_handler(str
6557 dprc_irq0_handler,
6558 dprc_irq0_handler_thread,
6559 IRQF_NO_SUSPEND | IRQF_ONESHOT,
6560 - "FSL MC DPRC irq0",
6561 + dev_name(&mc_dev->dev),
6562 &mc_dev->dev);
6563 if (error < 0) {
6564 dev_err(&mc_dev->dev,
6565 @@ -597,6 +604,7 @@ static int dprc_probe(struct fsl_mc_devi
6566 struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev);
6567 bool mc_io_created = false;
6568 bool msi_domain_set = false;
6569 + u16 major_ver, minor_ver;
6570  
6571 if (WARN_ON(strcmp(mc_dev->obj_desc.type, "dprc") != 0))
6572 return -EINVAL;
6573 @@ -669,13 +677,21 @@ static int dprc_probe(struct fsl_mc_devi
6574 goto error_cleanup_open;
6575 }
6576  
6577 - if (mc_bus->dprc_attr.version.major < DPRC_MIN_VER_MAJOR ||
6578 - (mc_bus->dprc_attr.version.major == DPRC_MIN_VER_MAJOR &&
6579 - mc_bus->dprc_attr.version.minor < DPRC_MIN_VER_MINOR)) {
6580 + error = dprc_get_api_version(mc_dev->mc_io, 0,
6581 + &major_ver,
6582 + &minor_ver);
6583 + if (error < 0) {
6584 + dev_err(&mc_dev->dev, "dprc_get_api_version() failed: %d\n",
6585 + error);
6586 + goto error_cleanup_open;
6587 + }
6588 +
6589 + if (major_ver < DPRC_MIN_VER_MAJOR ||
6590 + (major_ver == DPRC_MIN_VER_MAJOR &&
6591 + minor_ver < DPRC_MIN_VER_MINOR)) {
6592 dev_err(&mc_dev->dev,
6593 "ERROR: DPRC version %d.%d not supported\n",
6594 - mc_bus->dprc_attr.version.major,
6595 - mc_bus->dprc_attr.version.minor);
6596 + major_ver, minor_ver);
6597 error = -ENOTSUPP;
6598 goto error_cleanup_open;
6599 }
6600 --- a/drivers/staging/fsl-mc/bus/dprc.c
6601 +++ b/drivers/staging/fsl-mc/bus/dprc.c
6602 @@ -1,4 +1,5 @@
6603 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
6604 +/*
6605 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6606 *
6607 * Redistribution and use in source and binary forms, with or without
6608 * modification, are permitted provided that the following conditions are met:
6609 @@ -11,7 +12,6 @@
6610 * names of any contributors may be used to endorse or promote products
6611 * derived from this software without specific prior written permission.
6612 *
6613 - *
6614 * ALTERNATIVELY, this software may be distributed under the terms of the
6615 * GNU General Public License ("GPL") as published by the Free Software
6616 * Foundation, either version 2 of that License or (at your option) any
6617 @@ -100,93 +100,6 @@ int dprc_close(struct fsl_mc_io *mc_io,
6618 EXPORT_SYMBOL(dprc_close);
6619  
6620 /**
6621 - * dprc_create_container() - Create child container
6622 - * @mc_io: Pointer to MC portal's I/O object
6623 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6624 - * @token: Token of DPRC object
6625 - * @cfg: Child container configuration
6626 - * @child_container_id: Returned child container ID
6627 - * @child_portal_offset: Returned child portal offset from MC portal base
6628 - *
6629 - * Return: '0' on Success; Error code otherwise.
6630 - */
6631 -int dprc_create_container(struct fsl_mc_io *mc_io,
6632 - u32 cmd_flags,
6633 - u16 token,
6634 - struct dprc_cfg *cfg,
6635 - int *child_container_id,
6636 - u64 *child_portal_offset)
6637 -{
6638 - struct mc_command cmd = { 0 };
6639 - struct dprc_cmd_create_container *cmd_params;
6640 - struct dprc_rsp_create_container *rsp_params;
6641 - int err;
6642 -
6643 - /* prepare command */
6644 - cmd_params = (struct dprc_cmd_create_container *)cmd.params;
6645 - cmd_params->options = cpu_to_le32(cfg->options);
6646 - cmd_params->icid = cpu_to_le16(cfg->icid);
6647 - cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
6648 - strncpy(cmd_params->label, cfg->label, 16);
6649 - cmd_params->label[15] = '\0';
6650 -
6651 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT,
6652 - cmd_flags, token);
6653 -
6654 - /* send command to mc*/
6655 - err = mc_send_command(mc_io, &cmd);
6656 - if (err)
6657 - return err;
6658 -
6659 - /* retrieve response parameters */
6660 - rsp_params = (struct dprc_rsp_create_container *)cmd.params;
6661 - *child_container_id = le32_to_cpu(rsp_params->child_container_id);
6662 - *child_portal_offset = le64_to_cpu(rsp_params->child_portal_addr);
6663 -
6664 - return 0;
6665 -}
6666 -
6667 -/**
6668 - * dprc_destroy_container() - Destroy child container.
6669 - * @mc_io: Pointer to MC portal's I/O object
6670 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6671 - * @token: Token of DPRC object
6672 - * @child_container_id: ID of the container to destroy
6673 - *
6674 - * This function terminates the child container, so following this call the
6675 - * child container ID becomes invalid.
6676 - *
6677 - * Notes:
6678 - * - All resources and objects of the destroyed container are returned to the
6679 - * parent container or destroyed if were created be the destroyed container.
6680 - * - This function destroy all the child containers of the specified
6681 - * container prior to destroying the container itself.
6682 - *
6683 - * warning: Only the parent container is allowed to destroy a child policy
6684 - * Container 0 can't be destroyed
6685 - *
6686 - * Return: '0' on Success; Error code otherwise.
6687 - *
6688 - */
6689 -int dprc_destroy_container(struct fsl_mc_io *mc_io,
6690 - u32 cmd_flags,
6691 - u16 token,
6692 - int child_container_id)
6693 -{
6694 - struct mc_command cmd = { 0 };
6695 - struct dprc_cmd_destroy_container *cmd_params;
6696 -
6697 - /* prepare command */
6698 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT,
6699 - cmd_flags, token);
6700 - cmd_params = (struct dprc_cmd_destroy_container *)cmd.params;
6701 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6702 -
6703 - /* send command to mc*/
6704 - return mc_send_command(mc_io, &cmd);
6705 -}
6706 -
6707 -/**
6708 * dprc_reset_container - Reset child container.
6709 * @mc_io: Pointer to MC portal's I/O object
6710 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6711 @@ -565,279 +478,6 @@ int dprc_get_attributes(struct fsl_mc_io
6712 attr->icid = le16_to_cpu(rsp_params->icid);
6713 attr->options = le32_to_cpu(rsp_params->options);
6714 attr->portal_id = le32_to_cpu(rsp_params->portal_id);
6715 - attr->version.major = le16_to_cpu(rsp_params->version_major);
6716 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
6717 -
6718 - return 0;
6719 -}
6720 -
6721 -/**
6722 - * dprc_set_res_quota() - Set allocation policy for a specific resource/object
6723 - * type in a child container
6724 - * @mc_io: Pointer to MC portal's I/O object
6725 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6726 - * @token: Token of DPRC object
6727 - * @child_container_id: ID of the child container
6728 - * @type: Resource/object type
6729 - * @quota: Sets the maximum number of resources of the selected type
6730 - * that the child container is allowed to allocate from its parent;
6731 - * when quota is set to -1, the policy is the same as container's
6732 - * general policy.
6733 - *
6734 - * Allocation policy determines whether or not a container may allocate
6735 - * resources from its parent. Each container has a 'global' allocation policy
6736 - * that is set when the container is created.
6737 - *
6738 - * This function sets allocation policy for a specific resource type.
6739 - * The default policy for all resource types matches the container's 'global'
6740 - * allocation policy.
6741 - *
6742 - * Return: '0' on Success; Error code otherwise.
6743 - *
6744 - * @warning Only the parent container is allowed to change a child policy.
6745 - */
6746 -int dprc_set_res_quota(struct fsl_mc_io *mc_io,
6747 - u32 cmd_flags,
6748 - u16 token,
6749 - int child_container_id,
6750 - char *type,
6751 - u16 quota)
6752 -{
6753 - struct mc_command cmd = { 0 };
6754 - struct dprc_cmd_set_res_quota *cmd_params;
6755 -
6756 - /* prepare command */
6757 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_RES_QUOTA,
6758 - cmd_flags, token);
6759 - cmd_params = (struct dprc_cmd_set_res_quota *)cmd.params;
6760 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6761 - cmd_params->quota = cpu_to_le16(quota);
6762 - strncpy(cmd_params->type, type, 16);
6763 - cmd_params->type[15] = '\0';
6764 -
6765 - /* send command to mc*/
6766 - return mc_send_command(mc_io, &cmd);
6767 -}
6768 -
6769 -/**
6770 - * dprc_get_res_quota() - Gets the allocation policy of a specific
6771 - * resource/object type in a child container
6772 - * @mc_io: Pointer to MC portal's I/O object
6773 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6774 - * @token: Token of DPRC object
6775 - * @child_container_id; ID of the child container
6776 - * @type: resource/object type
6777 - * @quota: Returnes the maximum number of resources of the selected type
6778 - * that the child container is allowed to allocate from the parent;
6779 - * when quota is set to -1, the policy is the same as container's
6780 - * general policy.
6781 - *
6782 - * Return: '0' on Success; Error code otherwise.
6783 - */
6784 -int dprc_get_res_quota(struct fsl_mc_io *mc_io,
6785 - u32 cmd_flags,
6786 - u16 token,
6787 - int child_container_id,
6788 - char *type,
6789 - u16 *quota)
6790 -{
6791 - struct mc_command cmd = { 0 };
6792 - struct dprc_cmd_get_res_quota *cmd_params;
6793 - struct dprc_rsp_get_res_quota *rsp_params;
6794 - int err;
6795 -
6796 - /* prepare command */
6797 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_QUOTA,
6798 - cmd_flags, token);
6799 - cmd_params = (struct dprc_cmd_get_res_quota *)cmd.params;
6800 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6801 - strncpy(cmd_params->type, type, 16);
6802 - cmd_params->type[15] = '\0';
6803 -
6804 - /* send command to mc*/
6805 - err = mc_send_command(mc_io, &cmd);
6806 - if (err)
6807 - return err;
6808 -
6809 - /* retrieve response parameters */
6810 - rsp_params = (struct dprc_rsp_get_res_quota *)cmd.params;
6811 - *quota = le16_to_cpu(rsp_params->quota);
6812 -
6813 - return 0;
6814 -}
6815 -
6816 -/**
6817 - * dprc_assign() - Assigns objects or resource to a child container.
6818 - * @mc_io: Pointer to MC portal's I/O object
6819 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6820 - * @token: Token of DPRC object
6821 - * @container_id: ID of the child container
6822 - * @res_req: Describes the type and amount of resources to
6823 - * assign to the given container
6824 - *
6825 - * Assignment is usually done by a parent (this DPRC) to one of its child
6826 - * containers.
6827 - *
6828 - * According to the DPRC allocation policy, the assigned resources may be taken
6829 - * (allocated) from the container's ancestors, if not enough resources are
6830 - * available in the container itself.
6831 - *
6832 - * The type of assignment depends on the dprc_res_req options, as follows:
6833 - * - DPRC_RES_REQ_OPT_EXPLICIT: indicates that assigned resources should have
6834 - * the explicit base ID specified at the id_base_align field of res_req.
6835 - * - DPRC_RES_REQ_OPT_ALIGNED: indicates that the assigned resources should be
6836 - * aligned to the value given at id_base_align field of res_req.
6837 - * - DPRC_RES_REQ_OPT_PLUGGED: Relevant only for object assignment,
6838 - * and indicates that the object must be set to the plugged state.
6839 - *
6840 - * A container may use this function with its own ID in order to change a
6841 - * object state to plugged or unplugged.
6842 - *
6843 - * If IRQ information has been set in the child DPRC, it will signal an
6844 - * interrupt following every change in its object assignment.
6845 - *
6846 - * Return: '0' on Success; Error code otherwise.
6847 - */
6848 -int dprc_assign(struct fsl_mc_io *mc_io,
6849 - u32 cmd_flags,
6850 - u16 token,
6851 - int container_id,
6852 - struct dprc_res_req *res_req)
6853 -{
6854 - struct mc_command cmd = { 0 };
6855 - struct dprc_cmd_assign *cmd_params;
6856 -
6857 - /* prepare command */
6858 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_ASSIGN,
6859 - cmd_flags, token);
6860 - cmd_params = (struct dprc_cmd_assign *)cmd.params;
6861 - cmd_params->container_id = cpu_to_le32(container_id);
6862 - cmd_params->options = cpu_to_le32(res_req->options);
6863 - cmd_params->num = cpu_to_le32(res_req->num);
6864 - cmd_params->id_base_align = cpu_to_le32(res_req->id_base_align);
6865 - strncpy(cmd_params->type, res_req->type, 16);
6866 - cmd_params->type[15] = '\0';
6867 -
6868 - /* send command to mc*/
6869 - return mc_send_command(mc_io, &cmd);
6870 -}
6871 -
6872 -/**
6873 - * dprc_unassign() - Un-assigns objects or resources from a child container
6874 - * and moves them into this (parent) DPRC.
6875 - * @mc_io: Pointer to MC portal's I/O object
6876 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6877 - * @token: Token of DPRC object
6878 - * @child_container_id: ID of the child container
6879 - * @res_req: Describes the type and amount of resources to un-assign from
6880 - * the child container
6881 - *
6882 - * Un-assignment of objects can succeed only if the object is not in the
6883 - * plugged or opened state.
6884 - *
6885 - * Return: '0' on Success; Error code otherwise.
6886 - */
6887 -int dprc_unassign(struct fsl_mc_io *mc_io,
6888 - u32 cmd_flags,
6889 - u16 token,
6890 - int child_container_id,
6891 - struct dprc_res_req *res_req)
6892 -{
6893 - struct mc_command cmd = { 0 };
6894 - struct dprc_cmd_unassign *cmd_params;
6895 -
6896 - /* prepare command */
6897 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_UNASSIGN,
6898 - cmd_flags,
6899 - token);
6900 - cmd_params = (struct dprc_cmd_unassign *)cmd.params;
6901 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6902 - cmd_params->options = cpu_to_le32(res_req->options);
6903 - cmd_params->num = cpu_to_le32(res_req->num);
6904 - cmd_params->id_base_align = cpu_to_le32(res_req->id_base_align);
6905 - strncpy(cmd_params->type, res_req->type, 16);
6906 - cmd_params->type[15] = '\0';
6907 -
6908 - /* send command to mc*/
6909 - return mc_send_command(mc_io, &cmd);
6910 -}
6911 -
6912 -/**
6913 - * dprc_get_pool_count() - Get the number of dprc's pools
6914 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6915 - * @mc_io: Pointer to MC portal's I/O object
6916 - * @token: Token of DPRC object
6917 - * @pool_count: Returned number of resource pools in the dprc
6918 - *
6919 - * Return: '0' on Success; Error code otherwise.
6920 - */
6921 -int dprc_get_pool_count(struct fsl_mc_io *mc_io,
6922 - u32 cmd_flags,
6923 - u16 token,
6924 - int *pool_count)
6925 -{
6926 - struct mc_command cmd = { 0 };
6927 - struct dprc_rsp_get_pool_count *rsp_params;
6928 - int err;
6929 -
6930 - /* prepare command */
6931 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL_COUNT,
6932 - cmd_flags, token);
6933 -
6934 - /* send command to mc*/
6935 - err = mc_send_command(mc_io, &cmd);
6936 - if (err)
6937 - return err;
6938 -
6939 - /* retrieve response parameters */
6940 - rsp_params = (struct dprc_rsp_get_pool_count *)cmd.params;
6941 - *pool_count = le32_to_cpu(rsp_params->pool_count);
6942 -
6943 - return 0;
6944 -}
6945 -
6946 -/**
6947 - * dprc_get_pool() - Get the type (string) of a certain dprc's pool
6948 - * @mc_io: Pointer to MC portal's I/O object
6949 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6950 - * @token: Token of DPRC object
6951 - * @pool_index; Index of the pool to be queried (< pool_count)
6952 - * @type: The type of the pool
6953 - *
6954 - * The pool types retrieved one by one by incrementing
6955 - * pool_index up to (not including) the value of pool_count returned
6956 - * from dprc_get_pool_count(). dprc_get_pool_count() must
6957 - * be called prior to dprc_get_pool().
6958 - *
6959 - * Return: '0' on Success; Error code otherwise.
6960 - */
6961 -int dprc_get_pool(struct fsl_mc_io *mc_io,
6962 - u32 cmd_flags,
6963 - u16 token,
6964 - int pool_index,
6965 - char *type)
6966 -{
6967 - struct mc_command cmd = { 0 };
6968 - struct dprc_cmd_get_pool *cmd_params;
6969 - struct dprc_rsp_get_pool *rsp_params;
6970 - int err;
6971 -
6972 - /* prepare command */
6973 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL,
6974 - cmd_flags,
6975 - token);
6976 - cmd_params = (struct dprc_cmd_get_pool *)cmd.params;
6977 - cmd_params->pool_index = cpu_to_le32(pool_index);
6978 -
6979 - /* send command to mc*/
6980 - err = mc_send_command(mc_io, &cmd);
6981 - if (err)
6982 - return err;
6983 -
6984 - /* retrieve response parameters */
6985 - rsp_params = (struct dprc_rsp_get_pool *)cmd.params;
6986 - strncpy(type, rsp_params->type, 16);
6987 - type[15] = '\0';
6988  
6989 return 0;
6990 }
6991 @@ -934,64 +574,6 @@ int dprc_get_obj(struct fsl_mc_io *mc_io
6992 EXPORT_SYMBOL(dprc_get_obj);
6993  
6994 /**
6995 - * dprc_get_obj_desc() - Get object descriptor.
6996 - *
6997 - * @mc_io: Pointer to MC portal's I/O object
6998 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6999 - * @token: Token of DPRC object
7000 - * @obj_type: The type of the object to get its descriptor.
7001 - * @obj_id: The id of the object to get its descriptor
7002 - * @obj_desc: The returned descriptor to fill and return to the user
7003 - *
7004 - * Return: '0' on Success; Error code otherwise.
7005 - *
7006 - */
7007 -int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
7008 - u32 cmd_flags,
7009 - u16 token,
7010 - char *obj_type,
7011 - int obj_id,
7012 - struct dprc_obj_desc *obj_desc)
7013 -{
7014 - struct mc_command cmd = { 0 };
7015 - struct dprc_cmd_get_obj_desc *cmd_params;
7016 - struct dprc_rsp_get_obj_desc *rsp_params;
7017 - int err;
7018 -
7019 - /* prepare command */
7020 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_DESC,
7021 - cmd_flags,
7022 - token);
7023 - cmd_params = (struct dprc_cmd_get_obj_desc *)cmd.params;
7024 - cmd_params->obj_id = cpu_to_le32(obj_id);
7025 - strncpy(cmd_params->type, obj_type, 16);
7026 - cmd_params->type[15] = '\0';
7027 -
7028 - /* send command to mc*/
7029 - err = mc_send_command(mc_io, &cmd);
7030 - if (err)
7031 - return err;
7032 -
7033 - /* retrieve response parameters */
7034 - rsp_params = (struct dprc_rsp_get_obj_desc *)cmd.params;
7035 - obj_desc->id = le32_to_cpu(rsp_params->id);
7036 - obj_desc->vendor = le16_to_cpu(rsp_params->vendor);
7037 - obj_desc->irq_count = rsp_params->irq_count;
7038 - obj_desc->region_count = rsp_params->region_count;
7039 - obj_desc->state = le32_to_cpu(rsp_params->state);
7040 - obj_desc->ver_major = le16_to_cpu(rsp_params->version_major);
7041 - obj_desc->ver_minor = le16_to_cpu(rsp_params->version_minor);
7042 - obj_desc->flags = le16_to_cpu(rsp_params->flags);
7043 - strncpy(obj_desc->type, rsp_params->type, 16);
7044 - obj_desc->type[15] = '\0';
7045 - strncpy(obj_desc->label, rsp_params->label, 16);
7046 - obj_desc->label[15] = '\0';
7047 -
7048 - return 0;
7049 -}
7050 -EXPORT_SYMBOL(dprc_get_obj_desc);
7051 -
7052 -/**
7053 * dprc_set_obj_irq() - Set IRQ information for object to trigger an interrupt.
7054 * @mc_io: Pointer to MC portal's I/O object
7055 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7056 @@ -1130,52 +712,6 @@ int dprc_get_res_count(struct fsl_mc_io
7057 EXPORT_SYMBOL(dprc_get_res_count);
7058  
7059 /**
7060 - * dprc_get_res_ids() - Obtains IDs of free resources in the container
7061 - * @mc_io: Pointer to MC portal's I/O object
7062 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7063 - * @token: Token of DPRC object
7064 - * @type: pool type
7065 - * @range_desc: range descriptor
7066 - *
7067 - * Return: '0' on Success; Error code otherwise.
7068 - */
7069 -int dprc_get_res_ids(struct fsl_mc_io *mc_io,
7070 - u32 cmd_flags,
7071 - u16 token,
7072 - char *type,
7073 - struct dprc_res_ids_range_desc *range_desc)
7074 -{
7075 - struct mc_command cmd = { 0 };
7076 - struct dprc_cmd_get_res_ids *cmd_params;
7077 - struct dprc_rsp_get_res_ids *rsp_params;
7078 - int err;
7079 -
7080 - /* prepare command */
7081 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS,
7082 - cmd_flags, token);
7083 - cmd_params = (struct dprc_cmd_get_res_ids *)cmd.params;
7084 - cmd_params->iter_status = range_desc->iter_status;
7085 - cmd_params->base_id = cpu_to_le32(range_desc->base_id);
7086 - cmd_params->last_id = cpu_to_le32(range_desc->last_id);
7087 - strncpy(cmd_params->type, type, 16);
7088 - cmd_params->type[15] = '\0';
7089 -
7090 - /* send command to mc*/
7091 - err = mc_send_command(mc_io, &cmd);
7092 - if (err)
7093 - return err;
7094 -
7095 - /* retrieve response parameters */
7096 - rsp_params = (struct dprc_rsp_get_res_ids *)cmd.params;
7097 - range_desc->iter_status = rsp_params->iter_status;
7098 - range_desc->base_id = le32_to_cpu(rsp_params->base_id);
7099 - range_desc->last_id = le32_to_cpu(rsp_params->last_id);
7100 -
7101 - return 0;
7102 -}
7103 -EXPORT_SYMBOL(dprc_get_res_ids);
7104 -
7105 -/**
7106 * dprc_get_obj_region() - Get region information for a specified object.
7107 * @mc_io: Pointer to MC portal's I/O object
7108 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7109 @@ -1216,160 +752,66 @@ int dprc_get_obj_region(struct fsl_mc_io
7110  
7111 /* retrieve response parameters */
7112 rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params;
7113 - region_desc->base_offset = le64_to_cpu(rsp_params->base_addr);
7114 + region_desc->base_offset = le32_to_cpu(rsp_params->base_addr);
7115 region_desc->size = le32_to_cpu(rsp_params->size);
7116 + region_desc->type = rsp_params->type;
7117 + region_desc->flags = le32_to_cpu(rsp_params->flags);
7118  
7119 return 0;
7120 }
7121 EXPORT_SYMBOL(dprc_get_obj_region);
7122  
7123 /**
7124 - * dprc_set_obj_label() - Set object label.
7125 - * @mc_io: Pointer to MC portal's I/O object
7126 + * dprc_get_api_version - Get Data Path Resource Container API version
7127 + * @mc_io: Pointer to Mc portal's I/O object
7128 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7129 - * @token: Token of DPRC object
7130 - * @obj_type: Object's type
7131 - * @obj_id: Object's ID
7132 - * @label: The required label. The maximum length is 16 chars.
7133 + * @major_ver: Major version of Data Path Resource Container API
7134 + * @minor_ver: Minor version of Data Path Resource Container API
7135 *
7136 * Return: '0' on Success; Error code otherwise.
7137 */
7138 -int dprc_set_obj_label(struct fsl_mc_io *mc_io,
7139 - u32 cmd_flags,
7140 - u16 token,
7141 - char *obj_type,
7142 - int obj_id,
7143 - char *label)
7144 +int dprc_get_api_version(struct fsl_mc_io *mc_io,
7145 + u32 cmd_flags,
7146 + u16 *major_ver,
7147 + u16 *minor_ver)
7148 {
7149 struct mc_command cmd = { 0 };
7150 - struct dprc_cmd_set_obj_label *cmd_params;
7151 + int err;
7152  
7153 /* prepare command */
7154 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_LABEL,
7155 - cmd_flags,
7156 - token);
7157 - cmd_params = (struct dprc_cmd_set_obj_label *)cmd.params;
7158 - cmd_params->obj_id = cpu_to_le32(obj_id);
7159 - strncpy(cmd_params->label, label, 16);
7160 - cmd_params->label[15] = '\0';
7161 - strncpy(cmd_params->obj_type, obj_type, 16);
7162 - cmd_params->obj_type[15] = '\0';
7163 + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_API_VERSION,
7164 + cmd_flags, 0);
7165  
7166 - /* send command to mc*/
7167 - return mc_send_command(mc_io, &cmd);
7168 -}
7169 -EXPORT_SYMBOL(dprc_set_obj_label);
7170 -
7171 -/**
7172 - * dprc_connect() - Connect two endpoints to create a network link between them
7173 - * @mc_io: Pointer to MC portal's I/O object
7174 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7175 - * @token: Token of DPRC object
7176 - * @endpoint1: Endpoint 1 configuration parameters
7177 - * @endpoint2: Endpoint 2 configuration parameters
7178 - * @cfg: Connection configuration. The connection configuration is ignored for
7179 - * connections made to DPMAC objects, where rate is retrieved from the
7180 - * MAC configuration.
7181 - *
7182 - * Return: '0' on Success; Error code otherwise.
7183 - */
7184 -int dprc_connect(struct fsl_mc_io *mc_io,
7185 - u32 cmd_flags,
7186 - u16 token,
7187 - const struct dprc_endpoint *endpoint1,
7188 - const struct dprc_endpoint *endpoint2,
7189 - const struct dprc_connection_cfg *cfg)
7190 -{
7191 - struct mc_command cmd = { 0 };
7192 - struct dprc_cmd_connect *cmd_params;
7193 + /* send command to mc */
7194 + err = mc_send_command(mc_io, &cmd);
7195 + if (err)
7196 + return err;
7197  
7198 - /* prepare command */
7199 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT,
7200 - cmd_flags,
7201 - token);
7202 - cmd_params = (struct dprc_cmd_connect *)cmd.params;
7203 - cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
7204 - cmd_params->ep1_interface_id = cpu_to_le32(endpoint1->if_id);
7205 - cmd_params->ep2_id = cpu_to_le32(endpoint2->id);
7206 - cmd_params->ep2_interface_id = cpu_to_le32(endpoint2->if_id);
7207 - strncpy(cmd_params->ep1_type, endpoint1->type, 16);
7208 - cmd_params->ep1_type[15] = '\0';
7209 - cmd_params->max_rate = cpu_to_le32(cfg->max_rate);
7210 - cmd_params->committed_rate = cpu_to_le32(cfg->committed_rate);
7211 - strncpy(cmd_params->ep2_type, endpoint2->type, 16);
7212 - cmd_params->ep2_type[15] = '\0';
7213 + /* retrieve response parameters */
7214 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
7215  
7216 - /* send command to mc*/
7217 - return mc_send_command(mc_io, &cmd);
7218 + return 0;
7219 }
7220  
7221 /**
7222 - * dprc_disconnect() - Disconnect one endpoint to remove its network connection
7223 - * @mc_io: Pointer to MC portal's I/O object
7224 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7225 - * @token: Token of DPRC object
7226 - * @endpoint: Endpoint configuration parameters
7227 + * dprc_get_container_id - Get container ID associated with a given portal.
7228 + * @mc_io: Pointer to Mc portal's I/O object
7229 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7230 + * @container_id: Requested container id
7231 *
7232 * Return: '0' on Success; Error code otherwise.
7233 */
7234 -int dprc_disconnect(struct fsl_mc_io *mc_io,
7235 - u32 cmd_flags,
7236 - u16 token,
7237 - const struct dprc_endpoint *endpoint)
7238 -{
7239 - struct mc_command cmd = { 0 };
7240 - struct dprc_cmd_disconnect *cmd_params;
7241 -
7242 - /* prepare command */
7243 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT,
7244 - cmd_flags,
7245 - token);
7246 - cmd_params = (struct dprc_cmd_disconnect *)cmd.params;
7247 - cmd_params->id = cpu_to_le32(endpoint->id);
7248 - cmd_params->interface_id = cpu_to_le32(endpoint->if_id);
7249 - strncpy(cmd_params->type, endpoint->type, 16);
7250 - cmd_params->type[15] = '\0';
7251 -
7252 - /* send command to mc*/
7253 - return mc_send_command(mc_io, &cmd);
7254 -}
7255 -
7256 -/**
7257 - * dprc_get_connection() - Get connected endpoint and link status if connection
7258 - * exists.
7259 - * @mc_io: Pointer to MC portal's I/O object
7260 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7261 - * @token: Token of DPRC object
7262 - * @endpoint1: Endpoint 1 configuration parameters
7263 - * @endpoint2: Returned endpoint 2 configuration parameters
7264 - * @state: Returned link state:
7265 - * 1 - link is up;
7266 - * 0 - link is down;
7267 - * -1 - no connection (endpoint2 information is irrelevant)
7268 - *
7269 - * Return: '0' on Success; -ENAVAIL if connection does not exist.
7270 - */
7271 -int dprc_get_connection(struct fsl_mc_io *mc_io,
7272 - u32 cmd_flags,
7273 - u16 token,
7274 - const struct dprc_endpoint *endpoint1,
7275 - struct dprc_endpoint *endpoint2,
7276 - int *state)
7277 +int dprc_get_container_id(struct fsl_mc_io *mc_io,
7278 + u32 cmd_flags,
7279 + int *container_id)
7280 {
7281 struct mc_command cmd = { 0 };
7282 - struct dprc_cmd_get_connection *cmd_params;
7283 - struct dprc_rsp_get_connection *rsp_params;
7284 int err;
7285  
7286 /* prepare command */
7287 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION,
7288 + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID,
7289 cmd_flags,
7290 - token);
7291 - cmd_params = (struct dprc_cmd_get_connection *)cmd.params;
7292 - cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
7293 - cmd_params->ep1_interface_id = cpu_to_le32(endpoint1->if_id);
7294 - strncpy(cmd_params->ep1_type, endpoint1->type, 16);
7295 - cmd_params->ep1_type[15] = '\0';
7296 + 0);
7297  
7298 /* send command to mc*/
7299 err = mc_send_command(mc_io, &cmd);
7300 @@ -1377,12 +819,7 @@ int dprc_get_connection(struct fsl_mc_io
7301 return err;
7302  
7303 /* retrieve response parameters */
7304 - rsp_params = (struct dprc_rsp_get_connection *)cmd.params;
7305 - endpoint2->id = le32_to_cpu(rsp_params->ep2_id);
7306 - endpoint2->if_id = le32_to_cpu(rsp_params->ep2_interface_id);
7307 - strncpy(endpoint2->type, rsp_params->ep2_type, 16);
7308 - endpoint2->type[15] = '\0';
7309 - *state = le32_to_cpu(rsp_params->state);
7310 + *container_id = (int)mc_cmd_read_object_id(&cmd);
7311  
7312 return 0;
7313 }
7314 --- a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
7315 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
7316 @@ -1,7 +1,7 @@
7317 /*
7318 - * Freescale MC object device allocator driver
7319 + * fsl-mc object allocator driver
7320 *
7321 - * Copyright (C) 2013 Freescale Semiconductor, Inc.
7322 + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
7323 *
7324 * This file is licensed under the terms of the GNU General Public
7325 * License version 2. This program is licensed "as is" without any
7326 @@ -12,9 +12,9 @@
7327 #include <linux/msi.h>
7328 #include "../include/mc-bus.h"
7329 #include "../include/mc-sys.h"
7330 -#include "../include/dpbp-cmd.h"
7331 -#include "../include/dpcon-cmd.h"
7332  
7333 +#include "dpbp-cmd.h"
7334 +#include "dpcon-cmd.h"
7335 #include "fsl-mc-private.h"
7336  
7337 #define FSL_MC_IS_ALLOCATABLE(_obj_type) \
7338 @@ -23,15 +23,12 @@
7339 strcmp(_obj_type, "dpcon") == 0)
7340  
7341 /**
7342 - * fsl_mc_resource_pool_add_device - add allocatable device to a resource
7343 - * pool of a given MC bus
7344 + * fsl_mc_resource_pool_add_device - add allocatable object to a resource
7345 + * pool of a given fsl-mc bus
7346 *
7347 - * @mc_bus: pointer to the MC bus
7348 - * @pool_type: MC bus pool type
7349 - * @mc_dev: Pointer to allocatable MC object device
7350 - *
7351 - * It adds an allocatable MC object device to a container's resource pool of
7352 - * the given resource type
7353 + * @mc_bus: pointer to the fsl-mc bus
7354 + * @pool_type: pool type
7355 + * @mc_dev: pointer to allocatable fsl-mc device
7356 */
7357 static int __must_check fsl_mc_resource_pool_add_device(struct fsl_mc_bus
7358 *mc_bus,
7359 @@ -95,10 +92,10 @@ out:
7360 * fsl_mc_resource_pool_remove_device - remove an allocatable device from a
7361 * resource pool
7362 *
7363 - * @mc_dev: Pointer to allocatable MC object device
7364 + * @mc_dev: pointer to allocatable fsl-mc device
7365 *
7366 - * It permanently removes an allocatable MC object device from the resource
7367 - * pool, the device is currently in, as long as it is in the pool's free list.
7368 + * It permanently removes an allocatable fsl-mc device from the resource
7369 + * pool. It's an error if the device is in use.
7370 */
7371 static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device
7372 *mc_dev)
7373 @@ -255,17 +252,18 @@ out_unlock:
7374 EXPORT_SYMBOL_GPL(fsl_mc_resource_free);
7375  
7376 /**
7377 - * fsl_mc_object_allocate - Allocates a MC object device of the given
7378 - * pool type from a given MC bus
7379 + * fsl_mc_object_allocate - Allocates an fsl-mc object of the given
7380 + * pool type from a given fsl-mc bus instance
7381 *
7382 - * @mc_dev: MC device for which the MC object device is to be allocated
7383 - * @pool_type: MC bus resource pool type
7384 - * @new_mc_dev: Pointer to area where the pointer to the allocated
7385 - * MC object device is to be returned
7386 + * @mc_dev: fsl-mc device which is used in conjunction with the
7387 + * allocated object
7388 + * @pool_type: pool type
7389 + * @new_mc_dev: pointer to area where the pointer to the allocated device
7390 + * is to be returned
7391 *
7392 - * This function allocates a MC object device from the device's parent DPRC,
7393 - * from the corresponding MC bus' pool of allocatable MC object devices of
7394 - * the given resource type. mc_dev cannot be a DPRC itself.
7395 + * Allocatable objects are always used in conjunction with some functional
7396 + * device. This function allocates an object of the specified type from
7397 + * the DPRC containing the functional device.
7398 *
7399 * NOTE: pool_type must be different from FSL_MC_POOL_MCP, since MC
7400 * portals are allocated using fsl_mc_portal_allocate(), instead of
7401 @@ -312,10 +310,9 @@ error:
7402 EXPORT_SYMBOL_GPL(fsl_mc_object_allocate);
7403  
7404 /**
7405 - * fsl_mc_object_free - Returns an allocatable MC object device to the
7406 - * corresponding resource pool of a given MC bus.
7407 - *
7408 - * @mc_adev: Pointer to the MC object device
7409 + * fsl_mc_object_free - Returns an fsl-mc object to the resource
7410 + * pool where it came from.
7411 + * @mc_adev: Pointer to the fsl-mc device
7412 */
7413 void fsl_mc_object_free(struct fsl_mc_device *mc_adev)
7414 {
7415 @@ -332,8 +329,14 @@ void fsl_mc_object_free(struct fsl_mc_de
7416 EXPORT_SYMBOL_GPL(fsl_mc_object_free);
7417  
7418 /*
7419 - * Initialize the interrupt pool associated with a MC bus.
7420 - * It allocates a block of IRQs from the GIC-ITS
7421 + * A DPRC and the devices in the DPRC all share the same GIC-ITS device
7422 + * ID. A block of IRQs is pre-allocated and maintained in a pool
7423 + * from which devices can allocate them when needed.
7424 + */
7425 +
7426 +/*
7427 + * Initialize the interrupt pool associated with an fsl-mc bus.
7428 + * It allocates a block of IRQs from the GIC-ITS.
7429 */
7430 int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus,
7431 unsigned int irq_count)
7432 @@ -395,7 +398,7 @@ cleanup_msi_irqs:
7433 EXPORT_SYMBOL_GPL(fsl_mc_populate_irq_pool);
7434  
7435 /**
7436 - * Teardown the interrupt pool associated with an MC bus.
7437 + * Teardown the interrupt pool associated with an fsl-mc bus.
7438 * It frees the IRQs that were allocated to the pool, back to the GIC-ITS.
7439 */
7440 void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus)
7441 @@ -422,11 +425,7 @@ void fsl_mc_cleanup_irq_pool(struct fsl_
7442 EXPORT_SYMBOL_GPL(fsl_mc_cleanup_irq_pool);
7443  
7444 /**
7445 - * It allocates the IRQs required by a given MC object device. The
7446 - * IRQs are allocated from the interrupt pool associated with the
7447 - * MC bus that contains the device, if the device is not a DPRC device.
7448 - * Otherwise, the IRQs are allocated from the interrupt pool associated
7449 - * with the MC bus that represents the DPRC device itself.
7450 + * Allocate the IRQs required by a given fsl-mc device.
7451 */
7452 int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev)
7453 {
7454 @@ -495,8 +494,7 @@ error_resource_alloc:
7455 EXPORT_SYMBOL_GPL(fsl_mc_allocate_irqs);
7456  
7457 /*
7458 - * It frees the IRQs that were allocated for a MC object device, by
7459 - * returning them to the corresponding interrupt pool.
7460 + * Frees the IRQs that were allocated for an fsl-mc device.
7461 */
7462 void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev)
7463 {
7464 @@ -605,7 +603,7 @@ static int fsl_mc_allocator_probe(struct
7465 return error;
7466  
7467 dev_dbg(&mc_dev->dev,
7468 - "Allocatable MC object device bound to fsl_mc_allocator driver");
7469 + "Allocatable fsl-mc device bound to fsl_mc_allocator driver");
7470 return 0;
7471 }
7472  
7473 @@ -627,7 +625,7 @@ static int fsl_mc_allocator_remove(struc
7474 }
7475  
7476 dev_dbg(&mc_dev->dev,
7477 - "Allocatable MC object device unbound from fsl_mc_allocator driver");
7478 + "Allocatable fsl-mc device unbound from fsl_mc_allocator driver");
7479 return 0;
7480 }
7481  
7482 --- a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
7483 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
7484 @@ -1,7 +1,7 @@
7485 /*
7486 * Freescale Management Complex (MC) bus driver
7487 *
7488 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
7489 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
7490 * Author: German Rivera <German.Rivera@freescale.com>
7491 *
7492 * This file is licensed under the terms of the GNU General Public
7493 @@ -9,6 +9,8 @@
7494 * warranty of any kind, whether express or implied.
7495 */
7496  
7497 +#define pr_fmt(fmt) "fsl-mc: " fmt
7498 +
7499 #include <linux/module.h>
7500 #include <linux/of_device.h>
7501 #include <linux/of_address.h>
7502 @@ -25,8 +27,6 @@
7503 #include "fsl-mc-private.h"
7504 #include "dprc-cmd.h"
7505  
7506 -static struct kmem_cache *mc_dev_cache;
7507 -
7508 /**
7509 * Default DMA mask for devices on a fsl-mc bus
7510 */
7511 @@ -34,7 +34,7 @@ static struct kmem_cache *mc_dev_cache;
7512  
7513 /**
7514 * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device
7515 - * @root_mc_bus_dev: MC object device representing the root DPRC
7516 + * @root_mc_bus_dev: fsl-mc device representing the root DPRC
7517 * @num_translation_ranges: number of entries in addr_translation_ranges
7518 * @translation_ranges: array of bus to system address translation ranges
7519 */
7520 @@ -62,8 +62,8 @@ struct fsl_mc_addr_translation_range {
7521  
7522 /**
7523 * fsl_mc_bus_match - device to driver matching callback
7524 - * @dev: the MC object device structure to match against
7525 - * @drv: the device driver to search for matching MC object device id
7526 + * @dev: the fsl-mc device to match against
7527 + * @drv: the device driver to search for matching fsl-mc object type
7528 * structures
7529 *
7530 * Returns 1 on success, 0 otherwise.
7531 @@ -75,8 +75,11 @@ static int fsl_mc_bus_match(struct devic
7532 struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(drv);
7533 bool found = false;
7534  
7535 - if (WARN_ON(!fsl_mc_bus_exists()))
7536 + /* When driver_override is set, only bind to the matching driver */
7537 + if (mc_dev->driver_override) {
7538 + found = !strcmp(mc_dev->driver_override, mc_drv->driver.name);
7539 goto out;
7540 + }
7541  
7542 if (!mc_drv->match_id_table)
7543 goto out;
7544 @@ -91,7 +94,7 @@ static int fsl_mc_bus_match(struct devic
7545  
7546 /*
7547 * Traverse the match_id table of the given driver, trying to find
7548 - * a matching for the given MC object device.
7549 + * a matching for the given device.
7550 */
7551 for (id = mc_drv->match_id_table; id->vendor != 0x0; id++) {
7552 if (id->vendor == mc_dev->obj_desc.vendor &&
7553 @@ -132,23 +135,141 @@ static ssize_t modalias_show(struct devi
7554 }
7555 static DEVICE_ATTR_RO(modalias);
7556  
7557 +static ssize_t rescan_store(struct device *dev,
7558 + struct device_attribute *attr,
7559 + const char *buf, size_t count)
7560 +{
7561 + unsigned long val;
7562 + unsigned int irq_count;
7563 + struct fsl_mc_device *root_mc_dev;
7564 + struct fsl_mc_bus *root_mc_bus;
7565 +
7566 + if (!fsl_mc_is_root_dprc(dev))
7567 + return -EINVAL;
7568 +
7569 + root_mc_dev = to_fsl_mc_device(dev);
7570 + root_mc_bus = to_fsl_mc_bus(root_mc_dev);
7571 +
7572 + if (kstrtoul(buf, 0, &val) < 0)
7573 + return -EINVAL;
7574 +
7575 + if (val) {
7576 + mutex_lock(&root_mc_bus->scan_mutex);
7577 + dprc_scan_objects(root_mc_dev, NULL, &irq_count);
7578 + mutex_unlock(&root_mc_bus->scan_mutex);
7579 + }
7580 +
7581 + return count;
7582 +}
7583 +static DEVICE_ATTR_WO(rescan);
7584 +
7585 +static ssize_t driver_override_store(struct device *dev,
7586 + struct device_attribute *attr,
7587 + const char *buf, size_t count)
7588 +{
7589 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7590 + const char *driver_override, *old = mc_dev->driver_override;
7591 + char *cp;
7592 +
7593 + if (WARN_ON(dev->bus != &fsl_mc_bus_type))
7594 + return -EINVAL;
7595 +
7596 + if (count >= (PAGE_SIZE - 1))
7597 + return -EINVAL;
7598 +
7599 + driver_override = kstrndup(buf, count, GFP_KERNEL);
7600 + if (!driver_override)
7601 + return -ENOMEM;
7602 +
7603 + cp = strchr(driver_override, '\n');
7604 + if (cp)
7605 + *cp = '\0';
7606 +
7607 + if (strlen(driver_override)) {
7608 + mc_dev->driver_override = driver_override;
7609 + } else {
7610 + kfree(driver_override);
7611 + mc_dev->driver_override = NULL;
7612 + }
7613 +
7614 + kfree(old);
7615 +
7616 + return count;
7617 +}
7618 +
7619 +static ssize_t driver_override_show(struct device *dev,
7620 + struct device_attribute *attr, char *buf)
7621 +{
7622 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7623 +
7624 + return snprintf(buf, PAGE_SIZE, "%s\n", mc_dev->driver_override);
7625 +}
7626 +static DEVICE_ATTR_RW(driver_override);
7627 +
7628 static struct attribute *fsl_mc_dev_attrs[] = {
7629 &dev_attr_modalias.attr,
7630 + &dev_attr_rescan.attr,
7631 + &dev_attr_driver_override.attr,
7632 NULL,
7633 };
7634  
7635 ATTRIBUTE_GROUPS(fsl_mc_dev);
7636  
7637 +static int scan_fsl_mc_bus(struct device *dev, void *data)
7638 +{
7639 + unsigned int irq_count;
7640 + struct fsl_mc_device *root_mc_dev;
7641 + struct fsl_mc_bus *root_mc_bus;
7642 +
7643 + if (fsl_mc_is_root_dprc(dev)) {
7644 + root_mc_dev = to_fsl_mc_device(dev);
7645 + root_mc_bus = to_fsl_mc_bus(root_mc_dev);
7646 + mutex_lock(&root_mc_bus->scan_mutex);
7647 + dprc_scan_objects(root_mc_dev, NULL, &irq_count);
7648 + mutex_unlock(&root_mc_bus->scan_mutex);
7649 + }
7650 +
7651 + return 0;
7652 +}
7653 +
7654 +static ssize_t bus_rescan_store(struct bus_type *bus,
7655 + const char *buf, size_t count)
7656 +{
7657 + unsigned long val;
7658 +
7659 + if (kstrtoul(buf, 0, &val) < 0)
7660 + return -EINVAL;
7661 +
7662 + if (val)
7663 + bus_for_each_dev(bus, NULL, NULL, scan_fsl_mc_bus);
7664 +
7665 + return count;
7666 +}
7667 +static BUS_ATTR(rescan, (S_IWUSR | S_IWGRP), NULL, bus_rescan_store);
7668 +
7669 +static struct attribute *fsl_mc_bus_attrs[] = {
7670 + &bus_attr_rescan.attr,
7671 + NULL,
7672 +};
7673 +
7674 +static const struct attribute_group fsl_mc_bus_group = {
7675 + .attrs = fsl_mc_bus_attrs,
7676 +};
7677 +
7678 +static const struct attribute_group *fsl_mc_bus_groups[] = {
7679 + &fsl_mc_bus_group,
7680 + NULL,
7681 +};
7682 +
7683 struct bus_type fsl_mc_bus_type = {
7684 .name = "fsl-mc",
7685 .match = fsl_mc_bus_match,
7686 .uevent = fsl_mc_bus_uevent,
7687 .dev_groups = fsl_mc_dev_groups,
7688 + .bus_groups = fsl_mc_bus_groups,
7689 };
7690 EXPORT_SYMBOL_GPL(fsl_mc_bus_type);
7691  
7692 -static atomic_t root_dprc_count = ATOMIC_INIT(0);
7693 -
7694 static int fsl_mc_driver_probe(struct device *dev)
7695 {
7696 struct fsl_mc_driver *mc_drv;
7697 @@ -164,8 +285,7 @@ static int fsl_mc_driver_probe(struct de
7698  
7699 error = mc_drv->probe(mc_dev);
7700 if (error < 0) {
7701 - dev_err(dev, "MC object device probe callback failed: %d\n",
7702 - error);
7703 + dev_err(dev, "%s failed: %d\n", __func__, error);
7704 return error;
7705 }
7706  
7707 @@ -183,9 +303,7 @@ static int fsl_mc_driver_remove(struct d
7708  
7709 error = mc_drv->remove(mc_dev);
7710 if (error < 0) {
7711 - dev_err(dev,
7712 - "MC object device remove callback failed: %d\n",
7713 - error);
7714 + dev_err(dev, "%s failed: %d\n", __func__, error);
7715 return error;
7716 }
7717  
7718 @@ -232,8 +350,6 @@ int __fsl_mc_driver_register(struct fsl_
7719 return error;
7720 }
7721  
7722 - pr_info("MC object device driver %s registered\n",
7723 - mc_driver->driver.name);
7724 return 0;
7725 }
7726 EXPORT_SYMBOL_GPL(__fsl_mc_driver_register);
7727 @@ -249,15 +365,6 @@ void fsl_mc_driver_unregister(struct fsl
7728 EXPORT_SYMBOL_GPL(fsl_mc_driver_unregister);
7729  
7730 /**
7731 - * fsl_mc_bus_exists - check if a root dprc exists
7732 - */
7733 -bool fsl_mc_bus_exists(void)
7734 -{
7735 - return atomic_read(&root_dprc_count) > 0;
7736 -}
7737 -EXPORT_SYMBOL_GPL(fsl_mc_bus_exists);
7738 -
7739 -/**
7740 * fsl_mc_get_root_dprc - function to traverse to the root dprc
7741 */
7742 void fsl_mc_get_root_dprc(struct device *dev,
7743 @@ -315,21 +422,6 @@ static int get_dprc_icid(struct fsl_mc_i
7744 return error;
7745 }
7746  
7747 -static int get_dprc_version(struct fsl_mc_io *mc_io,
7748 - int container_id, u16 *major, u16 *minor)
7749 -{
7750 - struct dprc_attributes attr;
7751 - int error;
7752 -
7753 - error = get_dprc_attr(mc_io, container_id, &attr);
7754 - if (error == 0) {
7755 - *major = attr.version.major;
7756 - *minor = attr.version.minor;
7757 - }
7758 -
7759 - return error;
7760 -}
7761 -
7762 static int translate_mc_addr(struct fsl_mc_device *mc_dev,
7763 enum dprc_region_type mc_region_type,
7764 u64 mc_offset, phys_addr_t *phys_addr)
7765 @@ -451,18 +543,37 @@ bool fsl_mc_is_root_dprc(struct device *
7766 return dev == root_dprc_dev;
7767 }
7768  
7769 +static void fsl_mc_device_release(struct device *dev)
7770 +{
7771 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7772 + struct fsl_mc_bus *mc_bus = NULL;
7773 +
7774 + kfree(mc_dev->regions);
7775 +
7776 + if (strcmp(mc_dev->obj_desc.type, "dprc") == 0)
7777 + mc_bus = to_fsl_mc_bus(mc_dev);
7778 +
7779 + if (mc_bus)
7780 + kfree(mc_bus);
7781 + else
7782 + kfree(mc_dev);
7783 +}
7784 +
7785 /**
7786 - * Add a newly discovered MC object device to be visible in Linux
7787 + * Add a newly discovered fsl-mc device to be visible in Linux
7788 */
7789 int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
7790 struct fsl_mc_io *mc_io,
7791 struct device *parent_dev,
7792 + const char *driver_override,
7793 struct fsl_mc_device **new_mc_dev)
7794 {
7795 int error;
7796 struct fsl_mc_device *mc_dev = NULL;
7797 struct fsl_mc_bus *mc_bus = NULL;
7798 struct fsl_mc_device *parent_mc_dev;
7799 + struct device *fsl_mc_platform_dev;
7800 + struct device_node *fsl_mc_platform_node;
7801  
7802 if (dev_is_fsl_mc(parent_dev))
7803 parent_mc_dev = to_fsl_mc_device(parent_dev);
7804 @@ -473,7 +584,7 @@ int fsl_mc_device_add(struct dprc_obj_de
7805 /*
7806 * Allocate an MC bus device object:
7807 */
7808 - mc_bus = devm_kzalloc(parent_dev, sizeof(*mc_bus), GFP_KERNEL);
7809 + mc_bus = kzalloc(sizeof(*mc_bus), GFP_KERNEL);
7810 if (!mc_bus)
7811 return -ENOMEM;
7812  
7813 @@ -482,16 +593,30 @@ int fsl_mc_device_add(struct dprc_obj_de
7814 /*
7815 * Allocate a regular fsl_mc_device object:
7816 */
7817 - mc_dev = kmem_cache_zalloc(mc_dev_cache, GFP_KERNEL);
7818 + mc_dev = kzalloc(sizeof(*mc_dev), GFP_KERNEL);
7819 if (!mc_dev)
7820 return -ENOMEM;
7821 }
7822  
7823 mc_dev->obj_desc = *obj_desc;
7824 mc_dev->mc_io = mc_io;
7825 +
7826 + if (driver_override) {
7827 + /*
7828 + * We trust driver_override, so we don't need to use
7829 + * kstrndup() here
7830 + */
7831 + mc_dev->driver_override = kstrdup(driver_override, GFP_KERNEL);
7832 + if (!mc_dev->driver_override) {
7833 + error = -ENOMEM;
7834 + goto error_cleanup_dev;
7835 + }
7836 + }
7837 +
7838 device_initialize(&mc_dev->dev);
7839 mc_dev->dev.parent = parent_dev;
7840 mc_dev->dev.bus = &fsl_mc_bus_type;
7841 + mc_dev->dev.release = fsl_mc_device_release;
7842 dev_set_name(&mc_dev->dev, "%s.%d", obj_desc->type, obj_desc->id);
7843  
7844 if (strcmp(obj_desc->type, "dprc") == 0) {
7845 @@ -524,8 +649,6 @@ int fsl_mc_device_add(struct dprc_obj_de
7846 }
7847  
7848 mc_io2 = mc_io;
7849 -
7850 - atomic_inc(&root_dprc_count);
7851 }
7852  
7853 error = get_dprc_icid(mc_io2, obj_desc->id, &mc_dev->icid);
7854 @@ -533,8 +656,8 @@ int fsl_mc_device_add(struct dprc_obj_de
7855 goto error_cleanup_dev;
7856 } else {
7857 /*
7858 - * A non-DPRC MC object device has to be a child of another
7859 - * MC object (specifically a DPRC object)
7860 + * A non-DPRC object has to be a child of a DPRC, use the
7861 + * parent's ICID and interrupt domain.
7862 */
7863 mc_dev->icid = parent_mc_dev->icid;
7864 mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK;
7865 @@ -556,9 +679,14 @@ int fsl_mc_device_add(struct dprc_obj_de
7866 goto error_cleanup_dev;
7867 }
7868  
7869 - /* Objects are coherent, unless 'no shareability' flag set. */
7870 - if (!(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY))
7871 - arch_setup_dma_ops(&mc_dev->dev, 0, 0, NULL, true);
7872 + fsl_mc_platform_dev = &mc_dev->dev;
7873 + while (dev_is_fsl_mc(fsl_mc_platform_dev))
7874 + fsl_mc_platform_dev = fsl_mc_platform_dev->parent;
7875 + fsl_mc_platform_node = fsl_mc_platform_dev->of_node;
7876 +
7877 + /* Set up the iommu configuration for the devices. */
7878 + fsl_mc_dma_configure(mc_dev, fsl_mc_platform_node,
7879 + !(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY));
7880  
7881 /*
7882 * The device-specific probe callback will get invoked by device_add()
7883 @@ -571,9 +699,7 @@ int fsl_mc_device_add(struct dprc_obj_de
7884 goto error_cleanup_dev;
7885 }
7886  
7887 - (void)get_device(&mc_dev->dev);
7888 - dev_dbg(parent_dev, "Added MC object device %s\n",
7889 - dev_name(&mc_dev->dev));
7890 + dev_dbg(parent_dev, "added %s\n", dev_name(&mc_dev->dev));
7891  
7892 *new_mc_dev = mc_dev;
7893 return 0;
7894 @@ -581,47 +707,34 @@ int fsl_mc_device_add(struct dprc_obj_de
7895 error_cleanup_dev:
7896 kfree(mc_dev->regions);
7897 if (mc_bus)
7898 - devm_kfree(parent_dev, mc_bus);
7899 + kfree(mc_bus);
7900 else
7901 - kmem_cache_free(mc_dev_cache, mc_dev);
7902 + kfree(mc_dev);
7903  
7904 return error;
7905 }
7906 EXPORT_SYMBOL_GPL(fsl_mc_device_add);
7907  
7908 /**
7909 - * fsl_mc_device_remove - Remove a MC object device from being visible to
7910 + * fsl_mc_device_remove - Remove an fsl-mc device from being visible to
7911 * Linux
7912 *
7913 - * @mc_dev: Pointer to a MC object device object
7914 + * @mc_dev: Pointer to an fsl-mc device
7915 */
7916 void fsl_mc_device_remove(struct fsl_mc_device *mc_dev)
7917 {
7918 - struct fsl_mc_bus *mc_bus = NULL;
7919 -
7920 - kfree(mc_dev->regions);
7921 + kfree(mc_dev->driver_override);
7922 + mc_dev->driver_override = NULL;
7923  
7924 /*
7925 * The device-specific remove callback will get invoked by device_del()
7926 */
7927 device_del(&mc_dev->dev);
7928 - put_device(&mc_dev->dev);
7929  
7930 - if (strcmp(mc_dev->obj_desc.type, "dprc") == 0) {
7931 - mc_bus = to_fsl_mc_bus(mc_dev);
7932 -
7933 - if (fsl_mc_is_root_dprc(&mc_dev->dev)) {
7934 - if (atomic_read(&root_dprc_count) > 0)
7935 - atomic_dec(&root_dprc_count);
7936 - else
7937 - WARN_ON(1);
7938 - }
7939 - }
7940 + if (strcmp(mc_dev->obj_desc.type, "dprc") != 0)
7941 + mc_dev->dev.iommu_fwspec = NULL;
7942  
7943 - if (mc_bus)
7944 - devm_kfree(mc_dev->dev.parent, mc_bus);
7945 - else
7946 - kmem_cache_free(mc_dev_cache, mc_dev);
7947 + put_device(&mc_dev->dev);
7948 }
7949 EXPORT_SYMBOL_GPL(fsl_mc_device_remove);
7950  
7951 @@ -629,8 +742,7 @@ static int parse_mc_ranges(struct device
7952 int *paddr_cells,
7953 int *mc_addr_cells,
7954 int *mc_size_cells,
7955 - const __be32 **ranges_start,
7956 - u8 *num_ranges)
7957 + const __be32 **ranges_start)
7958 {
7959 const __be32 *prop;
7960 int range_tuple_cell_count;
7961 @@ -643,8 +755,6 @@ static int parse_mc_ranges(struct device
7962 dev_warn(dev,
7963 "missing or empty ranges property for device tree node '%s'\n",
7964 mc_node->name);
7965 -
7966 - *num_ranges = 0;
7967 return 0;
7968 }
7969  
7970 @@ -671,8 +781,7 @@ static int parse_mc_ranges(struct device
7971 return -EINVAL;
7972 }
7973  
7974 - *num_ranges = ranges_len / tuple_len;
7975 - return 0;
7976 + return ranges_len / tuple_len;
7977 }
7978  
7979 static int get_mc_addr_translation_ranges(struct device *dev,
7980 @@ -680,7 +789,7 @@ static int get_mc_addr_translation_range
7981 **ranges,
7982 u8 *num_ranges)
7983 {
7984 - int error;
7985 + int ret;
7986 int paddr_cells;
7987 int mc_addr_cells;
7988 int mc_size_cells;
7989 @@ -688,16 +797,16 @@ static int get_mc_addr_translation_range
7990 const __be32 *ranges_start;
7991 const __be32 *cell;
7992  
7993 - error = parse_mc_ranges(dev,
7994 + ret = parse_mc_ranges(dev,
7995 &paddr_cells,
7996 &mc_addr_cells,
7997 &mc_size_cells,
7998 - &ranges_start,
7999 - num_ranges);
8000 - if (error < 0)
8001 - return error;
8002 + &ranges_start);
8003 + if (ret < 0)
8004 + return ret;
8005  
8006 - if (!(*num_ranges)) {
8007 + *num_ranges = ret;
8008 + if (!ret) {
8009 /*
8010 * Missing or empty ranges property ("ranges;") for the
8011 * 'fsl,qoriq-mc' node. In this case, identity mapping
8012 @@ -749,8 +858,6 @@ static int fsl_mc_bus_probe(struct platf
8013 struct mc_version mc_version;
8014 struct resource res;
8015  
8016 - dev_info(&pdev->dev, "Root MC bus device probed");
8017 -
8018 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
8019 if (!mc)
8020 return -ENOMEM;
8021 @@ -783,8 +890,7 @@ static int fsl_mc_bus_probe(struct platf
8022 goto error_cleanup_mc_io;
8023 }
8024  
8025 - dev_info(&pdev->dev,
8026 - "Freescale Management Complex Firmware version: %u.%u.%u\n",
8027 + dev_info(&pdev->dev, "MC firmware version: %u.%u.%u\n",
8028 mc_version.major, mc_version.minor, mc_version.revision);
8029  
8030 error = get_mc_addr_translation_ranges(&pdev->dev,
8031 @@ -793,16 +899,17 @@ static int fsl_mc_bus_probe(struct platf
8032 if (error < 0)
8033 goto error_cleanup_mc_io;
8034  
8035 - error = dpmng_get_container_id(mc_io, 0, &container_id);
8036 + error = dprc_get_container_id(mc_io, 0, &container_id);
8037 if (error < 0) {
8038 dev_err(&pdev->dev,
8039 - "dpmng_get_container_id() failed: %d\n", error);
8040 + "dprc_get_container_id() failed: %d\n", error);
8041 goto error_cleanup_mc_io;
8042 }
8043  
8044 memset(&obj_desc, 0, sizeof(struct dprc_obj_desc));
8045 - error = get_dprc_version(mc_io, container_id,
8046 - &obj_desc.ver_major, &obj_desc.ver_minor);
8047 + error = dprc_get_api_version(mc_io, 0,
8048 + &obj_desc.ver_major,
8049 + &obj_desc.ver_minor);
8050 if (error < 0)
8051 goto error_cleanup_mc_io;
8052  
8053 @@ -812,7 +919,8 @@ static int fsl_mc_bus_probe(struct platf
8054 obj_desc.irq_count = 1;
8055 obj_desc.region_count = 0;
8056  
8057 - error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, &mc_bus_dev);
8058 + error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, NULL,
8059 + &mc_bus_dev);
8060 if (error < 0)
8061 goto error_cleanup_mc_io;
8062  
8063 @@ -840,7 +948,6 @@ static int fsl_mc_bus_remove(struct plat
8064 fsl_destroy_mc_io(mc->root_mc_bus_dev->mc_io);
8065 mc->root_mc_bus_dev->mc_io = NULL;
8066  
8067 - dev_info(&pdev->dev, "Root MC bus device removed");
8068 return 0;
8069 }
8070  
8071 @@ -865,22 +972,12 @@ static int __init fsl_mc_bus_driver_init
8072 {
8073 int error;
8074  
8075 - mc_dev_cache = kmem_cache_create("fsl_mc_device",
8076 - sizeof(struct fsl_mc_device), 0, 0,
8077 - NULL);
8078 - if (!mc_dev_cache) {
8079 - pr_err("Could not create fsl_mc_device cache\n");
8080 - return -ENOMEM;
8081 - }
8082 -
8083 error = bus_register(&fsl_mc_bus_type);
8084 if (error < 0) {
8085 - pr_err("fsl-mc bus type registration failed: %d\n", error);
8086 + pr_err("bus type registration failed: %d\n", error);
8087 goto error_cleanup_cache;
8088 }
8089  
8090 - pr_info("fsl-mc bus type registered\n");
8091 -
8092 error = platform_driver_register(&fsl_mc_bus_driver);
8093 if (error < 0) {
8094 pr_err("platform_driver_register() failed: %d\n", error);
8095 @@ -914,7 +1011,6 @@ error_cleanup_bus:
8096 bus_unregister(&fsl_mc_bus_type);
8097  
8098 error_cleanup_cache:
8099 - kmem_cache_destroy(mc_dev_cache);
8100 return error;
8101 }
8102 postcore_initcall(fsl_mc_bus_driver_init);
8103 --- /dev/null
8104 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-iommu.c
8105 @@ -0,0 +1,104 @@
8106 +/*
8107 + * Copyright 2016-17 NXP
8108 + * Author: Nipun Gupta <nipun.gupta@nxp.com>
8109 + *
8110 + * This file is licensed under the terms of the GNU General Public
8111 + * License version 2. This program is licensed "as is" without any
8112 + * warranty of any kind, whether express or implied.
8113 + */
8114 +
8115 +#include <linux/iommu.h>
8116 +#include <linux/of.h>
8117 +#include <linux/of_iommu.h>
8118 +#include "../include/mc.h"
8119 +
8120 +/* Setup the IOMMU for the DPRC container */
8121 +static const struct iommu_ops
8122 +*fsl_mc_iommu_configure(struct fsl_mc_device *mc_dev,
8123 + struct device_node *fsl_mc_platform_node)
8124 +{
8125 + struct of_phandle_args iommu_spec;
8126 + const struct iommu_ops *ops;
8127 + u32 iommu_phandle;
8128 + struct device_node *iommu_node;
8129 + const __be32 *map = NULL;
8130 + int iommu_cells, map_len, ret;
8131 +
8132 + map = of_get_property(fsl_mc_platform_node, "iommu-map", &map_len);
8133 + if (!map)
8134 + return NULL;
8135 +
8136 + ops = mc_dev->dev.bus->iommu_ops;
8137 + if (!ops || !ops->of_xlate)
8138 + return NULL;
8139 +
8140 + iommu_phandle = be32_to_cpup(map + 1);
8141 + iommu_node = of_find_node_by_phandle(iommu_phandle);
8142 +
8143 + if (of_property_read_u32(iommu_node, "#iommu-cells", &iommu_cells)) {
8144 + pr_err("%s: missing #iommu-cells property\n", iommu_node->name);
8145 + return NULL;
8146 + }
8147 +
8148 + /* Initialize the fwspec */
8149 + ret = iommu_fwspec_init(&mc_dev->dev, &iommu_node->fwnode, ops);
8150 + if (ret)
8151 + return NULL;
8152 +
8153 + /*
8154 + * Fill in the required stream-id before calling the iommu's
8155 + * ops->xlate callback.
8156 + */
8157 + iommu_spec.np = iommu_node;
8158 + iommu_spec.args[0] = mc_dev->icid;
8159 + iommu_spec.args_count = 1;
8160 +
8161 + ret = ops->of_xlate(&mc_dev->dev, &iommu_spec);
8162 + if (ret)
8163 + return NULL;
8164 +
8165 + of_node_put(iommu_spec.np);
8166 +
8167 + return ops;
8168 +}
8169 +
8170 +/* Set up DMA configuration for fsl-mc devices */
8171 +void fsl_mc_dma_configure(struct fsl_mc_device *mc_dev,
8172 + struct device_node *fsl_mc_platform_node, int coherent)
8173 +{
8174 + const struct iommu_ops *ops;
8175 +
8176 + ops = fsl_mc_iommu_configure(mc_dev, fsl_mc_platform_node);
8177 +
8178 + mc_dev->dev.coherent_dma_mask = DMA_BIT_MASK(48);
8179 + mc_dev->dev.dma_mask = &mc_dev->dev.coherent_dma_mask;
8180 + arch_setup_dma_ops(&mc_dev->dev, 0,
8181 + mc_dev->dev.coherent_dma_mask + 1, ops, coherent);
8182 +}
8183 +
8184 +/* Macro to get the container device of a MC device */
8185 +#define fsl_mc_cont_dev(_dev) ((to_fsl_mc_device(_dev)->flags & \
8186 + FSL_MC_IS_DPRC) ? (_dev) : ((_dev)->parent))
8187 +
8188 +/* Macro to check if a device is a container device */
8189 +#define is_cont_dev(_dev) (to_fsl_mc_device(_dev)->flags & FSL_MC_IS_DPRC)
8190 +
8191 +/* Get the IOMMU group for device on fsl-mc bus */
8192 +struct iommu_group *fsl_mc_device_group(struct device *dev)
8193 +{
8194 + struct device *cont_dev = fsl_mc_cont_dev(dev);
8195 + struct iommu_group *group;
8196 +
8197 + /* Container device is responsible for creating the iommu group */
8198 + if (is_cont_dev(dev)) {
8199 + group = iommu_group_alloc();
8200 + if (IS_ERR(group))
8201 + return NULL;
8202 + } else {
8203 + get_device(cont_dev);
8204 + group = iommu_group_get(cont_dev);
8205 + put_device(cont_dev);
8206 + }
8207 +
8208 + return group;
8209 +}
8210 --- a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
8211 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
8212 @@ -1,7 +1,7 @@
8213 /*
8214 * Freescale Management Complex (MC) bus driver MSI support
8215 *
8216 - * Copyright (C) 2015 Freescale Semiconductor, Inc.
8217 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
8218 * Author: German Rivera <German.Rivera@freescale.com>
8219 *
8220 * This file is licensed under the terms of the GNU General Public
8221 --- a/drivers/staging/fsl-mc/bus/fsl-mc-private.h
8222 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-private.h
8223 @@ -10,13 +10,15 @@
8224 #ifndef _FSL_MC_PRIVATE_H_
8225 #define _FSL_MC_PRIVATE_H_
8226  
8227 +#include "../include/mc.h"
8228 +#include "../include/mc-bus.h"
8229 +
8230 int __must_check fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
8231 struct fsl_mc_io *mc_io,
8232 struct device *parent_dev,
8233 + const char *driver_override,
8234 struct fsl_mc_device **new_mc_dev);
8235  
8236 -void fsl_mc_device_remove(struct fsl_mc_device *mc_dev);
8237 -
8238 int __init dprc_driver_init(void);
8239  
8240 void dprc_driver_exit(void);
8241 --- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
8242 +++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
8243 @@ -1,7 +1,7 @@
8244 /*
8245 * Freescale Management Complex (MC) bus driver MSI support
8246 *
8247 - * Copyright (C) 2015 Freescale Semiconductor, Inc.
8248 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
8249 * Author: German Rivera <German.Rivera@freescale.com>
8250 *
8251 * This file is licensed under the terms of the GNU General Public
8252 @@ -20,7 +20,7 @@
8253 #include "fsl-mc-private.h"
8254  
8255 static struct irq_chip its_msi_irq_chip = {
8256 - .name = "fsl-mc-bus-msi",
8257 + .name = "ITS-fMSI",
8258 .irq_mask = irq_chip_mask_parent,
8259 .irq_unmask = irq_chip_unmask_parent,
8260 .irq_eoi = irq_chip_eoi_parent,
8261 @@ -52,7 +52,7 @@ static int its_fsl_mc_msi_prepare(struct
8262 return msi_info->ops->msi_prepare(msi_domain->parent, dev, nvec, info);
8263 }
8264  
8265 -static struct msi_domain_ops its_fsl_mc_msi_ops = {
8266 +static struct msi_domain_ops its_fsl_mc_msi_ops __ro_after_init = {
8267 .msi_prepare = its_fsl_mc_msi_prepare,
8268 };
8269  
8270 @@ -97,8 +97,8 @@ int __init its_fsl_mc_msi_init(void)
8271 continue;
8272 }
8273  
8274 - WARN_ON(mc_msi_domain->
8275 - host_data != &its_fsl_mc_msi_domain_info);
8276 + WARN_ON(mc_msi_domain->host_data !=
8277 + &its_fsl_mc_msi_domain_info);
8278  
8279 pr_info("fsl-mc MSI: %s domain created\n", np->full_name);
8280 }
8281 --- a/drivers/staging/fsl-mc/bus/mc-io.c
8282 +++ b/drivers/staging/fsl-mc/bus/mc-io.c
8283 @@ -1,4 +1,5 @@
8284 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
8285 +/*
8286 + * Copyright 2013-2016 Freescale Semiconductor Inc.
8287 *
8288 * Redistribution and use in source and binary forms, with or without
8289 * modification, are permitted provided that the following conditions are met:
8290 @@ -11,7 +12,6 @@
8291 * names of any contributors may be used to endorse or promote products
8292 * derived from this software without specific prior written permission.
8293 *
8294 - *
8295 * ALTERNATIVELY, this software may be distributed under the terms of the
8296 * GNU General Public License ("GPL") as published by the Free Software
8297 * Foundation, either version 2 of that License or (at your option) any
8298 --- /dev/null
8299 +++ b/drivers/staging/fsl-mc/bus/mc-ioctl.h
8300 @@ -0,0 +1,22 @@
8301 +/*
8302 + * Freescale Management Complex (MC) ioclt interface
8303 + *
8304 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
8305 + * Author: Lijun Pan <Lijun.Pan@freescale.com>
8306 + *
8307 + * This file is licensed under the terms of the GNU General Public
8308 + * License version 2. This program is licensed "as is" without any
8309 + * warranty of any kind, whether express or implied.
8310 + */
8311 +#ifndef _FSL_MC_IOCTL_H_
8312 +#define _FSL_MC_IOCTL_H_
8313 +
8314 +#include <linux/ioctl.h>
8315 +#include "../include/mc-sys.h"
8316 +
8317 +#define RESTOOL_IOCTL_TYPE 'R'
8318 +
8319 +#define RESTOOL_SEND_MC_COMMAND \
8320 + _IOWR(RESTOOL_IOCTL_TYPE, 0xE0, struct mc_command)
8321 +
8322 +#endif /* _FSL_MC_IOCTL_H_ */
8323 --- /dev/null
8324 +++ b/drivers/staging/fsl-mc/bus/mc-restool.c
8325 @@ -0,0 +1,405 @@
8326 +/*
8327 + * Freescale Management Complex (MC) restool driver
8328 + *
8329 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
8330 + * Author: Lijun Pan <Lijun.Pan@freescale.com>
8331 + *
8332 + * This file is licensed under the terms of the GNU General Public
8333 + * License version 2. This program is licensed "as is" without any
8334 + * warranty of any kind, whether express or implied.
8335 + */
8336 +
8337 +#include "../include/mc.h"
8338 +#include <linux/module.h>
8339 +#include <linux/fs.h>
8340 +#include <linux/miscdevice.h>
8341 +#include <linux/mm.h>
8342 +#include <linux/slab.h>
8343 +#include <linux/uaccess.h>
8344 +#include <linux/mutex.h>
8345 +#include <linux/platform_device.h>
8346 +#include "mc-ioctl.h"
8347 +#include "../include/mc-sys.h"
8348 +#include "../include/mc-bus.h"
8349 +#include "../include/mc-cmd.h"
8350 +#include "../include/dpmng.h"
8351 +
8352 +/**
8353 + * Maximum number of DPRCs that can be opened at the same time
8354 + */
8355 +#define MAX_DPRC_HANDLES 64
8356 +
8357 +/**
8358 + * restool_misc - information associated with the newly added miscdevice
8359 + * @misc: newly created miscdevice associated with root dprc
8360 + * @miscdevt: device id of this miscdevice
8361 + * @list: a linked list node representing this miscdevcie
8362 + * @static_mc_io: pointer to the static MC I/O object used by the restool
8363 + * @dynamic_instance_count: number of dynamically created instances
8364 + * @static_instance_in_use: static instance is in use or not
8365 + * @mutex: mutex lock to serialze the open/release operations
8366 + * @dev: root dprc associated with this miscdevice
8367 + */
8368 +struct restool_misc {
8369 + struct miscdevice misc;
8370 + dev_t miscdevt;
8371 + struct list_head list;
8372 + struct fsl_mc_io *static_mc_io;
8373 + u32 dynamic_instance_count;
8374 + bool static_instance_in_use;
8375 + struct mutex mutex; /* serialze the open/release operations */
8376 + struct device *dev;
8377 +};
8378 +
8379 +/**
8380 + * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device
8381 + * @root_mc_bus_dev: fsl-mc device representing the root DPRC
8382 + * @num_translation_ranges: number of entries in addr_translation_ranges
8383 + * @translation_ranges: array of bus to system address translation ranges
8384 + */
8385 +struct fsl_mc {
8386 + struct fsl_mc_device *root_mc_bus_dev;
8387 + u8 num_translation_ranges;
8388 + struct fsl_mc_addr_translation_range *translation_ranges;
8389 +};
8390 +
8391 +/*
8392 + * initialize a global list to link all
8393 + * the miscdevice nodes (struct restool_misc)
8394 + */
8395 +static LIST_HEAD(misc_list);
8396 +static DEFINE_MUTEX(misc_list_mutex);
8397 +
8398 +static int fsl_mc_restool_dev_open(struct inode *inode, struct file *filep)
8399 +{
8400 + struct fsl_mc_device *root_mc_dev;
8401 + int error;
8402 + struct fsl_mc_io *dynamic_mc_io = NULL;
8403 + struct restool_misc *restool_misc = NULL;
8404 + struct restool_misc *restool_misc_cursor;
8405 +
8406 + mutex_lock(&misc_list_mutex);
8407 +
8408 + list_for_each_entry(restool_misc_cursor, &misc_list, list) {
8409 + if (restool_misc_cursor->miscdevt == inode->i_rdev) {
8410 + restool_misc = restool_misc_cursor;
8411 + break;
8412 + }
8413 + }
8414 +
8415 + mutex_unlock(&misc_list_mutex);
8416 +
8417 + if (!restool_misc)
8418 + return -EINVAL;
8419 +
8420 + if (WARN_ON(!restool_misc->dev))
8421 + return -EINVAL;
8422 +
8423 + mutex_lock(&restool_misc->mutex);
8424 +
8425 + if (!restool_misc->static_instance_in_use) {
8426 + restool_misc->static_instance_in_use = true;
8427 + filep->private_data = restool_misc->static_mc_io;
8428 + } else {
8429 + dynamic_mc_io = kzalloc(sizeof(*dynamic_mc_io), GFP_KERNEL);
8430 + if (!dynamic_mc_io) {
8431 + error = -ENOMEM;
8432 + goto err_unlock;
8433 + }
8434 +
8435 + root_mc_dev = to_fsl_mc_device(restool_misc->dev);
8436 + error = fsl_mc_portal_allocate(root_mc_dev, 0, &dynamic_mc_io);
8437 + if (error < 0) {
8438 + pr_err("Not able to allocate MC portal\n");
8439 + goto free_dynamic_mc_io;
8440 + }
8441 + ++restool_misc->dynamic_instance_count;
8442 + filep->private_data = dynamic_mc_io;
8443 + }
8444 +
8445 + mutex_unlock(&restool_misc->mutex);
8446 +
8447 + return 0;
8448 +
8449 +free_dynamic_mc_io:
8450 + kfree(dynamic_mc_io);
8451 +err_unlock:
8452 + mutex_unlock(&restool_misc->mutex);
8453 +
8454 + return error;
8455 +}
8456 +
8457 +static int fsl_mc_restool_dev_release(struct inode *inode, struct file *filep)
8458 +{
8459 + struct fsl_mc_io *local_mc_io = filep->private_data;
8460 + struct restool_misc *restool_misc = NULL;
8461 + struct restool_misc *restool_misc_cursor;
8462 +
8463 + if (WARN_ON(!filep->private_data))
8464 + return -EINVAL;
8465 +
8466 + mutex_lock(&misc_list_mutex);
8467 +
8468 + list_for_each_entry(restool_misc_cursor, &misc_list, list) {
8469 + if (restool_misc_cursor->miscdevt == inode->i_rdev) {
8470 + restool_misc = restool_misc_cursor;
8471 + break;
8472 + }
8473 + }
8474 +
8475 + mutex_unlock(&misc_list_mutex);
8476 +
8477 + if (!restool_misc)
8478 + return -EINVAL;
8479 +
8480 + mutex_lock(&restool_misc->mutex);
8481 +
8482 + if (WARN_ON(restool_misc->dynamic_instance_count == 0 &&
8483 + !restool_misc->static_instance_in_use)) {
8484 + mutex_unlock(&restool_misc->mutex);
8485 + return -EINVAL;
8486 + }
8487 +
8488 + /* Globally clean up opened/untracked handles */
8489 + fsl_mc_portal_reset(local_mc_io);
8490 +
8491 + /*
8492 + * must check
8493 + * whether local_mc_io is dynamic or static instance
8494 + * Otherwise it will free up the reserved portal by accident
8495 + * or even not free up the dynamic allocated portal
8496 + * if 2 or more instances running concurrently
8497 + */
8498 + if (local_mc_io == restool_misc->static_mc_io) {
8499 + restool_misc->static_instance_in_use = false;
8500 + } else {
8501 + fsl_mc_portal_free(local_mc_io);
8502 + kfree(filep->private_data);
8503 + --restool_misc->dynamic_instance_count;
8504 + }
8505 +
8506 + filep->private_data = NULL;
8507 + mutex_unlock(&restool_misc->mutex);
8508 +
8509 + return 0;
8510 +}
8511 +
8512 +static int restool_send_mc_command(unsigned long arg,
8513 + struct fsl_mc_io *local_mc_io)
8514 +{
8515 + int error;
8516 + struct mc_command mc_cmd;
8517 +
8518 + if (copy_from_user(&mc_cmd, (void __user *)arg, sizeof(mc_cmd)))
8519 + return -EFAULT;
8520 +
8521 + /*
8522 + * Send MC command to the MC:
8523 + */
8524 + error = mc_send_command(local_mc_io, &mc_cmd);
8525 + if (error < 0)
8526 + return error;
8527 +
8528 + if (copy_to_user((void __user *)arg, &mc_cmd, sizeof(mc_cmd)))
8529 + return -EFAULT;
8530 +
8531 + return 0;
8532 +}
8533 +
8534 +static long
8535 +fsl_mc_restool_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
8536 +{
8537 + int error;
8538 +
8539 + switch (cmd) {
8540 + case RESTOOL_SEND_MC_COMMAND:
8541 + error = restool_send_mc_command(arg, file->private_data);
8542 + break;
8543 + default:
8544 + pr_err("%s: unexpected ioctl call number\n", __func__);
8545 + error = -EINVAL;
8546 + }
8547 +
8548 + return error;
8549 +}
8550 +
8551 +static const struct file_operations fsl_mc_restool_dev_fops = {
8552 + .owner = THIS_MODULE,
8553 + .open = fsl_mc_restool_dev_open,
8554 + .release = fsl_mc_restool_dev_release,
8555 + .unlocked_ioctl = fsl_mc_restool_dev_ioctl,
8556 +};
8557 +
8558 +static int restool_add_device_file(struct device *dev)
8559 +{
8560 + u32 name1 = 0;
8561 + char name2[20] = {0};
8562 + int error;
8563 + struct fsl_mc_device *root_mc_dev;
8564 + struct restool_misc *restool_misc;
8565 +
8566 + if (dev->bus == &platform_bus_type && dev->driver_data) {
8567 + if (sscanf(dev_name(dev), "%x.%s", &name1, name2) != 2)
8568 + return -EINVAL;
8569 +
8570 + if (strcmp(name2, "fsl-mc") == 0)
8571 + pr_debug("platform's root dprc name is: %s\n",
8572 + dev_name(&(((struct fsl_mc *)
8573 + (dev->driver_data))->root_mc_bus_dev->dev)));
8574 + }
8575 +
8576 + if (!fsl_mc_is_root_dprc(dev))
8577 + return 0;
8578 +
8579 + restool_misc = kzalloc(sizeof(*restool_misc), GFP_KERNEL);
8580 + if (!restool_misc)
8581 + return -ENOMEM;
8582 +
8583 + restool_misc->dev = dev;
8584 + root_mc_dev = to_fsl_mc_device(dev);
8585 + error = fsl_mc_portal_allocate(root_mc_dev, 0,
8586 + &restool_misc->static_mc_io);
8587 + if (error < 0) {
8588 + pr_err("Not able to allocate MC portal\n");
8589 + goto free_restool_misc;
8590 + }
8591 +
8592 + restool_misc->misc.minor = MISC_DYNAMIC_MINOR;
8593 + restool_misc->misc.name = dev_name(dev);
8594 + restool_misc->misc.fops = &fsl_mc_restool_dev_fops;
8595 +
8596 + error = misc_register(&restool_misc->misc);
8597 + if (error < 0) {
8598 + pr_err("misc_register() failed: %d\n", error);
8599 + goto free_portal;
8600 + }
8601 +
8602 + restool_misc->miscdevt = restool_misc->misc.this_device->devt;
8603 + mutex_init(&restool_misc->mutex);
8604 + mutex_lock(&misc_list_mutex);
8605 + list_add(&restool_misc->list, &misc_list);
8606 + mutex_unlock(&misc_list_mutex);
8607 +
8608 + pr_info("/dev/%s driver registered\n", dev_name(dev));
8609 +
8610 + return 0;
8611 +
8612 +free_portal:
8613 + fsl_mc_portal_free(restool_misc->static_mc_io);
8614 +free_restool_misc:
8615 + kfree(restool_misc);
8616 +
8617 + return error;
8618 +}
8619 +
8620 +static int restool_bus_notifier(struct notifier_block *nb,
8621 + unsigned long action, void *data)
8622 +{
8623 + int error;
8624 + struct device *dev = data;
8625 +
8626 + switch (action) {
8627 + case BUS_NOTIFY_ADD_DEVICE:
8628 + error = restool_add_device_file(dev);
8629 + if (error)
8630 + return error;
8631 + break;
8632 + case BUS_NOTIFY_DEL_DEVICE:
8633 + case BUS_NOTIFY_REMOVED_DEVICE:
8634 + case BUS_NOTIFY_BIND_DRIVER:
8635 + case BUS_NOTIFY_BOUND_DRIVER:
8636 + case BUS_NOTIFY_UNBIND_DRIVER:
8637 + case BUS_NOTIFY_UNBOUND_DRIVER:
8638 + break;
8639 + default:
8640 + pr_err("%s: unrecognized device action from %s\n", __func__,
8641 + dev_name(dev));
8642 + return -EINVAL;
8643 + }
8644 +
8645 + return 0;
8646 +}
8647 +
8648 +static int add_to_restool(struct device *dev, void *data)
8649 +{
8650 + return restool_add_device_file(dev);
8651 +}
8652 +
8653 +static int __init fsl_mc_restool_driver_init(void)
8654 +{
8655 + int error;
8656 + struct notifier_block *nb;
8657 +
8658 + nb = kzalloc(sizeof(*nb), GFP_KERNEL);
8659 + if (!nb)
8660 + return -ENOMEM;
8661 +
8662 + nb->notifier_call = restool_bus_notifier;
8663 + error = bus_register_notifier(&fsl_mc_bus_type, nb);
8664 + if (error)
8665 + goto free_nb;
8666 +
8667 + /*
8668 + * This driver runs after fsl-mc bus driver runs.
8669 + * Hence, many of the root dprcs are already attached to fsl-mc bus
8670 + * In order to make sure we find all the root dprcs,
8671 + * we need to scan the fsl_mc_bus_type.
8672 + */
8673 + error = bus_for_each_dev(&fsl_mc_bus_type, NULL, NULL, add_to_restool);
8674 + if (error) {
8675 + bus_unregister_notifier(&fsl_mc_bus_type, nb);
8676 + kfree(nb);
8677 + pr_err("restool driver registration failure\n");
8678 + return error;
8679 + }
8680 +
8681 + return 0;
8682 +
8683 +free_nb:
8684 + kfree(nb);
8685 + return error;
8686 +}
8687 +
8688 +module_init(fsl_mc_restool_driver_init);
8689 +
8690 +static void __exit fsl_mc_restool_driver_exit(void)
8691 +{
8692 + struct restool_misc *restool_misc;
8693 + struct restool_misc *restool_misc_tmp;
8694 + char name1[20] = {0};
8695 + u32 name2 = 0;
8696 +
8697 + list_for_each_entry_safe(restool_misc, restool_misc_tmp,
8698 + &misc_list, list) {
8699 + if (sscanf(restool_misc->misc.name, "%4s.%u", name1, &name2)
8700 + != 2)
8701 + continue;
8702 +
8703 + pr_debug("name1=%s,name2=%u\n", name1, name2);
8704 + pr_debug("misc-device: %s\n", restool_misc->misc.name);
8705 + if (strcmp(name1, "dprc") != 0)
8706 + continue;
8707 +
8708 + if (WARN_ON(!restool_misc->static_mc_io))
8709 + return;
8710 +
8711 + if (WARN_ON(restool_misc->dynamic_instance_count != 0))
8712 + return;
8713 +
8714 + if (WARN_ON(restool_misc->static_instance_in_use))
8715 + return;
8716 +
8717 + misc_deregister(&restool_misc->misc);
8718 + pr_info("/dev/%s driver unregistered\n",
8719 + restool_misc->misc.name);
8720 + fsl_mc_portal_free(restool_misc->static_mc_io);
8721 + list_del(&restool_misc->list);
8722 + kfree(restool_misc);
8723 + }
8724 +}
8725 +
8726 +module_exit(fsl_mc_restool_driver_exit);
8727 +
8728 +MODULE_AUTHOR("Freescale Semiconductor Inc.");
8729 +MODULE_DESCRIPTION("Freescale's MC restool driver");
8730 +MODULE_LICENSE("GPL");
8731 --- a/drivers/staging/fsl-mc/bus/mc-sys.c
8732 +++ b/drivers/staging/fsl-mc/bus/mc-sys.c
8733 @@ -1,4 +1,5 @@
8734 -/* Copyright 2013-2014 Freescale Semiconductor Inc.
8735 +/*
8736 + * Copyright 2013-2016 Freescale Semiconductor Inc.
8737 *
8738 * I/O services to send MC commands to the MC hardware
8739 *
8740 @@ -13,7 +14,6 @@
8741 * names of any contributors may be used to endorse or promote products
8742 * derived from this software without specific prior written permission.
8743 *
8744 - *
8745 * ALTERNATIVELY, this software may be distributed under the terms of the
8746 * GNU General Public License ("GPL") as published by the Free Software
8747 * Foundation, either version 2 of that License or (at your option) any
8748 @@ -46,7 +46,7 @@
8749 /**
8750 * Timeout in milliseconds to wait for the completion of an MC command
8751 */
8752 -#define MC_CMD_COMPLETION_TIMEOUT_MS 500
8753 +#define MC_CMD_COMPLETION_TIMEOUT_MS 15000
8754  
8755 /*
8756 * usleep_range() min and max values used to throttle down polling
8757 @@ -67,7 +67,7 @@ static u16 mc_cmd_hdr_read_cmdid(struct
8758 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
8759 u16 cmd_id = le16_to_cpu(hdr->cmd_id);
8760  
8761 - return (cmd_id & MC_CMD_HDR_CMDID_MASK) >> MC_CMD_HDR_CMDID_SHIFT;
8762 + return cmd_id;
8763 }
8764  
8765 static int mc_status_to_error(enum mc_cmd_status status)
8766 @@ -200,7 +200,7 @@ static int mc_polling_wait_preemptible(s
8767  
8768 if (time_after_eq(jiffies, jiffies_until_timeout)) {
8769 dev_dbg(mc_io->dev,
8770 - "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n",
8771 + "MC command timed out (portal: %#llx, dprc handle: %#x, command: %#x)\n",
8772 mc_io->portal_phys_addr,
8773 (unsigned int)mc_cmd_hdr_read_token(cmd),
8774 (unsigned int)mc_cmd_hdr_read_cmdid(cmd));
8775 @@ -240,7 +240,7 @@ static int mc_polling_wait_atomic(struct
8776 timeout_usecs -= MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS;
8777 if (timeout_usecs == 0) {
8778 dev_dbg(mc_io->dev,
8779 - "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n",
8780 + "MC command timed out (portal: %#llx, dprc handle: %#x, command: %#x)\n",
8781 mc_io->portal_phys_addr,
8782 (unsigned int)mc_cmd_hdr_read_token(cmd),
8783 (unsigned int)mc_cmd_hdr_read_cmdid(cmd));
8784 @@ -294,7 +294,7 @@ int mc_send_command(struct fsl_mc_io *mc
8785  
8786 if (status != MC_CMD_STATUS_OK) {
8787 dev_dbg(mc_io->dev,
8788 - "MC command failed: portal: %#llx, obj handle: %#x, command: %#x, status: %s (%#x)\n",
8789 + "MC command failed: portal: %#llx, dprc handle: %#x, command: %#x, status: %s (%#x)\n",
8790 mc_io->portal_phys_addr,
8791 (unsigned int)mc_cmd_hdr_read_token(cmd),
8792 (unsigned int)mc_cmd_hdr_read_cmdid(cmd),
8793 --- /dev/null
8794 +++ b/drivers/staging/fsl-mc/include/dpaa2-fd.h
8795 @@ -0,0 +1,706 @@
8796 +/*
8797 + * Copyright 2014-2016 Freescale Semiconductor Inc.
8798 + * Copyright 2016 NXP
8799 + *
8800 + * Redistribution and use in source and binary forms, with or without
8801 + * modification, are permitted provided that the following conditions are met:
8802 + * * Redistributions of source code must retain the above copyright
8803 + * notice, this list of conditions and the following disclaimer.
8804 + * * Redistributions in binary form must reproduce the above copyright
8805 + * notice, this list of conditions and the following disclaimer in the
8806 + * documentation and/or other materials provided with the distribution.
8807 + * * Neither the name of Freescale Semiconductor nor the
8808 + * names of its contributors may be used to endorse or promote products
8809 + * derived from this software without specific prior written permission.
8810 + *
8811 + * ALTERNATIVELY, this software may be distributed under the terms of the
8812 + * GNU General Public License ("GPL") as published by the Free Software
8813 + * Foundation, either version 2 of that License or (at your option) any
8814 + * later version.
8815 + *
8816 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
8817 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
8818 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8819 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
8820 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
8821 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
8822 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
8823 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8824 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
8825 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8826 + */
8827 +#ifndef __FSL_DPAA2_FD_H
8828 +#define __FSL_DPAA2_FD_H
8829 +
8830 +#include <linux/kernel.h>
8831 +
8832 +/**
8833 + * DOC: DPAA2 FD - Frame Descriptor APIs for DPAA2
8834 + *
8835 + * Frame Descriptors (FDs) are used to describe frame data in the DPAA2.
8836 + * Frames can be enqueued and dequeued to Frame Queues (FQs) which are consumed
8837 + * by the various DPAA accelerators (WRIOP, SEC, PME, DCE)
8838 + *
8839 + * There are three types of frames: single, scatter gather, and frame lists.
8840 + *
8841 + * The set of APIs in this file must be used to create, manipulate and
8842 + * query Frame Descriptors.
8843 + */
8844 +
8845 +/**
8846 + * struct dpaa2_fd - Struct describing FDs
8847 + * @words: for easier/faster copying the whole FD structure
8848 + * @addr: address in the FD
8849 + * @len: length in the FD
8850 + * @bpid: buffer pool ID
8851 + * @format_offset: format, offset, and short-length fields
8852 + * @frc: frame context
8853 + * @ctrl: control bits...including dd, sc, va, err, etc
8854 + * @flc: flow context address
8855 + *
8856 + * This structure represents the basic Frame Descriptor used in the system.
8857 + */
8858 +struct dpaa2_fd {
8859 + union {
8860 + u32 words[8];
8861 + struct dpaa2_fd_simple {
8862 + __le64 addr;
8863 + __le32 len;
8864 + __le16 bpid;
8865 + __le16 format_offset;
8866 + __le32 frc;
8867 + __le32 ctrl;
8868 + __le64 flc;
8869 + } simple;
8870 + };
8871 +};
8872 +
8873 +#define FD_SHORT_LEN_FLAG_MASK 0x1
8874 +#define FD_SHORT_LEN_FLAG_SHIFT 14
8875 +#define FD_SHORT_LEN_MASK 0x3FFFF
8876 +#define FD_OFFSET_MASK 0x0FFF
8877 +#define FD_FORMAT_MASK 0x3
8878 +#define FD_FORMAT_SHIFT 12
8879 +#define FD_BPID_MASK 0x3FFF
8880 +#define SG_SHORT_LEN_FLAG_MASK 0x1
8881 +#define SG_SHORT_LEN_FLAG_SHIFT 14
8882 +#define SG_SHORT_LEN_MASK 0x1FFFF
8883 +#define SG_OFFSET_MASK 0x0FFF
8884 +#define SG_FORMAT_MASK 0x3
8885 +#define SG_FORMAT_SHIFT 12
8886 +#define SG_BPID_MASK 0x3FFF
8887 +#define SG_FINAL_FLAG_MASK 0x1
8888 +#define SG_FINAL_FLAG_SHIFT 15
8889 +#define FL_SHORT_LEN_FLAG_MASK 0x1
8890 +#define FL_SHORT_LEN_FLAG_SHIFT 14
8891 +#define FL_SHORT_LEN_MASK 0x3FFFF
8892 +#define FL_OFFSET_MASK 0x0FFF
8893 +#define FL_FORMAT_MASK 0x3
8894 +#define FL_FORMAT_SHIFT 12
8895 +#define FL_BPID_MASK 0x3FFF
8896 +#define FL_FINAL_FLAG_MASK 0x1
8897 +#define FL_FINAL_FLAG_SHIFT 15
8898 +
8899 +/* Error bits in FD CTRL */
8900 +#define FD_CTRL_ERR_MASK 0x000000FF
8901 +#define FD_CTRL_UFD 0x00000004
8902 +#define FD_CTRL_SBE 0x00000008
8903 +#define FD_CTRL_FLC 0x00000010
8904 +#define FD_CTRL_FSE 0x00000020
8905 +#define FD_CTRL_FAERR 0x00000040
8906 +
8907 +/* Annotation bits in FD CTRL */
8908 +#define FD_CTRL_PTA 0x00800000
8909 +#define FD_CTRL_PTV1 0x00400000
8910 +
8911 +enum dpaa2_fd_format {
8912 + dpaa2_fd_single = 0,
8913 + dpaa2_fd_list,
8914 + dpaa2_fd_sg
8915 +};
8916 +
8917 +/**
8918 + * dpaa2_fd_get_addr() - get the addr field of frame descriptor
8919 + * @fd: the given frame descriptor
8920 + *
8921 + * Return the address in the frame descriptor.
8922 + */
8923 +static inline dma_addr_t dpaa2_fd_get_addr(const struct dpaa2_fd *fd)
8924 +{
8925 + return (dma_addr_t)le64_to_cpu(fd->simple.addr);
8926 +}
8927 +
8928 +/**
8929 + * dpaa2_fd_set_addr() - Set the addr field of frame descriptor
8930 + * @fd: the given frame descriptor
8931 + * @addr: the address needs to be set in frame descriptor
8932 + */
8933 +static inline void dpaa2_fd_set_addr(struct dpaa2_fd *fd, dma_addr_t addr)
8934 +{
8935 + fd->simple.addr = cpu_to_le64(addr);
8936 +}
8937 +
8938 +/**
8939 + * dpaa2_fd_get_frc() - Get the frame context in the frame descriptor
8940 + * @fd: the given frame descriptor
8941 + *
8942 + * Return the frame context field in the frame descriptor.
8943 + */
8944 +static inline u32 dpaa2_fd_get_frc(const struct dpaa2_fd *fd)
8945 +{
8946 + return le32_to_cpu(fd->simple.frc);
8947 +}
8948 +
8949 +/**
8950 + * dpaa2_fd_set_frc() - Set the frame context in the frame descriptor
8951 + * @fd: the given frame descriptor
8952 + * @frc: the frame context needs to be set in frame descriptor
8953 + */
8954 +static inline void dpaa2_fd_set_frc(struct dpaa2_fd *fd, u32 frc)
8955 +{
8956 + fd->simple.frc = cpu_to_le32(frc);
8957 +}
8958 +
8959 +/**
8960 + * dpaa2_fd_get_ctrl() - Get the control bits in the frame descriptor
8961 + * @fd: the given frame descriptor
8962 + *
8963 + * Return the control bits field in the frame descriptor.
8964 + */
8965 +static inline u32 dpaa2_fd_get_ctrl(const struct dpaa2_fd *fd)
8966 +{
8967 + return le32_to_cpu(fd->simple.ctrl);
8968 +}
8969 +
8970 +/**
8971 + * dpaa2_fd_set_ctrl() - Set the control bits in the frame descriptor
8972 + * @fd: the given frame descriptor
8973 + * @ctrl: the control bits to be set in the frame descriptor
8974 + */
8975 +static inline void dpaa2_fd_set_ctrl(struct dpaa2_fd *fd, u32 ctrl)
8976 +{
8977 + fd->simple.ctrl = cpu_to_le32(ctrl);
8978 +}
8979 +
8980 +/**
8981 + * dpaa2_fd_get_flc() - Get the flow context in the frame descriptor
8982 + * @fd: the given frame descriptor
8983 + *
8984 + * Return the flow context in the frame descriptor.
8985 + */
8986 +static inline dma_addr_t dpaa2_fd_get_flc(const struct dpaa2_fd *fd)
8987 +{
8988 + return (dma_addr_t)le64_to_cpu(fd->simple.flc);
8989 +}
8990 +
8991 +/**
8992 + * dpaa2_fd_set_flc() - Set the flow context field of frame descriptor
8993 + * @fd: the given frame descriptor
8994 + * @flc_addr: the flow context needs to be set in frame descriptor
8995 + */
8996 +static inline void dpaa2_fd_set_flc(struct dpaa2_fd *fd, dma_addr_t flc_addr)
8997 +{
8998 + fd->simple.flc = cpu_to_le64(flc_addr);
8999 +}
9000 +
9001 +static inline bool dpaa2_fd_short_len(const struct dpaa2_fd *fd)
9002 +{
9003 + return !!((le16_to_cpu(fd->simple.format_offset) >>
9004 + FD_SHORT_LEN_FLAG_SHIFT) & FD_SHORT_LEN_FLAG_MASK);
9005 +}
9006 +
9007 +/**
9008 + * dpaa2_fd_get_len() - Get the length in the frame descriptor
9009 + * @fd: the given frame descriptor
9010 + *
9011 + * Return the length field in the frame descriptor.
9012 + */
9013 +static inline u32 dpaa2_fd_get_len(const struct dpaa2_fd *fd)
9014 +{
9015 + if (dpaa2_fd_short_len(fd))
9016 + return le32_to_cpu(fd->simple.len) & FD_SHORT_LEN_MASK;
9017 +
9018 + return le32_to_cpu(fd->simple.len);
9019 +}
9020 +
9021 +/**
9022 + * dpaa2_fd_set_len() - Set the length field of frame descriptor
9023 + * @fd: the given frame descriptor
9024 + * @len: the length needs to be set in frame descriptor
9025 + */
9026 +static inline void dpaa2_fd_set_len(struct dpaa2_fd *fd, u32 len)
9027 +{
9028 + fd->simple.len = cpu_to_le32(len);
9029 +}
9030 +
9031 +/**
9032 + * dpaa2_fd_get_offset() - Get the offset field in the frame descriptor
9033 + * @fd: the given frame descriptor
9034 + *
9035 + * Return the offset.
9036 + */
9037 +static inline uint16_t dpaa2_fd_get_offset(const struct dpaa2_fd *fd)
9038 +{
9039 + return le16_to_cpu(fd->simple.format_offset) & FD_OFFSET_MASK;
9040 +}
9041 +
9042 +/**
9043 + * dpaa2_fd_set_offset() - Set the offset field of frame descriptor
9044 + * @fd: the given frame descriptor
9045 + * @offset: the offset needs to be set in frame descriptor
9046 + */
9047 +static inline void dpaa2_fd_set_offset(struct dpaa2_fd *fd, uint16_t offset)
9048 +{
9049 + fd->simple.format_offset &= cpu_to_le16(~FD_OFFSET_MASK);
9050 + fd->simple.format_offset |= cpu_to_le16(offset);
9051 +}
9052 +
9053 +/**
9054 + * dpaa2_fd_get_format() - Get the format field in the frame descriptor
9055 + * @fd: the given frame descriptor
9056 + *
9057 + * Return the format.
9058 + */
9059 +static inline enum dpaa2_fd_format dpaa2_fd_get_format(
9060 + const struct dpaa2_fd *fd)
9061 +{
9062 + return (enum dpaa2_fd_format)((le16_to_cpu(fd->simple.format_offset)
9063 + >> FD_FORMAT_SHIFT) & FD_FORMAT_MASK);
9064 +}
9065 +
9066 +/**
9067 + * dpaa2_fd_set_format() - Set the format field of frame descriptor
9068 + * @fd: the given frame descriptor
9069 + * @format: the format needs to be set in frame descriptor
9070 + */
9071 +static inline void dpaa2_fd_set_format(struct dpaa2_fd *fd,
9072 + enum dpaa2_fd_format format)
9073 +{
9074 + fd->simple.format_offset &=
9075 + cpu_to_le16(~(FD_FORMAT_MASK << FD_FORMAT_SHIFT));
9076 + fd->simple.format_offset |= cpu_to_le16(format << FD_FORMAT_SHIFT);
9077 +}
9078 +
9079 +/**
9080 + * dpaa2_fd_get_bpid() - Get the bpid field in the frame descriptor
9081 + * @fd: the given frame descriptor
9082 + *
9083 + * Return the buffer pool id.
9084 + */
9085 +static inline uint16_t dpaa2_fd_get_bpid(const struct dpaa2_fd *fd)
9086 +{
9087 + return le16_to_cpu(fd->simple.bpid) & FD_BPID_MASK;
9088 +}
9089 +
9090 +/**
9091 + * dpaa2_fd_set_bpid() - Set the bpid field of frame descriptor
9092 + * @fd: the given frame descriptor
9093 + * @bpid: buffer pool id to be set
9094 + */
9095 +static inline void dpaa2_fd_set_bpid(struct dpaa2_fd *fd, uint16_t bpid)
9096 +{
9097 + fd->simple.bpid &= cpu_to_le16(~(FD_BPID_MASK));
9098 + fd->simple.bpid |= cpu_to_le16(bpid);
9099 +}
9100 +
9101 +/**
9102 + * struct dpaa2_sg_entry - the scatter-gathering structure
9103 + * @addr: address of the sg entry
9104 + * @len: length in this sg entry
9105 + * @bpid: buffer pool id
9106 + * @format_offset: format and offset fields
9107 + */
9108 +struct dpaa2_sg_entry {
9109 + __le64 addr;
9110 + __le32 len;
9111 + __le16 bpid;
9112 + __le16 format_offset;
9113 +};
9114 +
9115 +enum dpaa2_sg_format {
9116 + dpaa2_sg_single = 0,
9117 + dpaa2_sg_frame_data,
9118 + dpaa2_sg_sgt_ext
9119 +};
9120 +
9121 +/* Accessors for SG entry fields */
9122 +
9123 +/**
9124 + * dpaa2_sg_get_addr() - Get the address from SG entry
9125 + * @sg: the given scatter-gathering object
9126 + *
9127 + * Return the address.
9128 + */
9129 +static inline dma_addr_t dpaa2_sg_get_addr(const struct dpaa2_sg_entry *sg)
9130 +{
9131 + return le64_to_cpu((dma_addr_t)sg->addr);
9132 +}
9133 +
9134 +/**
9135 + * dpaa2_sg_set_addr() - Set the address in SG entry
9136 + * @sg: the given scatter-gathering object
9137 + * @addr: the address to be set
9138 + */
9139 +static inline void dpaa2_sg_set_addr(struct dpaa2_sg_entry *sg, dma_addr_t addr)
9140 +{
9141 + sg->addr = cpu_to_le64(addr);
9142 +}
9143 +
9144 +static inline bool dpaa2_sg_short_len(const struct dpaa2_sg_entry *sg)
9145 +{
9146 + return !!((le16_to_cpu(sg->format_offset) >> SG_SHORT_LEN_FLAG_SHIFT)
9147 + & SG_SHORT_LEN_FLAG_MASK);
9148 +}
9149 +
9150 +/**
9151 + * dpaa2_sg_get_len() - Get the length in SG entry
9152 + * @sg: the given scatter-gathering object
9153 + *
9154 + * Return the length.
9155 + */
9156 +static inline u32 dpaa2_sg_get_len(const struct dpaa2_sg_entry *sg)
9157 +{
9158 + if (dpaa2_sg_short_len(sg))
9159 + return le32_to_cpu(sg->len) & SG_SHORT_LEN_MASK;
9160 +
9161 + return le32_to_cpu(sg->len);
9162 +}
9163 +
9164 +/**
9165 + * dpaa2_sg_set_len() - Set the length in SG entry
9166 + * @sg: the given scatter-gathering object
9167 + * @len: the length to be set
9168 + */
9169 +static inline void dpaa2_sg_set_len(struct dpaa2_sg_entry *sg, u32 len)
9170 +{
9171 + sg->len = cpu_to_le32(len);
9172 +}
9173 +
9174 +/**
9175 + * dpaa2_sg_get_offset() - Get the offset in SG entry
9176 + * @sg: the given scatter-gathering object
9177 + *
9178 + * Return the offset.
9179 + */
9180 +static inline u16 dpaa2_sg_get_offset(const struct dpaa2_sg_entry *sg)
9181 +{
9182 + return le16_to_cpu(sg->format_offset) & SG_OFFSET_MASK;
9183 +}
9184 +
9185 +/**
9186 + * dpaa2_sg_set_offset() - Set the offset in SG entry
9187 + * @sg: the given scatter-gathering object
9188 + * @offset: the offset to be set
9189 + */
9190 +static inline void dpaa2_sg_set_offset(struct dpaa2_sg_entry *sg,
9191 + u16 offset)
9192 +{
9193 + sg->format_offset &= cpu_to_le16(~SG_OFFSET_MASK);
9194 + sg->format_offset |= cpu_to_le16(offset);
9195 +}
9196 +
9197 +/**
9198 + * dpaa2_sg_get_format() - Get the SG format in SG entry
9199 + * @sg: the given scatter-gathering object
9200 + *
9201 + * Return the format.
9202 + */
9203 +static inline enum dpaa2_sg_format
9204 + dpaa2_sg_get_format(const struct dpaa2_sg_entry *sg)
9205 +{
9206 + return (enum dpaa2_sg_format)((le16_to_cpu(sg->format_offset)
9207 + >> SG_FORMAT_SHIFT) & SG_FORMAT_MASK);
9208 +}
9209 +
9210 +/**
9211 + * dpaa2_sg_set_format() - Set the SG format in SG entry
9212 + * @sg: the given scatter-gathering object
9213 + * @format: the format to be set
9214 + */
9215 +static inline void dpaa2_sg_set_format(struct dpaa2_sg_entry *sg,
9216 + enum dpaa2_sg_format format)
9217 +{
9218 + sg->format_offset &= cpu_to_le16(~(SG_FORMAT_MASK << SG_FORMAT_SHIFT));
9219 + sg->format_offset |= cpu_to_le16(format << SG_FORMAT_SHIFT);
9220 +}
9221 +
9222 +/**
9223 + * dpaa2_sg_get_bpid() - Get the buffer pool id in SG entry
9224 + * @sg: the given scatter-gathering object
9225 + *
9226 + * Return the bpid.
9227 + */
9228 +static inline u16 dpaa2_sg_get_bpid(const struct dpaa2_sg_entry *sg)
9229 +{
9230 + return le16_to_cpu(sg->bpid) & SG_BPID_MASK;
9231 +}
9232 +
9233 +/**
9234 + * dpaa2_sg_set_bpid() - Set the buffer pool id in SG entry
9235 + * @sg: the given scatter-gathering object
9236 + * @bpid: the bpid to be set
9237 + */
9238 +static inline void dpaa2_sg_set_bpid(struct dpaa2_sg_entry *sg, u16 bpid)
9239 +{
9240 + sg->bpid &= cpu_to_le16(~(SG_BPID_MASK));
9241 + sg->bpid |= cpu_to_le16(bpid);
9242 +}
9243 +
9244 +/**
9245 + * dpaa2_sg_is_final() - Check final bit in SG entry
9246 + * @sg: the given scatter-gathering object
9247 + *
9248 + * Return bool.
9249 + */
9250 +static inline bool dpaa2_sg_is_final(const struct dpaa2_sg_entry *sg)
9251 +{
9252 + return !!(le16_to_cpu(sg->format_offset) >> SG_FINAL_FLAG_SHIFT);
9253 +}
9254 +
9255 +/**
9256 + * dpaa2_sg_set_final() - Set the final bit in SG entry
9257 + * @sg: the given scatter-gathering object
9258 + * @final: the final boolean to be set
9259 + */
9260 +static inline void dpaa2_sg_set_final(struct dpaa2_sg_entry *sg, bool final)
9261 +{
9262 + sg->format_offset &= cpu_to_le16(~(SG_FINAL_FLAG_MASK
9263 + << SG_FINAL_FLAG_SHIFT));
9264 + sg->format_offset |= cpu_to_le16(final << SG_FINAL_FLAG_SHIFT);
9265 +}
9266 +
9267 +/**
9268 + * struct dpaa2_fl_entry - structure for frame list entry.
9269 + * @addr: address in the FLE
9270 + * @len: length in the FLE
9271 + * @bpid: buffer pool ID
9272 + * @format_offset: format, offset, and short-length fields
9273 + * @frc: frame context
9274 + * @ctrl: control bits...including pta, pvt1, pvt2, err, etc
9275 + * @flc: flow context address
9276 + */
9277 +struct dpaa2_fl_entry {
9278 + __le64 addr;
9279 + __le32 len;
9280 + __le16 bpid;
9281 + __le16 format_offset;
9282 + __le32 frc;
9283 + __le32 ctrl;
9284 + __le64 flc;
9285 +};
9286 +
9287 +enum dpaa2_fl_format {
9288 + dpaa2_fl_single = 0,
9289 + dpaa2_fl_res,
9290 + dpaa2_fl_sg
9291 +};
9292 +
9293 +/**
9294 + * dpaa2_fl_get_addr() - get the addr field of FLE
9295 + * @fle: the given frame list entry
9296 + *
9297 + * Return the address in the frame list entry.
9298 + */
9299 +static inline dma_addr_t dpaa2_fl_get_addr(const struct dpaa2_fl_entry *fle)
9300 +{
9301 + return (dma_addr_t)le64_to_cpu(fle->addr);
9302 +}
9303 +
9304 +/**
9305 + * dpaa2_fl_set_addr() - Set the addr field of FLE
9306 + * @fle: the given frame list entry
9307 + * @addr: the address needs to be set in frame list entry
9308 + */
9309 +static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle,
9310 + dma_addr_t addr)
9311 +{
9312 + fle->addr = cpu_to_le64(addr);
9313 +}
9314 +
9315 +/**
9316 + * dpaa2_fl_get_frc() - Get the frame context in the FLE
9317 + * @fle: the given frame list entry
9318 + *
9319 + * Return the frame context field in the frame lsit entry.
9320 + */
9321 +static inline u32 dpaa2_fl_get_frc(const struct dpaa2_fl_entry *fle)
9322 +{
9323 + return le32_to_cpu(fle->frc);
9324 +}
9325 +
9326 +/**
9327 + * dpaa2_fl_set_frc() - Set the frame context in the FLE
9328 + * @fle: the given frame list entry
9329 + * @frc: the frame context needs to be set in frame list entry
9330 + */
9331 +static inline void dpaa2_fl_set_frc(struct dpaa2_fl_entry *fle, u32 frc)
9332 +{
9333 + fle->frc = cpu_to_le32(frc);
9334 +}
9335 +
9336 +/**
9337 + * dpaa2_fl_get_ctrl() - Get the control bits in the FLE
9338 + * @fle: the given frame list entry
9339 + *
9340 + * Return the control bits field in the frame list entry.
9341 + */
9342 +static inline u32 dpaa2_fl_get_ctrl(const struct dpaa2_fl_entry *fle)
9343 +{
9344 + return le32_to_cpu(fle->ctrl);
9345 +}
9346 +
9347 +/**
9348 + * dpaa2_fl_set_ctrl() - Set the control bits in the FLE
9349 + * @fle: the given frame list entry
9350 + * @ctrl: the control bits to be set in the frame list entry
9351 + */
9352 +static inline void dpaa2_fl_set_ctrl(struct dpaa2_fl_entry *fle, u32 ctrl)
9353 +{
9354 + fle->ctrl = cpu_to_le32(ctrl);
9355 +}
9356 +
9357 +/**
9358 + * dpaa2_fl_get_flc() - Get the flow context in the FLE
9359 + * @fle: the given frame list entry
9360 + *
9361 + * Return the flow context in the frame list entry.
9362 + */
9363 +static inline dma_addr_t dpaa2_fl_get_flc(const struct dpaa2_fl_entry *fle)
9364 +{
9365 + return (dma_addr_t)le64_to_cpu(fle->flc);
9366 +}
9367 +
9368 +/**
9369 + * dpaa2_fl_set_flc() - Set the flow context field of FLE
9370 + * @fle: the given frame list entry
9371 + * @flc_addr: the flow context needs to be set in frame list entry
9372 + */
9373 +static inline void dpaa2_fl_set_flc(struct dpaa2_fl_entry *fle,
9374 + dma_addr_t flc_addr)
9375 +{
9376 + fle->flc = cpu_to_le64(flc_addr);
9377 +}
9378 +
9379 +static inline bool dpaa2_fl_short_len(const struct dpaa2_fl_entry *fle)
9380 +{
9381 + return !!((le16_to_cpu(fle->format_offset) >>
9382 + FL_SHORT_LEN_FLAG_SHIFT) & FL_SHORT_LEN_FLAG_MASK);
9383 +}
9384 +
9385 +/**
9386 + * dpaa2_fl_get_len() - Get the length in the FLE
9387 + * @fle: the given frame list entry
9388 + *
9389 + * Return the length field in the frame list entry.
9390 + */
9391 +static inline u32 dpaa2_fl_get_len(const struct dpaa2_fl_entry *fle)
9392 +{
9393 + if (dpaa2_fl_short_len(fle))
9394 + return le32_to_cpu(fle->len) & FL_SHORT_LEN_MASK;
9395 +
9396 + return le32_to_cpu(fle->len);
9397 +}
9398 +
9399 +/**
9400 + * dpaa2_fl_set_len() - Set the length field of FLE
9401 + * @fle: the given frame list entry
9402 + * @len: the length needs to be set in frame list entry
9403 + */
9404 +static inline void dpaa2_fl_set_len(struct dpaa2_fl_entry *fle, u32 len)
9405 +{
9406 + fle->len = cpu_to_le32(len);
9407 +}
9408 +
9409 +/**
9410 + * dpaa2_fl_get_offset() - Get the offset field in the frame list entry
9411 + * @fle: the given frame list entry
9412 + *
9413 + * Return the offset.
9414 + */
9415 +static inline u16 dpaa2_fl_get_offset(const struct dpaa2_fl_entry *fle)
9416 +{
9417 + return le16_to_cpu(fle->format_offset) & FL_OFFSET_MASK;
9418 +}
9419 +
9420 +/**
9421 + * dpaa2_fl_set_offset() - Set the offset field of FLE
9422 + * @fle: the given frame list entry
9423 + * @offset: the offset needs to be set in frame list entry
9424 + */
9425 +static inline void dpaa2_fl_set_offset(struct dpaa2_fl_entry *fle, u16 offset)
9426 +{
9427 + fle->format_offset &= cpu_to_le16(~FL_OFFSET_MASK);
9428 + fle->format_offset |= cpu_to_le16(offset);
9429 +}
9430 +
9431 +/**
9432 + * dpaa2_fl_get_format() - Get the format field in the FLE
9433 + * @fle: the given frame list entry
9434 + *
9435 + * Return the format.
9436 + */
9437 +static inline enum dpaa2_fl_format dpaa2_fl_get_format(
9438 + const struct dpaa2_fl_entry *fle)
9439 +{
9440 + return (enum dpaa2_fl_format)((le16_to_cpu(fle->format_offset) >>
9441 + FL_FORMAT_SHIFT) & FL_FORMAT_MASK);
9442 +}
9443 +
9444 +/**
9445 + * dpaa2_fl_set_format() - Set the format field of FLE
9446 + * @fle: the given frame list entry
9447 + * @format: the format needs to be set in frame list entry
9448 + */
9449 +static inline void dpaa2_fl_set_format(struct dpaa2_fl_entry *fle,
9450 + enum dpaa2_fl_format format)
9451 +{
9452 + fle->format_offset &= cpu_to_le16(~(FL_FORMAT_MASK << FL_FORMAT_SHIFT));
9453 + fle->format_offset |= cpu_to_le16(format << FL_FORMAT_SHIFT);
9454 +}
9455 +
9456 +/**
9457 + * dpaa2_fl_get_bpid() - Get the bpid field in the FLE
9458 + * @fle: the given frame list entry
9459 + *
9460 + * Return the buffer pool id.
9461 + */
9462 +static inline u16 dpaa2_fl_get_bpid(const struct dpaa2_fl_entry *fle)
9463 +{
9464 + return le16_to_cpu(fle->bpid) & FL_BPID_MASK;
9465 +}
9466 +
9467 +/**
9468 + * dpaa2_fl_set_bpid() - Set the bpid field of FLE
9469 + * @fle: the given frame list entry
9470 + * @bpid: buffer pool id to be set
9471 + */
9472 +static inline void dpaa2_fl_set_bpid(struct dpaa2_fl_entry *fle, u16 bpid)
9473 +{
9474 + fle->bpid &= cpu_to_le16(~(FL_BPID_MASK));
9475 + fle->bpid |= cpu_to_le16(bpid);
9476 +}
9477 +
9478 +/**
9479 + * dpaa2_fl_is_final() - Check final bit in FLE
9480 + * @fle: the given frame list entry
9481 + *
9482 + * Return bool.
9483 + */
9484 +static inline bool dpaa2_fl_is_final(const struct dpaa2_fl_entry *fle)
9485 +{
9486 + return !!(le16_to_cpu(fle->format_offset) >> FL_FINAL_FLAG_SHIFT);
9487 +}
9488 +
9489 +/**
9490 + * dpaa2_fl_set_final() - Set the final bit in FLE
9491 + * @fle: the given frame list entry
9492 + * @final: the final boolean to be set
9493 + */
9494 +static inline void dpaa2_fl_set_final(struct dpaa2_fl_entry *fle, bool final)
9495 +{
9496 + fle->format_offset &= cpu_to_le16(~(FL_FINAL_FLAG_MASK <<
9497 + FL_FINAL_FLAG_SHIFT));
9498 + fle->format_offset |= cpu_to_le16(final << FL_FINAL_FLAG_SHIFT);
9499 +}
9500 +
9501 +#endif /* __FSL_DPAA2_FD_H */
9502 --- /dev/null
9503 +++ b/drivers/staging/fsl-mc/include/dpaa2-global.h
9504 @@ -0,0 +1,202 @@
9505 +/*
9506 + * Copyright 2014-2016 Freescale Semiconductor Inc.
9507 + * Copyright 2016 NXP
9508 + *
9509 + * Redistribution and use in source and binary forms, with or without
9510 + * modification, are permitted provided that the following conditions are met:
9511 + * * Redistributions of source code must retain the above copyright
9512 + * notice, this list of conditions and the following disclaimer.
9513 + * * Redistributions in binary form must reproduce the above copyright
9514 + * notice, this list of conditions and the following disclaimer in the
9515 + * documentation and/or other materials provided with the distribution.
9516 + * * Neither the name of Freescale Semiconductor nor the
9517 + * names of its contributors may be used to endorse or promote products
9518 + * derived from this software without specific prior written permission.
9519 + *
9520 + * ALTERNATIVELY, this software may be distributed under the terms of the
9521 + * GNU General Public License ("GPL") as published by the Free Software
9522 + * Foundation, either version 2 of that License or (at your option) any
9523 + * later version.
9524 + *
9525 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9526 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9527 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9528 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9529 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9530 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9531 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9532 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9533 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9534 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9535 + */
9536 +#ifndef __FSL_DPAA2_GLOBAL_H
9537 +#define __FSL_DPAA2_GLOBAL_H
9538 +
9539 +#include <linux/types.h>
9540 +#include <linux/cpumask.h>
9541 +#include "dpaa2-fd.h"
9542 +
9543 +struct dpaa2_dq {
9544 + union {
9545 + struct common {
9546 + u8 verb;
9547 + u8 reserved[63];
9548 + } common;
9549 + struct dq {
9550 + u8 verb;
9551 + u8 stat;
9552 + __le16 seqnum;
9553 + __le16 oprid;
9554 + u8 reserved;
9555 + u8 tok;
9556 + __le32 fqid;
9557 + u32 reserved2;
9558 + __le32 fq_byte_cnt;
9559 + __le32 fq_frm_cnt;
9560 + __le64 fqd_ctx;
9561 + u8 fd[32];
9562 + } dq;
9563 + struct scn {
9564 + u8 verb;
9565 + u8 stat;
9566 + u8 state;
9567 + u8 reserved;
9568 + __le32 rid_tok;
9569 + __le64 ctx;
9570 + } scn;
9571 + };
9572 +};
9573 +
9574 +/* Parsing frame dequeue results */
9575 +/* FQ empty */
9576 +#define DPAA2_DQ_STAT_FQEMPTY 0x80
9577 +/* FQ held active */
9578 +#define DPAA2_DQ_STAT_HELDACTIVE 0x40
9579 +/* FQ force eligible */
9580 +#define DPAA2_DQ_STAT_FORCEELIGIBLE 0x20
9581 +/* valid frame */
9582 +#define DPAA2_DQ_STAT_VALIDFRAME 0x10
9583 +/* FQ ODP enable */
9584 +#define DPAA2_DQ_STAT_ODPVALID 0x04
9585 +/* volatile dequeue */
9586 +#define DPAA2_DQ_STAT_VOLATILE 0x02
9587 +/* volatile dequeue command is expired */
9588 +#define DPAA2_DQ_STAT_EXPIRED 0x01
9589 +
9590 +#define DQ_FQID_MASK 0x00FFFFFF
9591 +#define DQ_FRAME_COUNT_MASK 0x00FFFFFF
9592 +
9593 +/**
9594 + * dpaa2_dq_flags() - Get the stat field of dequeue response
9595 + * @dq: the dequeue result.
9596 + */
9597 +static inline u32 dpaa2_dq_flags(const struct dpaa2_dq *dq)
9598 +{
9599 + return dq->dq.stat;
9600 +}
9601 +
9602 +/**
9603 + * dpaa2_dq_is_pull() - Check whether the dq response is from a pull
9604 + * command.
9605 + * @dq: the dequeue result
9606 + *
9607 + * Return 1 for volatile(pull) dequeue, 0 for static dequeue.
9608 + */
9609 +static inline int dpaa2_dq_is_pull(const struct dpaa2_dq *dq)
9610 +{
9611 + return (int)(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_VOLATILE);
9612 +}
9613 +
9614 +/**
9615 + * dpaa2_dq_is_pull_complete() - Check whether the pull command is completed.
9616 + * @dq: the dequeue result
9617 + *
9618 + * Return boolean.
9619 + */
9620 +static inline bool dpaa2_dq_is_pull_complete(const struct dpaa2_dq *dq)
9621 +{
9622 + return !!(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_EXPIRED);
9623 +}
9624 +
9625 +/**
9626 + * dpaa2_dq_seqnum() - Get the seqnum field in dequeue response
9627 + * @dq: the dequeue result
9628 + *
9629 + * seqnum is valid only if VALIDFRAME flag is TRUE
9630 + *
9631 + * Return seqnum.
9632 + */
9633 +static inline u16 dpaa2_dq_seqnum(const struct dpaa2_dq *dq)
9634 +{
9635 + return le16_to_cpu(dq->dq.seqnum);
9636 +}
9637 +
9638 +/**
9639 + * dpaa2_dq_odpid() - Get the odpid field in dequeue response
9640 + * @dq: the dequeue result
9641 + *
9642 + * odpid is valid only if ODPVALID flag is TRUE.
9643 + *
9644 + * Return odpid.
9645 + */
9646 +static inline u16 dpaa2_dq_odpid(const struct dpaa2_dq *dq)
9647 +{
9648 + return le16_to_cpu(dq->dq.oprid);
9649 +}
9650 +
9651 +/**
9652 + * dpaa2_dq_fqid() - Get the fqid in dequeue response
9653 + * @dq: the dequeue result
9654 + *
9655 + * Return fqid.
9656 + */
9657 +static inline u32 dpaa2_dq_fqid(const struct dpaa2_dq *dq)
9658 +{
9659 + return le32_to_cpu(dq->dq.fqid) & DQ_FQID_MASK;
9660 +}
9661 +
9662 +/**
9663 + * dpaa2_dq_byte_count() - Get the byte count in dequeue response
9664 + * @dq: the dequeue result
9665 + *
9666 + * Return the byte count remaining in the FQ.
9667 + */
9668 +static inline u32 dpaa2_dq_byte_count(const struct dpaa2_dq *dq)
9669 +{
9670 + return le32_to_cpu(dq->dq.fq_byte_cnt);
9671 +}
9672 +
9673 +/**
9674 + * dpaa2_dq_frame_count() - Get the frame count in dequeue response
9675 + * @dq: the dequeue result
9676 + *
9677 + * Return the frame count remaining in the FQ.
9678 + */
9679 +static inline u32 dpaa2_dq_frame_count(const struct dpaa2_dq *dq)
9680 +{
9681 + return le32_to_cpu(dq->dq.fq_frm_cnt) & DQ_FRAME_COUNT_MASK;
9682 +}
9683 +
9684 +/**
9685 + * dpaa2_dq_fd_ctx() - Get the frame queue context in dequeue response
9686 + * @dq: the dequeue result
9687 + *
9688 + * Return the frame queue context.
9689 + */
9690 +static inline u64 dpaa2_dq_fqd_ctx(const struct dpaa2_dq *dq)
9691 +{
9692 + return le64_to_cpu(dq->dq.fqd_ctx);
9693 +}
9694 +
9695 +/**
9696 + * dpaa2_dq_fd() - Get the frame descriptor in dequeue response
9697 + * @dq: the dequeue result
9698 + *
9699 + * Return the frame descriptor.
9700 + */
9701 +static inline const struct dpaa2_fd *dpaa2_dq_fd(const struct dpaa2_dq *dq)
9702 +{
9703 + return (const struct dpaa2_fd *)&dq->dq.fd[0];
9704 +}
9705 +
9706 +#endif /* __FSL_DPAA2_GLOBAL_H */
9707 --- /dev/null
9708 +++ b/drivers/staging/fsl-mc/include/dpaa2-io.h
9709 @@ -0,0 +1,190 @@
9710 +/*
9711 + * Copyright 2014-2016 Freescale Semiconductor Inc.
9712 + * Copyright 2017 NXP
9713 + *
9714 + * Redistribution and use in source and binary forms, with or without
9715 + * modification, are permitted provided that the following conditions are met:
9716 + * * Redistributions of source code must retain the above copyright
9717 + * notice, this list of conditions and the following disclaimer.
9718 + * * Redistributions in binary form must reproduce the above copyright
9719 + * notice, this list of conditions and the following disclaimer in the
9720 + * documentation and/or other materials provided with the distribution.
9721 + * * Neither the name of Freescale Semiconductor nor the
9722 + * names of its contributors may be used to endorse or promote products
9723 + * derived from this software without specific prior written permission.
9724 + *
9725 + * ALTERNATIVELY, this software may be distributed under the terms of the
9726 + * GNU General Public License ("GPL") as published by the Free Software
9727 + * Foundation, either version 2 of that License or (at your option) any
9728 + * later version.
9729 + *
9730 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9731 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9732 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9733 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9734 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9735 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9736 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9737 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9738 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9739 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9740 + */
9741 +#ifndef __FSL_DPAA2_IO_H
9742 +#define __FSL_DPAA2_IO_H
9743 +
9744 +#include <linux/types.h>
9745 +#include <linux/cpumask.h>
9746 +
9747 +#include "dpaa2-fd.h"
9748 +#include "dpaa2-global.h"
9749 +
9750 +struct dpaa2_io;
9751 +struct dpaa2_io_store;
9752 +struct device;
9753 +
9754 +/**
9755 + * DOC: DPIO Service
9756 + *
9757 + * The DPIO service provides APIs for users to interact with the datapath
9758 + * by enqueueing and dequeing frame descriptors.
9759 + *
9760 + * The following set of APIs can be used to enqueue and dequeue frames
9761 + * as well as producing notification callbacks when data is available
9762 + * for dequeue.
9763 + */
9764 +
9765 +/**
9766 + * struct dpaa2_io_desc - The DPIO descriptor
9767 + * @receives_notifications: Use notificaton mode. Non-zero if the DPIO
9768 + * has a channel.
9769 + * @has_8prio: Set to non-zero for channel with 8 priority WQs. Ignored
9770 + * unless receives_notification is TRUE.
9771 + * @cpu: The cpu index that at least interrupt handlers will
9772 + * execute on.
9773 + * @stash_affinity: The stash affinity for this portal favour 'cpu'
9774 + * @regs_cena: The cache enabled regs.
9775 + * @regs_cinh: The cache inhibited regs
9776 + * @dpio_id: The dpio index
9777 + * @qman_version: The qman version
9778 + *
9779 + * Describes the attributes and features of the DPIO object.
9780 + */
9781 +struct dpaa2_io_desc {
9782 + int receives_notifications;
9783 + int has_8prio;
9784 + int cpu;
9785 + void *regs_cena;
9786 + void *regs_cinh;
9787 + int dpio_id;
9788 + u32 qman_version;
9789 +};
9790 +
9791 +struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc);
9792 +
9793 +void dpaa2_io_down(struct dpaa2_io *d);
9794 +
9795 +irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj);
9796 +
9797 +/**
9798 + * struct dpaa2_io_notification_ctx - The DPIO notification context structure
9799 + * @cb: The callback to be invoked when the notification arrives
9800 + * @is_cdan: Zero for FQDAN, non-zero for CDAN
9801 + * @id: FQID or channel ID, needed for rearm
9802 + * @desired_cpu: The cpu on which the notifications will show up. -1 means
9803 + * any CPU.
9804 + * @dpio_id: The dpio index
9805 + * @qman64: The 64-bit context value shows up in the FQDAN/CDAN.
9806 + * @node: The list node
9807 + * @dpio_private: The dpio object internal to dpio_service
9808 + *
9809 + * Used when a FQDAN/CDAN registration is made by drivers.
9810 + */
9811 +struct dpaa2_io_notification_ctx {
9812 + void (*cb)(struct dpaa2_io_notification_ctx *);
9813 + int is_cdan;
9814 + u32 id;
9815 + int desired_cpu;
9816 + int dpio_id;
9817 + u64 qman64;
9818 + struct list_head node;
9819 + void *dpio_private;
9820 +};
9821 +
9822 +int dpaa2_io_service_register(struct dpaa2_io *service,
9823 + struct dpaa2_io_notification_ctx *ctx);
9824 +void dpaa2_io_service_deregister(struct dpaa2_io *service,
9825 + struct dpaa2_io_notification_ctx *ctx);
9826 +int dpaa2_io_service_rearm(struct dpaa2_io *service,
9827 + struct dpaa2_io_notification_ctx *ctx);
9828 +
9829 +int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
9830 + struct dpaa2_io_store *s);
9831 +int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
9832 + struct dpaa2_io_store *s);
9833 +
9834 +int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d, u32 fqid,
9835 + const struct dpaa2_fd *fd);
9836 +int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
9837 + u16 qdbin, const struct dpaa2_fd *fd);
9838 +int dpaa2_io_service_release(struct dpaa2_io *d, u32 bpid,
9839 + const u64 *buffers, unsigned int num_buffers);
9840 +int dpaa2_io_service_acquire(struct dpaa2_io *d, u32 bpid,
9841 + u64 *buffers, unsigned int num_buffers);
9842 +
9843 +struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
9844 + struct device *dev);
9845 +void dpaa2_io_store_destroy(struct dpaa2_io_store *s);
9846 +struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last);
9847 +
9848 +#ifdef CONFIG_FSL_QBMAN_DEBUG
9849 +int dpaa2_io_query_fq_count(struct dpaa2_io *d, uint32_t fqid,
9850 + uint32_t *fcnt, uint32_t *bcnt);
9851 +int dpaa2_io_query_bp_count(struct dpaa2_io *d, uint32_t bpid,
9852 + uint32_t *num);
9853 +#endif
9854 +
9855 +
9856 +/***************/
9857 +/* CSCN */
9858 +/***************/
9859 +
9860 +/**
9861 + * struct dpaa2_cscn - The CSCN message format
9862 + * @verb: identifies the type of message (should be 0x27).
9863 + * @stat: status bits related to dequeuing response (not used)
9864 + * @state: bit 0 = 0/1 if CG is no/is congested
9865 + * @reserved: reserved byte
9866 + * @cgid: congest grp ID - the first 16 bits
9867 + * @ctx: context data
9868 + *
9869 + * Congestion management can be implemented in software through
9870 + * the use of Congestion State Change Notifications (CSCN). These
9871 + * are messages written by DPAA2 hardware to memory whenever the
9872 + * instantaneous count (I_CNT field in the CG) exceeds the
9873 + * Congestion State (CS) entrance threshold, signifying congestion
9874 + * entrance, or when the instantaneous count returns below exit
9875 + * threshold, signifying congestion exit. The format of the message
9876 + * is given by the dpaa2_cscn structure. Bit 0 of the state field
9877 + * represents congestion state written by the hardware.
9878 + */
9879 +struct dpaa2_cscn {
9880 + u8 verb;
9881 + u8 stat;
9882 + u8 state;
9883 + u8 reserved;
9884 + __le32 cgid;
9885 + __le64 ctx;
9886 +};
9887 +
9888 +#define DPAA2_CSCN_SIZE 64
9889 +#define DPAA2_CSCN_ALIGN 16
9890 +
9891 +#define DPAA2_CSCN_STATE_MASK 0x1
9892 +#define DPAA2_CSCN_CONGESTED 1
9893 +
9894 +static inline bool dpaa2_cscn_state_congested(struct dpaa2_cscn *cscn)
9895 +{
9896 + return ((cscn->state & DPAA2_CSCN_STATE_MASK) == DPAA2_CSCN_CONGESTED);
9897 +}
9898 +
9899 +#endif /* __FSL_DPAA2_IO_H */
9900 --- a/drivers/staging/fsl-mc/include/dpbp-cmd.h
9901 +++ /dev/null
9902 @@ -1,185 +0,0 @@
9903 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
9904 - *
9905 - * Redistribution and use in source and binary forms, with or without
9906 - * modification, are permitted provided that the following conditions are met:
9907 - * * Redistributions of source code must retain the above copyright
9908 - * notice, this list of conditions and the following disclaimer.
9909 - * * Redistributions in binary form must reproduce the above copyright
9910 - * notice, this list of conditions and the following disclaimer in the
9911 - * documentation and/or other materials provided with the distribution.
9912 - * * Neither the name of the above-listed copyright holders nor the
9913 - * names of any contributors may be used to endorse or promote products
9914 - * derived from this software without specific prior written permission.
9915 - *
9916 - *
9917 - * ALTERNATIVELY, this software may be distributed under the terms of the
9918 - * GNU General Public License ("GPL") as published by the Free Software
9919 - * Foundation, either version 2 of that License or (at your option) any
9920 - * later version.
9921 - *
9922 - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
9923 - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
9924 - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9925 - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
9926 - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
9927 - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
9928 - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
9929 - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
9930 - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
9931 - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
9932 - * POSSIBILITY OF SUCH DAMAGE.
9933 - */
9934 -#ifndef _FSL_DPBP_CMD_H
9935 -#define _FSL_DPBP_CMD_H
9936 -
9937 -/* DPBP Version */
9938 -#define DPBP_VER_MAJOR 2
9939 -#define DPBP_VER_MINOR 2
9940 -
9941 -/* Command IDs */
9942 -#define DPBP_CMDID_CLOSE 0x800
9943 -#define DPBP_CMDID_OPEN 0x804
9944 -#define DPBP_CMDID_CREATE 0x904
9945 -#define DPBP_CMDID_DESTROY 0x900
9946 -
9947 -#define DPBP_CMDID_ENABLE 0x002
9948 -#define DPBP_CMDID_DISABLE 0x003
9949 -#define DPBP_CMDID_GET_ATTR 0x004
9950 -#define DPBP_CMDID_RESET 0x005
9951 -#define DPBP_CMDID_IS_ENABLED 0x006
9952 -
9953 -#define DPBP_CMDID_SET_IRQ 0x010
9954 -#define DPBP_CMDID_GET_IRQ 0x011
9955 -#define DPBP_CMDID_SET_IRQ_ENABLE 0x012
9956 -#define DPBP_CMDID_GET_IRQ_ENABLE 0x013
9957 -#define DPBP_CMDID_SET_IRQ_MASK 0x014
9958 -#define DPBP_CMDID_GET_IRQ_MASK 0x015
9959 -#define DPBP_CMDID_GET_IRQ_STATUS 0x016
9960 -#define DPBP_CMDID_CLEAR_IRQ_STATUS 0x017
9961 -
9962 -#define DPBP_CMDID_SET_NOTIFICATIONS 0x01b0
9963 -#define DPBP_CMDID_GET_NOTIFICATIONS 0x01b1
9964 -
9965 -struct dpbp_cmd_open {
9966 - __le32 dpbp_id;
9967 -};
9968 -
9969 -#define DPBP_ENABLE 0x1
9970 -
9971 -struct dpbp_rsp_is_enabled {
9972 - u8 enabled;
9973 -};
9974 -
9975 -struct dpbp_cmd_set_irq {
9976 - /* cmd word 0 */
9977 - u8 irq_index;
9978 - u8 pad[3];
9979 - __le32 irq_val;
9980 - /* cmd word 1 */
9981 - __le64 irq_addr;
9982 - /* cmd word 2 */
9983 - __le32 irq_num;
9984 -};
9985 -
9986 -struct dpbp_cmd_get_irq {
9987 - __le32 pad;
9988 - u8 irq_index;
9989 -};
9990 -
9991 -struct dpbp_rsp_get_irq {
9992 - /* response word 0 */
9993 - __le32 irq_val;
9994 - __le32 pad;
9995 - /* response word 1 */
9996 - __le64 irq_addr;
9997 - /* response word 2 */
9998 - __le32 irq_num;
9999 - __le32 type;
10000 -};
10001 -
10002 -struct dpbp_cmd_set_irq_enable {
10003 - u8 enable;
10004 - u8 pad[3];
10005 - u8 irq_index;
10006 -};
10007 -
10008 -struct dpbp_cmd_get_irq_enable {
10009 - __le32 pad;
10010 - u8 irq_index;
10011 -};
10012 -
10013 -struct dpbp_rsp_get_irq_enable {
10014 - u8 enabled;
10015 -};
10016 -
10017 -struct dpbp_cmd_set_irq_mask {
10018 - __le32 mask;
10019 - u8 irq_index;
10020 -};
10021 -
10022 -struct dpbp_cmd_get_irq_mask {
10023 - __le32 pad;
10024 - u8 irq_index;
10025 -};
10026 -
10027 -struct dpbp_rsp_get_irq_mask {
10028 - __le32 mask;
10029 -};
10030 -
10031 -struct dpbp_cmd_get_irq_status {
10032 - __le32 status;
10033 - u8 irq_index;
10034 -};
10035 -
10036 -struct dpbp_rsp_get_irq_status {
10037 - __le32 status;
10038 -};
10039 -
10040 -struct dpbp_cmd_clear_irq_status {
10041 - __le32 status;
10042 - u8 irq_index;
10043 -};
10044 -
10045 -struct dpbp_rsp_get_attributes {
10046 - /* response word 0 */
10047 - __le16 pad;
10048 - __le16 bpid;
10049 - __le32 id;
10050 - /* response word 1 */
10051 - __le16 version_major;
10052 - __le16 version_minor;
10053 -};
10054 -
10055 -struct dpbp_cmd_set_notifications {
10056 - /* cmd word 0 */
10057 - __le32 depletion_entry;
10058 - __le32 depletion_exit;
10059 - /* cmd word 1 */
10060 - __le32 surplus_entry;
10061 - __le32 surplus_exit;
10062 - /* cmd word 2 */
10063 - __le16 options;
10064 - __le16 pad[3];
10065 - /* cmd word 3 */
10066 - __le64 message_ctx;
10067 - /* cmd word 4 */
10068 - __le64 message_iova;
10069 -};
10070 -
10071 -struct dpbp_rsp_get_notifications {
10072 - /* response word 0 */
10073 - __le32 depletion_entry;
10074 - __le32 depletion_exit;
10075 - /* response word 1 */
10076 - __le32 surplus_entry;
10077 - __le32 surplus_exit;
10078 - /* response word 2 */
10079 - __le16 options;
10080 - __le16 pad[3];
10081 - /* response word 3 */
10082 - __le64 message_ctx;
10083 - /* response word 4 */
10084 - __le64 message_iova;
10085 -};
10086 -
10087 -#endif /* _FSL_DPBP_CMD_H */
10088 --- a/drivers/staging/fsl-mc/include/dpbp.h
10089 +++ b/drivers/staging/fsl-mc/include/dpbp.h
10090 @@ -1,4 +1,5 @@
10091 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10092 +/*
10093 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10094 *
10095 * Redistribution and use in source and binary forms, with or without
10096 * modification, are permitted provided that the following conditions are met:
10097 @@ -32,7 +33,8 @@
10098 #ifndef __FSL_DPBP_H
10099 #define __FSL_DPBP_H
10100  
10101 -/* Data Path Buffer Pool API
10102 +/*
10103 + * Data Path Buffer Pool API
10104 * Contains initialization APIs and runtime control APIs for DPBP
10105 */
10106  
10107 @@ -44,25 +46,8 @@ int dpbp_open(struct fsl_mc_io *mc_io,
10108 u16 *token);
10109  
10110 int dpbp_close(struct fsl_mc_io *mc_io,
10111 - u32 cmd_flags,
10112 - u16 token);
10113 -
10114 -/**
10115 - * struct dpbp_cfg - Structure representing DPBP configuration
10116 - * @options: place holder
10117 - */
10118 -struct dpbp_cfg {
10119 - u32 options;
10120 -};
10121 -
10122 -int dpbp_create(struct fsl_mc_io *mc_io,
10123 - u32 cmd_flags,
10124 - const struct dpbp_cfg *cfg,
10125 - u16 *token);
10126 -
10127 -int dpbp_destroy(struct fsl_mc_io *mc_io,
10128 - u32 cmd_flags,
10129 - u16 token);
10130 + u32 cmd_flags,
10131 + u16 token);
10132  
10133 int dpbp_enable(struct fsl_mc_io *mc_io,
10134 u32 cmd_flags,
10135 @@ -82,139 +67,24 @@ int dpbp_reset(struct fsl_mc_io *mc_io,
10136 u16 token);
10137  
10138 /**
10139 - * struct dpbp_irq_cfg - IRQ configuration
10140 - * @addr: Address that must be written to signal a message-based interrupt
10141 - * @val: Value to write into irq_addr address
10142 - * @irq_num: A user defined number associated with this IRQ
10143 - */
10144 -struct dpbp_irq_cfg {
10145 - u64 addr;
10146 - u32 val;
10147 - int irq_num;
10148 -};
10149 -
10150 -int dpbp_set_irq(struct fsl_mc_io *mc_io,
10151 - u32 cmd_flags,
10152 - u16 token,
10153 - u8 irq_index,
10154 - struct dpbp_irq_cfg *irq_cfg);
10155 -
10156 -int dpbp_get_irq(struct fsl_mc_io *mc_io,
10157 - u32 cmd_flags,
10158 - u16 token,
10159 - u8 irq_index,
10160 - int *type,
10161 - struct dpbp_irq_cfg *irq_cfg);
10162 -
10163 -int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
10164 - u32 cmd_flags,
10165 - u16 token,
10166 - u8 irq_index,
10167 - u8 en);
10168 -
10169 -int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
10170 - u32 cmd_flags,
10171 - u16 token,
10172 - u8 irq_index,
10173 - u8 *en);
10174 -
10175 -int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
10176 - u32 cmd_flags,
10177 - u16 token,
10178 - u8 irq_index,
10179 - u32 mask);
10180 -
10181 -int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
10182 - u32 cmd_flags,
10183 - u16 token,
10184 - u8 irq_index,
10185 - u32 *mask);
10186 -
10187 -int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
10188 - u32 cmd_flags,
10189 - u16 token,
10190 - u8 irq_index,
10191 - u32 *status);
10192 -
10193 -int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
10194 - u32 cmd_flags,
10195 - u16 token,
10196 - u8 irq_index,
10197 - u32 status);
10198 -
10199 -/**
10200 * struct dpbp_attr - Structure representing DPBP attributes
10201 * @id: DPBP object ID
10202 - * @version: DPBP version
10203 * @bpid: Hardware buffer pool ID; should be used as an argument in
10204 * acquire/release operations on buffers
10205 */
10206 struct dpbp_attr {
10207 int id;
10208 - /**
10209 - * struct version - Structure representing DPBP version
10210 - * @major: DPBP major version
10211 - * @minor: DPBP minor version
10212 - */
10213 - struct {
10214 - u16 major;
10215 - u16 minor;
10216 - } version;
10217 u16 bpid;
10218 };
10219  
10220 -int dpbp_get_attributes(struct fsl_mc_io *mc_io,
10221 - u32 cmd_flags,
10222 - u16 token,
10223 - struct dpbp_attr *attr);
10224 -
10225 -/**
10226 - * DPBP notifications options
10227 - */
10228 -
10229 -/**
10230 - * BPSCN write will attempt to allocate into a cache (coherent write)
10231 - */
10232 -#define DPBP_NOTIF_OPT_COHERENT_WRITE 0x00000001
10233 -
10234 -/**
10235 - * struct dpbp_notification_cfg - Structure representing DPBP notifications
10236 - * towards software
10237 - * @depletion_entry: below this threshold the pool is "depleted";
10238 - * set it to '0' to disable it
10239 - * @depletion_exit: greater than or equal to this threshold the pool exit its
10240 - * "depleted" state
10241 - * @surplus_entry: above this threshold the pool is in "surplus" state;
10242 - * set it to '0' to disable it
10243 - * @surplus_exit: less than or equal to this threshold the pool exit its
10244 - * "surplus" state
10245 - * @message_iova: MUST be given if either 'depletion_entry' or 'surplus_entry'
10246 - * is not '0' (enable); I/O virtual address (must be in DMA-able memory),
10247 - * must be 16B aligned.
10248 - * @message_ctx: The context that will be part of the BPSCN message and will
10249 - * be written to 'message_iova'
10250 - * @options: Mask of available options; use 'DPBP_NOTIF_OPT_<X>' values
10251 - */
10252 -struct dpbp_notification_cfg {
10253 - u32 depletion_entry;
10254 - u32 depletion_exit;
10255 - u32 surplus_entry;
10256 - u32 surplus_exit;
10257 - u64 message_iova;
10258 - u64 message_ctx;
10259 - u16 options;
10260 -};
10261 -
10262 -int dpbp_set_notifications(struct fsl_mc_io *mc_io,
10263 - u32 cmd_flags,
10264 - u16 token,
10265 - struct dpbp_notification_cfg *cfg);
10266 -
10267 -int dpbp_get_notifications(struct fsl_mc_io *mc_io,
10268 - u32 cmd_flags,
10269 - u16 token,
10270 - struct dpbp_notification_cfg *cfg);
10271 -
10272 -/** @} */
10273 +int dpbp_get_attributes(struct fsl_mc_io *mc_io,
10274 + u32 cmd_flags,
10275 + u16 token,
10276 + struct dpbp_attr *attr);
10277 +
10278 +int dpbp_get_api_version(struct fsl_mc_io *mc_io,
10279 + u32 cmd_flags,
10280 + u16 *major_ver,
10281 + u16 *minor_ver);
10282  
10283 #endif /* __FSL_DPBP_H */
10284 --- /dev/null
10285 +++ b/drivers/staging/fsl-mc/include/dpcon.h
10286 @@ -0,0 +1,115 @@
10287 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
10288 + *
10289 + * Redistribution and use in source and binary forms, with or without
10290 + * modification, are permitted provided that the following conditions are met:
10291 + * * Redistributions of source code must retain the above copyright
10292 + * notice, this list of conditions and the following disclaimer.
10293 + * * Redistributions in binary form must reproduce the above copyright
10294 + * notice, this list of conditions and the following disclaimer in the
10295 + * documentation and/or other materials provided with the distribution.
10296 + * * Neither the name of the above-listed copyright holders nor the
10297 + * names of any contributors may be used to endorse or promote products
10298 + * derived from this software without specific prior written permission.
10299 + *
10300 + *
10301 + * ALTERNATIVELY, this software may be distributed under the terms of the
10302 + * GNU General Public License ("GPL") as published by the Free Software
10303 + * Foundation, either version 2 of that License or (at your option) any
10304 + * later version.
10305 + *
10306 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10307 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10308 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10309 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10310 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10311 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10312 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10313 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10314 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10315 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10316 + * POSSIBILITY OF SUCH DAMAGE.
10317 + */
10318 +#ifndef __FSL_DPCON_H
10319 +#define __FSL_DPCON_H
10320 +
10321 +/* Data Path Concentrator API
10322 + * Contains initialization APIs and runtime control APIs for DPCON
10323 + */
10324 +
10325 +struct fsl_mc_io;
10326 +
10327 +/** General DPCON macros */
10328 +
10329 +/**
10330 + * Use it to disable notifications; see dpcon_set_notification()
10331 + */
10332 +#define DPCON_INVALID_DPIO_ID (int)(-1)
10333 +
10334 +int dpcon_open(struct fsl_mc_io *mc_io,
10335 + u32 cmd_flags,
10336 + int dpcon_id,
10337 + u16 *token);
10338 +
10339 +int dpcon_close(struct fsl_mc_io *mc_io,
10340 + u32 cmd_flags,
10341 + u16 token);
10342 +
10343 +int dpcon_enable(struct fsl_mc_io *mc_io,
10344 + u32 cmd_flags,
10345 + u16 token);
10346 +
10347 +int dpcon_disable(struct fsl_mc_io *mc_io,
10348 + u32 cmd_flags,
10349 + u16 token);
10350 +
10351 +int dpcon_is_enabled(struct fsl_mc_io *mc_io,
10352 + u32 cmd_flags,
10353 + u16 token,
10354 + int *en);
10355 +
10356 +int dpcon_reset(struct fsl_mc_io *mc_io,
10357 + u32 cmd_flags,
10358 + u16 token);
10359 +
10360 +/**
10361 + * struct dpcon_attr - Structure representing DPCON attributes
10362 + * @id: DPCON object ID
10363 + * @qbman_ch_id: Channel ID to be used by dequeue operation
10364 + * @num_priorities: Number of priorities for the DPCON channel (1-8)
10365 + */
10366 +struct dpcon_attr {
10367 + int id;
10368 + u16 qbman_ch_id;
10369 + u8 num_priorities;
10370 +};
10371 +
10372 +int dpcon_get_attributes(struct fsl_mc_io *mc_io,
10373 + u32 cmd_flags,
10374 + u16 token,
10375 + struct dpcon_attr *attr);
10376 +
10377 +/**
10378 + * struct dpcon_notification_cfg - Structure representing notification params
10379 + * @dpio_id: DPIO object ID; must be configured with a notification channel;
10380 + * to disable notifications set it to 'DPCON_INVALID_DPIO_ID';
10381 + * @priority: Priority selection within the DPIO channel; valid values
10382 + * are 0-7, depending on the number of priorities in that channel
10383 + * @user_ctx: User context value provided with each CDAN message
10384 + */
10385 +struct dpcon_notification_cfg {
10386 + int dpio_id;
10387 + u8 priority;
10388 + u64 user_ctx;
10389 +};
10390 +
10391 +int dpcon_set_notification(struct fsl_mc_io *mc_io,
10392 + u32 cmd_flags,
10393 + u16 token,
10394 + struct dpcon_notification_cfg *cfg);
10395 +
10396 +int dpcon_get_api_version(struct fsl_mc_io *mc_io,
10397 + u32 cmd_flags,
10398 + u16 *major_ver,
10399 + u16 *minor_ver);
10400 +
10401 +#endif /* __FSL_DPCON_H */
10402 --- a/drivers/staging/fsl-mc/include/dpmng.h
10403 +++ b/drivers/staging/fsl-mc/include/dpmng.h
10404 @@ -1,4 +1,5 @@
10405 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10406 +/*
10407 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10408 *
10409 * Redistribution and use in source and binary forms, with or without
10410 * modification, are permitted provided that the following conditions are met:
10411 @@ -32,7 +33,8 @@
10412 #ifndef __FSL_DPMNG_H
10413 #define __FSL_DPMNG_H
10414  
10415 -/* Management Complex General API
10416 +/*
10417 + * Management Complex General API
10418 * Contains general API for the Management Complex firmware
10419 */
10420  
10421 @@ -58,12 +60,8 @@ struct mc_version {
10422 u32 revision;
10423 };
10424  
10425 -int mc_get_version(struct fsl_mc_io *mc_io,
10426 - u32 cmd_flags,
10427 - struct mc_version *mc_ver_info);
10428 -
10429 -int dpmng_get_container_id(struct fsl_mc_io *mc_io,
10430 - u32 cmd_flags,
10431 - int *container_id);
10432 +int mc_get_version(struct fsl_mc_io *mc_io,
10433 + u32 cmd_flags,
10434 + struct mc_version *mc_ver_info);
10435  
10436 #endif /* __FSL_DPMNG_H */
10437 --- /dev/null
10438 +++ b/drivers/staging/fsl-mc/include/dpopr.h
10439 @@ -0,0 +1,110 @@
10440 +/*
10441 + * Copyright 2017 NXP
10442 + *
10443 + * Redistribution and use in source and binary forms, with or without
10444 + * modification, are permitted provided that the following conditions are met:
10445 + * * Redistributions of source code must retain the above copyright
10446 + * notice, this list of conditions and the following disclaimer.
10447 + * * Redistributions in binary form must reproduce the above copyright
10448 + * notice, this list of conditions and the following disclaimer in the
10449 + * documentation and/or other materials provided with the distribution.
10450 + * * Neither the name of the above-listed copyright holders nor the
10451 + * names of any contributors may be used to endorse or promote products
10452 + * derived from this software without specific prior written permission.
10453 + *
10454 + *
10455 + * ALTERNATIVELY, this software may be distributed under the terms of the
10456 + * GNU General Public License ("GPL") as published by the Free Software
10457 + * Foundation, either version 2 of that License or (at your option) any
10458 + * later version.
10459 + *
10460 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10461 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10462 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10463 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10464 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10465 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10466 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10467 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10468 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10469 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10470 + * POSSIBILITY OF SUCH DAMAGE.
10471 + */
10472 +#ifndef __FSL_DPOPR_H_
10473 +#define __FSL_DPOPR_H_
10474 +
10475 +/* Data Path Order Restoration API
10476 + * Contains initialization APIs and runtime APIs for the Order Restoration
10477 + */
10478 +
10479 +/** Order Restoration properties */
10480 +
10481 +/**
10482 + * Create a new Order Point Record option
10483 + */
10484 +#define OPR_OPT_CREATE 0x1
10485 +/**
10486 + * Retire an existing Order Point Record option
10487 + */
10488 +#define OPR_OPT_RETIRE 0x2
10489 +
10490 +/**
10491 + * struct opr_cfg - Structure representing OPR configuration
10492 + * @oprrws: Order point record (OPR) restoration window size (0 to 5)
10493 + * 0 - Window size is 32 frames.
10494 + * 1 - Window size is 64 frames.
10495 + * 2 - Window size is 128 frames.
10496 + * 3 - Window size is 256 frames.
10497 + * 4 - Window size is 512 frames.
10498 + * 5 - Window size is 1024 frames.
10499 + * @oa: OPR auto advance NESN window size (0 disabled, 1 enabled)
10500 + * @olws: OPR acceptable late arrival window size (0 to 3)
10501 + * 0 - Disabled. Late arrivals are always rejected.
10502 + * 1 - Window size is 32 frames.
10503 + * 2 - Window size is the same as the OPR restoration
10504 + * window size configured in the OPRRWS field.
10505 + * 3 - Window size is 8192 frames. Late arrivals are
10506 + * always accepted.
10507 + * @oeane: Order restoration list (ORL) resource exhaustion
10508 + * advance NESN enable (0 disabled, 1 enabled)
10509 + * @oloe: OPR loose ordering enable (0 disabled, 1 enabled)
10510 + */
10511 +struct opr_cfg {
10512 + u8 oprrws;
10513 + u8 oa;
10514 + u8 olws;
10515 + u8 oeane;
10516 + u8 oloe;
10517 +};
10518 +
10519 +/**
10520 + * struct opr_qry - Structure representing OPR configuration
10521 + * @enable: Enabled state
10522 + * @rip: Retirement In Progress
10523 + * @ndsn: Next dispensed sequence number
10524 + * @nesn: Next expected sequence number
10525 + * @ea_hseq: Early arrival head sequence number
10526 + * @hseq_nlis: HSEQ not last in sequence
10527 + * @ea_tseq: Early arrival tail sequence number
10528 + * @tseq_nlis: TSEQ not last in sequence
10529 + * @ea_tptr: Early arrival tail pointer
10530 + * @ea_hptr: Early arrival head pointer
10531 + * @opr_id: Order Point Record ID
10532 + * @opr_vid: Order Point Record Virtual ID
10533 + */
10534 +struct opr_qry {
10535 + char enable;
10536 + char rip;
10537 + u16 ndsn;
10538 + u16 nesn;
10539 + u16 ea_hseq;
10540 + char hseq_nlis;
10541 + u16 ea_tseq;
10542 + char tseq_nlis;
10543 + u16 ea_tptr;
10544 + u16 ea_hptr;
10545 + u16 opr_id;
10546 + u16 opr_vid;
10547 +};
10548 +
10549 +#endif /* __FSL_DPOPR_H_ */
10550 --- a/drivers/staging/fsl-mc/include/dprc.h
10551 +++ b/drivers/staging/fsl-mc/include/dprc.h
10552 @@ -1,4 +1,5 @@
10553 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10554 +/*
10555 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10556 *
10557 * Redistribution and use in source and binary forms, with or without
10558 * modification, are permitted provided that the following conditions are met:
10559 @@ -34,26 +35,13 @@
10560  
10561 #include "mc-cmd.h"
10562  
10563 -/* Data Path Resource Container API
10564 +/*
10565 + * Data Path Resource Container API
10566 * Contains DPRC API for managing and querying DPAA resources
10567 */
10568  
10569 struct fsl_mc_io;
10570  
10571 -/**
10572 - * Set this value as the icid value in dprc_cfg structure when creating a
10573 - * container, in case the ICID is not selected by the user and should be
10574 - * allocated by the DPRC from the pool of ICIDs.
10575 - */
10576 -#define DPRC_GET_ICID_FROM_POOL (u16)(~(0))
10577 -
10578 -/**
10579 - * Set this value as the portal_id value in dprc_cfg structure when creating a
10580 - * container, in case the portal ID is not specifically selected by the
10581 - * user and should be allocated by the DPRC from the pool of portal ids.
10582 - */
10583 -#define DPRC_GET_PORTAL_ID_FROM_POOL (int)(~(0))
10584 -
10585 int dprc_open(struct fsl_mc_io *mc_io,
10586 u32 cmd_flags,
10587 int container_id,
10588 @@ -63,75 +51,6 @@ int dprc_close(struct fsl_mc_io *mc_io,
10589 u32 cmd_flags,
10590 u16 token);
10591  
10592 -/**
10593 - * Container general options
10594 - *
10595 - * These options may be selected at container creation by the container creator
10596 - * and can be retrieved using dprc_get_attributes()
10597 - */
10598 -
10599 -/* Spawn Policy Option allowed - Indicates that the new container is allowed
10600 - * to spawn and have its own child containers.
10601 - */
10602 -#define DPRC_CFG_OPT_SPAWN_ALLOWED 0x00000001
10603 -
10604 -/* General Container allocation policy - Indicates that the new container is
10605 - * allowed to allocate requested resources from its parent container; if not
10606 - * set, the container is only allowed to use resources in its own pools; Note
10607 - * that this is a container's global policy, but the parent container may
10608 - * override it and set specific quota per resource type.
10609 - */
10610 -#define DPRC_CFG_OPT_ALLOC_ALLOWED 0x00000002
10611 -
10612 -/* Object initialization allowed - software context associated with this
10613 - * container is allowed to invoke object initialization operations.
10614 - */
10615 -#define DPRC_CFG_OPT_OBJ_CREATE_ALLOWED 0x00000004
10616 -
10617 -/* Topology change allowed - software context associated with this
10618 - * container is allowed to invoke topology operations, such as attach/detach
10619 - * of network objects.
10620 - */
10621 -#define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008
10622 -
10623 -/* AIOP - Indicates that container belongs to AIOP. */
10624 -#define DPRC_CFG_OPT_AIOP 0x00000020
10625 -
10626 -/* IRQ Config - Indicates that the container allowed to configure its IRQs. */
10627 -#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED 0x00000040
10628 -
10629 -/**
10630 - * struct dprc_cfg - Container configuration options
10631 - * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free
10632 - * ICID value is allocated by the DPRC
10633 - * @portal_id: Portal ID; if set to 'DPRC_GET_PORTAL_ID_FROM_POOL', a free
10634 - * portal ID is allocated by the DPRC
10635 - * @options: Combination of 'DPRC_CFG_OPT_<X>' options
10636 - * @label: Object's label
10637 - */
10638 -struct dprc_cfg {
10639 - u16 icid;
10640 - int portal_id;
10641 - u64 options;
10642 - char label[16];
10643 -};
10644 -
10645 -int dprc_create_container(struct fsl_mc_io *mc_io,
10646 - u32 cmd_flags,
10647 - u16 token,
10648 - struct dprc_cfg *cfg,
10649 - int *child_container_id,
10650 - u64 *child_portal_offset);
10651 -
10652 -int dprc_destroy_container(struct fsl_mc_io *mc_io,
10653 - u32 cmd_flags,
10654 - u16 token,
10655 - int child_container_id);
10656 -
10657 -int dprc_reset_container(struct fsl_mc_io *mc_io,
10658 - u32 cmd_flags,
10659 - u16 token,
10660 - int child_container_id);
10661  
10662 /* IRQ */
10663  
10664 @@ -139,7 +58,7 @@ int dprc_reset_container(struct fsl_mc_i
10665 #define DPRC_IRQ_INDEX 0
10666  
10667 /* Number of dprc's IRQs */
10668 -#define DPRC_NUM_OF_IRQS 1
10669 +#define DPRC_NUM_OF_IRQS 1
10670  
10671 /* DPRC IRQ events */
10672  
10673 @@ -151,12 +70,14 @@ int dprc_reset_container(struct fsl_mc_i
10674 #define DPRC_IRQ_EVENT_RES_ADDED 0x00000004
10675 /* IRQ event - Indicates that resources removed from the container */
10676 #define DPRC_IRQ_EVENT_RES_REMOVED 0x00000008
10677 -/* IRQ event - Indicates that one of the descendant containers that opened by
10678 +/*
10679 + * IRQ event - Indicates that one of the descendant containers that opened by
10680 * this container is destroyed
10681 */
10682 #define DPRC_IRQ_EVENT_CONTAINER_DESTROYED 0x00000010
10683  
10684 -/* IRQ event - Indicates that on one of the container's opened object is
10685 +/*
10686 + * IRQ event - Indicates that on one of the container's opened object is
10687 * destroyed
10688 */
10689 #define DPRC_IRQ_EVENT_OBJ_DESTROYED 0x00000020
10690 @@ -171,59 +92,59 @@ int dprc_reset_container(struct fsl_mc_i
10691 * @irq_num: A user defined number associated with this IRQ
10692 */
10693 struct dprc_irq_cfg {
10694 - phys_addr_t paddr;
10695 - u32 val;
10696 - int irq_num;
10697 -};
10698 -
10699 -int dprc_set_irq(struct fsl_mc_io *mc_io,
10700 - u32 cmd_flags,
10701 - u16 token,
10702 - u8 irq_index,
10703 - struct dprc_irq_cfg *irq_cfg);
10704 -
10705 -int dprc_get_irq(struct fsl_mc_io *mc_io,
10706 - u32 cmd_flags,
10707 - u16 token,
10708 - u8 irq_index,
10709 - int *type,
10710 - struct dprc_irq_cfg *irq_cfg);
10711 -
10712 -int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
10713 - u32 cmd_flags,
10714 - u16 token,
10715 - u8 irq_index,
10716 - u8 en);
10717 -
10718 -int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
10719 - u32 cmd_flags,
10720 - u16 token,
10721 - u8 irq_index,
10722 - u8 *en);
10723 -
10724 -int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
10725 - u32 cmd_flags,
10726 - u16 token,
10727 - u8 irq_index,
10728 - u32 mask);
10729 -
10730 -int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
10731 - u32 cmd_flags,
10732 - u16 token,
10733 - u8 irq_index,
10734 - u32 *mask);
10735 -
10736 -int dprc_get_irq_status(struct fsl_mc_io *mc_io,
10737 - u32 cmd_flags,
10738 - u16 token,
10739 - u8 irq_index,
10740 - u32 *status);
10741 -
10742 -int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
10743 - u32 cmd_flags,
10744 - u16 token,
10745 - u8 irq_index,
10746 - u32 status);
10747 + phys_addr_t paddr;
10748 + u32 val;
10749 + int irq_num;
10750 +};
10751 +
10752 +int dprc_set_irq(struct fsl_mc_io *mc_io,
10753 + u32 cmd_flags,
10754 + u16 token,
10755 + u8 irq_index,
10756 + struct dprc_irq_cfg *irq_cfg);
10757 +
10758 +int dprc_get_irq(struct fsl_mc_io *mc_io,
10759 + u32 cmd_flags,
10760 + u16 token,
10761 + u8 irq_index,
10762 + int *type,
10763 + struct dprc_irq_cfg *irq_cfg);
10764 +
10765 +int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
10766 + u32 cmd_flags,
10767 + u16 token,
10768 + u8 irq_index,
10769 + u8 en);
10770 +
10771 +int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
10772 + u32 cmd_flags,
10773 + u16 token,
10774 + u8 irq_index,
10775 + u8 *en);
10776 +
10777 +int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
10778 + u32 cmd_flags,
10779 + u16 token,
10780 + u8 irq_index,
10781 + u32 mask);
10782 +
10783 +int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
10784 + u32 cmd_flags,
10785 + u16 token,
10786 + u8 irq_index,
10787 + u32 *mask);
10788 +
10789 +int dprc_get_irq_status(struct fsl_mc_io *mc_io,
10790 + u32 cmd_flags,
10791 + u16 token,
10792 + u8 irq_index,
10793 + u32 *status);
10794 +
10795 +int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
10796 + u32 cmd_flags,
10797 + u16 token,
10798 + u8 irq_index,
10799 + u32 status);
10800  
10801 /**
10802 * struct dprc_attributes - Container attributes
10803 @@ -231,114 +152,23 @@ int dprc_clear_irq_status(struct fsl_mc_
10804 * @icid: Container's ICID
10805 * @portal_id: Container's portal ID
10806 * @options: Container's options as set at container's creation
10807 - * @version: DPRC version
10808 */
10809 struct dprc_attributes {
10810 int container_id;
10811 u16 icid;
10812 int portal_id;
10813 u64 options;
10814 - /**
10815 - * struct version - DPRC version
10816 - * @major: DPRC major version
10817 - * @minor: DPRC minor version
10818 - */
10819 - struct {
10820 - u16 major;
10821 - u16 minor;
10822 - } version;
10823 };
10824  
10825 -int dprc_get_attributes(struct fsl_mc_io *mc_io,
10826 - u32 cmd_flags,
10827 - u16 token,
10828 - struct dprc_attributes *attributes);
10829 -
10830 -int dprc_set_res_quota(struct fsl_mc_io *mc_io,
10831 - u32 cmd_flags,
10832 - u16 token,
10833 - int child_container_id,
10834 - char *type,
10835 - u16 quota);
10836 -
10837 -int dprc_get_res_quota(struct fsl_mc_io *mc_io,
10838 - u32 cmd_flags,
10839 - u16 token,
10840 - int child_container_id,
10841 - char *type,
10842 - u16 *quota);
10843 -
10844 -/* Resource request options */
10845 -
10846 -/* Explicit resource ID request - The requested objects/resources
10847 - * are explicit and sequential (in case of resources).
10848 - * The base ID is given at res_req at base_align field
10849 - */
10850 -#define DPRC_RES_REQ_OPT_EXPLICIT 0x00000001
10851 -
10852 -/* Aligned resources request - Relevant only for resources
10853 - * request (and not objects). Indicates that resources base ID should be
10854 - * sequential and aligned to the value given at dprc_res_req base_align field
10855 - */
10856 -#define DPRC_RES_REQ_OPT_ALIGNED 0x00000002
10857 -
10858 -/* Plugged Flag - Relevant only for object assignment request.
10859 - * Indicates that after all objects assigned. An interrupt will be invoked at
10860 - * the relevant GPP. The assigned object will be marked as plugged.
10861 - * plugged objects can't be assigned from their container
10862 - */
10863 -#define DPRC_RES_REQ_OPT_PLUGGED 0x00000004
10864 -
10865 -/**
10866 - * struct dprc_res_req - Resource request descriptor, to be used in assignment
10867 - * or un-assignment of resources and objects.
10868 - * @type: Resource/object type: Represent as a NULL terminated string.
10869 - * This string may received by using dprc_get_pool() to get resource
10870 - * type and dprc_get_obj() to get object type;
10871 - * Note: it is not possible to assign/un-assign DPRC objects
10872 - * @num: Number of resources
10873 - * @options: Request options: combination of DPRC_RES_REQ_OPT_ options
10874 - * @id_base_align: In case of explicit assignment (DPRC_RES_REQ_OPT_EXPLICIT
10875 - * is set at option), this field represents the required base ID
10876 - * for resource allocation; In case of aligned assignment
10877 - * (DPRC_RES_REQ_OPT_ALIGNED is set at option), this field
10878 - * indicates the required alignment for the resource ID(s) -
10879 - * use 0 if there is no alignment or explicit ID requirements
10880 - */
10881 -struct dprc_res_req {
10882 - char type[16];
10883 - u32 num;
10884 - u32 options;
10885 - int id_base_align;
10886 -};
10887 -
10888 -int dprc_assign(struct fsl_mc_io *mc_io,
10889 - u32 cmd_flags,
10890 - u16 token,
10891 - int container_id,
10892 - struct dprc_res_req *res_req);
10893 -
10894 -int dprc_unassign(struct fsl_mc_io *mc_io,
10895 - u32 cmd_flags,
10896 - u16 token,
10897 - int child_container_id,
10898 - struct dprc_res_req *res_req);
10899 -
10900 -int dprc_get_pool_count(struct fsl_mc_io *mc_io,
10901 - u32 cmd_flags,
10902 - u16 token,
10903 - int *pool_count);
10904 -
10905 -int dprc_get_pool(struct fsl_mc_io *mc_io,
10906 - u32 cmd_flags,
10907 - u16 token,
10908 - int pool_index,
10909 - char *type);
10910 +int dprc_get_attributes(struct fsl_mc_io *mc_io,
10911 + u32 cmd_flags,
10912 + u16 token,
10913 + struct dprc_attributes *attributes);
10914  
10915 int dprc_get_obj_count(struct fsl_mc_io *mc_io,
10916 - u32 cmd_flags,
10917 - u16 token,
10918 - int *obj_count);
10919 + u32 cmd_flags,
10920 + u16 token,
10921 + int *obj_count);
10922  
10923 /* Objects Attributes Flags */
10924  
10925 @@ -353,7 +183,7 @@ int dprc_get_obj_count(struct fsl_mc_io
10926 * masters;
10927 * user is responsible for proper memory handling through IOMMU configuration.
10928 */
10929 -#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
10930 +#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
10931  
10932 /**
10933 * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj()
10934 @@ -381,41 +211,41 @@ struct dprc_obj_desc {
10935 u16 flags;
10936 };
10937  
10938 -int dprc_get_obj(struct fsl_mc_io *mc_io,
10939 - u32 cmd_flags,
10940 - u16 token,
10941 - int obj_index,
10942 - struct dprc_obj_desc *obj_desc);
10943 -
10944 -int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
10945 - u32 cmd_flags,
10946 - u16 token,
10947 - char *obj_type,
10948 - int obj_id,
10949 - struct dprc_obj_desc *obj_desc);
10950 -
10951 -int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
10952 - u32 cmd_flags,
10953 - u16 token,
10954 - char *obj_type,
10955 - int obj_id,
10956 - u8 irq_index,
10957 - struct dprc_irq_cfg *irq_cfg);
10958 -
10959 -int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
10960 - u32 cmd_flags,
10961 - u16 token,
10962 - char *obj_type,
10963 - int obj_id,
10964 - u8 irq_index,
10965 - int *type,
10966 - struct dprc_irq_cfg *irq_cfg);
10967 -
10968 -int dprc_get_res_count(struct fsl_mc_io *mc_io,
10969 - u32 cmd_flags,
10970 - u16 token,
10971 - char *type,
10972 - int *res_count);
10973 +int dprc_get_obj(struct fsl_mc_io *mc_io,
10974 + u32 cmd_flags,
10975 + u16 token,
10976 + int obj_index,
10977 + struct dprc_obj_desc *obj_desc);
10978 +
10979 +int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
10980 + u32 cmd_flags,
10981 + u16 token,
10982 + char *obj_type,
10983 + int obj_id,
10984 + struct dprc_obj_desc *obj_desc);
10985 +
10986 +int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
10987 + u32 cmd_flags,
10988 + u16 token,
10989 + char *obj_type,
10990 + int obj_id,
10991 + u8 irq_index,
10992 + struct dprc_irq_cfg *irq_cfg);
10993 +
10994 +int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
10995 + u32 cmd_flags,
10996 + u16 token,
10997 + char *obj_type,
10998 + int obj_id,
10999 + u8 irq_index,
11000 + int *type,
11001 + struct dprc_irq_cfg *irq_cfg);
11002 +
11003 +int dprc_get_res_count(struct fsl_mc_io *mc_io,
11004 + u32 cmd_flags,
11005 + u16 token,
11006 + char *type,
11007 + int *res_count);
11008  
11009 /**
11010 * enum dprc_iter_status - Iteration status
11011 @@ -429,27 +259,6 @@ enum dprc_iter_status {
11012 DPRC_ITER_STATUS_LAST = 2
11013 };
11014  
11015 -/**
11016 - * struct dprc_res_ids_range_desc - Resource ID range descriptor
11017 - * @base_id: Base resource ID of this range
11018 - * @last_id: Last resource ID of this range
11019 - * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at
11020 - * first iteration; while the returned marker is DPRC_ITER_STATUS_MORE,
11021 - * additional iterations are needed, until the returned marker is
11022 - * DPRC_ITER_STATUS_LAST
11023 - */
11024 -struct dprc_res_ids_range_desc {
11025 - int base_id;
11026 - int last_id;
11027 - enum dprc_iter_status iter_status;
11028 -};
11029 -
11030 -int dprc_get_res_ids(struct fsl_mc_io *mc_io,
11031 - u32 cmd_flags,
11032 - u16 token,
11033 - char *type,
11034 - struct dprc_res_ids_range_desc *range_desc);
11035 -
11036 /* Region flags */
11037 /* Cacheable - Indicates that region should be mapped as cacheable */
11038 #define DPRC_REGION_CACHEABLE 0x00000001
11039 @@ -481,64 +290,27 @@ struct dprc_region_desc {
11040 enum dprc_region_type type;
11041 };
11042  
11043 -int dprc_get_obj_region(struct fsl_mc_io *mc_io,
11044 - u32 cmd_flags,
11045 - u16 token,
11046 - char *obj_type,
11047 - int obj_id,
11048 - u8 region_index,
11049 - struct dprc_region_desc *region_desc);
11050 -
11051 -int dprc_set_obj_label(struct fsl_mc_io *mc_io,
11052 - u32 cmd_flags,
11053 - u16 token,
11054 - char *obj_type,
11055 - int obj_id,
11056 - char *label);
11057 +int dprc_get_obj_region(struct fsl_mc_io *mc_io,
11058 + u32 cmd_flags,
11059 + u16 token,
11060 + char *obj_type,
11061 + int obj_id,
11062 + u8 region_index,
11063 + struct dprc_region_desc *region_desc);
11064  
11065 -/**
11066 - * struct dprc_endpoint - Endpoint description for link connect/disconnect
11067 - * operations
11068 - * @type: Endpoint object type: NULL terminated string
11069 - * @id: Endpoint object ID
11070 - * @if_id: Interface ID; should be set for endpoints with multiple
11071 - * interfaces ("dpsw", "dpdmux"); for others, always set to 0
11072 - */
11073 -struct dprc_endpoint {
11074 - char type[16];
11075 - int id;
11076 - int if_id;
11077 -};
11078 +int dprc_get_api_version(struct fsl_mc_io *mc_io,
11079 + u32 cmd_flags,
11080 + u16 *major_ver,
11081 + u16 *minor_ver);
11082  
11083 -/**
11084 - * struct dprc_connection_cfg - Connection configuration.
11085 - * Used for virtual connections only
11086 - * @committed_rate: Committed rate (Mbits/s)
11087 - * @max_rate: Maximum rate (Mbits/s)
11088 - */
11089 -struct dprc_connection_cfg {
11090 - u32 committed_rate;
11091 - u32 max_rate;
11092 -};
11093 +int dprc_get_container_id(struct fsl_mc_io *mc_io,
11094 + u32 cmd_flags,
11095 + int *container_id);
11096  
11097 -int dprc_connect(struct fsl_mc_io *mc_io,
11098 - u32 cmd_flags,
11099 - u16 token,
11100 - const struct dprc_endpoint *endpoint1,
11101 - const struct dprc_endpoint *endpoint2,
11102 - const struct dprc_connection_cfg *cfg);
11103 -
11104 -int dprc_disconnect(struct fsl_mc_io *mc_io,
11105 - u32 cmd_flags,
11106 - u16 token,
11107 - const struct dprc_endpoint *endpoint);
11108 -
11109 -int dprc_get_connection(struct fsl_mc_io *mc_io,
11110 - u32 cmd_flags,
11111 - u16 token,
11112 - const struct dprc_endpoint *endpoint1,
11113 - struct dprc_endpoint *endpoint2,
11114 - int *state);
11115 +int dprc_reset_container(struct fsl_mc_io *mc_io,
11116 + u32 cmd_flags,
11117 + u16 token,
11118 + int child_container_id);
11119  
11120 #endif /* _FSL_DPRC_H */
11121  
11122 --- a/drivers/staging/fsl-mc/include/mc-bus.h
11123 +++ b/drivers/staging/fsl-mc/include/mc-bus.h
11124 @@ -1,7 +1,7 @@
11125 /*
11126 * Freescale Management Complex (MC) bus declarations
11127 *
11128 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
11129 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
11130 * Author: German Rivera <German.Rivera@freescale.com>
11131 *
11132 * This file is licensed under the terms of the GNU General Public
11133 @@ -42,8 +42,8 @@ struct msi_domain_info;
11134 */
11135 struct fsl_mc_resource_pool {
11136 enum fsl_mc_pool_type type;
11137 - int16_t max_count;
11138 - int16_t free_count;
11139 + int max_count;
11140 + int free_count;
11141 struct mutex mutex; /* serializes access to free_list */
11142 struct list_head free_list;
11143 struct fsl_mc_bus *mc_bus;
11144 @@ -73,6 +73,7 @@ struct fsl_mc_bus {
11145 int dprc_scan_container(struct fsl_mc_device *mc_bus_dev);
11146  
11147 int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
11148 + const char *driver_override,
11149 unsigned int *total_irq_count);
11150  
11151 int __init dprc_driver_init(void);
11152 --- a/drivers/staging/fsl-mc/include/mc-cmd.h
11153 +++ b/drivers/staging/fsl-mc/include/mc-cmd.h
11154 @@ -1,4 +1,5 @@
11155 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
11156 +/*
11157 + * Copyright 2013-2016 Freescale Semiconductor Inc.
11158 *
11159 * Redistribution and use in source and binary forms, with or without
11160 * modification, are permitted provided that the following conditions are met:
11161 @@ -48,6 +49,15 @@ struct mc_command {
11162 u64 params[MC_CMD_NUM_OF_PARAMS];
11163 };
11164  
11165 +struct mc_rsp_create {
11166 + __le32 object_id;
11167 +};
11168 +
11169 +struct mc_rsp_api_ver {
11170 + __le16 major_ver;
11171 + __le16 minor_ver;
11172 +};
11173 +
11174 enum mc_cmd_status {
11175 MC_CMD_STATUS_OK = 0x0, /* Completed successfully */
11176 MC_CMD_STATUS_READY = 0x1, /* Ready to be processed */
11177 @@ -72,11 +82,6 @@ enum mc_cmd_status {
11178 /* Command completion flag */
11179 #define MC_CMD_FLAG_INTR_DIS 0x01
11180  
11181 -#define MC_CMD_HDR_CMDID_MASK 0xFFF0
11182 -#define MC_CMD_HDR_CMDID_SHIFT 4
11183 -#define MC_CMD_HDR_TOKEN_MASK 0xFFC0
11184 -#define MC_CMD_HDR_TOKEN_SHIFT 6
11185 -
11186 static inline u64 mc_encode_cmd_header(u16 cmd_id,
11187 u32 cmd_flags,
11188 u16 token)
11189 @@ -84,10 +89,8 @@ static inline u64 mc_encode_cmd_header(u
11190 u64 header = 0;
11191 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&header;
11192  
11193 - hdr->cmd_id = cpu_to_le16((cmd_id << MC_CMD_HDR_CMDID_SHIFT) &
11194 - MC_CMD_HDR_CMDID_MASK);
11195 - hdr->token = cpu_to_le16((token << MC_CMD_HDR_TOKEN_SHIFT) &
11196 - MC_CMD_HDR_TOKEN_MASK);
11197 + hdr->cmd_id = cpu_to_le16(cmd_id);
11198 + hdr->token = cpu_to_le16(token);
11199 hdr->status = MC_CMD_STATUS_READY;
11200 if (cmd_flags & MC_CMD_FLAG_PRI)
11201 hdr->flags_hw = MC_CMD_FLAG_PRI;
11202 @@ -102,7 +105,26 @@ static inline u16 mc_cmd_hdr_read_token(
11203 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
11204 u16 token = le16_to_cpu(hdr->token);
11205  
11206 - return (token & MC_CMD_HDR_TOKEN_MASK) >> MC_CMD_HDR_TOKEN_SHIFT;
11207 + return token;
11208 +}
11209 +
11210 +static inline u32 mc_cmd_read_object_id(struct mc_command *cmd)
11211 +{
11212 + struct mc_rsp_create *rsp_params;
11213 +
11214 + rsp_params = (struct mc_rsp_create *)cmd->params;
11215 + return le32_to_cpu(rsp_params->object_id);
11216 +}
11217 +
11218 +static inline void mc_cmd_read_api_version(struct mc_command *cmd,
11219 + u16 *major_ver,
11220 + u16 *minor_ver)
11221 +{
11222 + struct mc_rsp_api_ver *rsp_params;
11223 +
11224 + rsp_params = (struct mc_rsp_api_ver *)cmd->params;
11225 + *major_ver = le16_to_cpu(rsp_params->major_ver);
11226 + *minor_ver = le16_to_cpu(rsp_params->minor_ver);
11227 }
11228  
11229 #endif /* __FSL_MC_CMD_H */
11230 --- a/drivers/staging/fsl-mc/include/mc-sys.h
11231 +++ b/drivers/staging/fsl-mc/include/mc-sys.h
11232 @@ -1,4 +1,5 @@
11233 -/* Copyright 2013-2014 Freescale Semiconductor Inc.
11234 +/*
11235 + * Copyright 2013-2016 Freescale Semiconductor Inc.
11236 *
11237 * Interface of the I/O services to send MC commands to the MC hardware
11238 *
11239 --- a/drivers/staging/fsl-mc/include/mc.h
11240 +++ b/drivers/staging/fsl-mc/include/mc.h
11241 @@ -1,7 +1,7 @@
11242 /*
11243 * Freescale Management Complex (MC) bus public interface
11244 *
11245 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
11246 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
11247 * Author: German Rivera <German.Rivera@freescale.com>
11248 *
11249 * This file is licensed under the terms of the GNU General Public
11250 @@ -81,7 +81,7 @@ enum fsl_mc_pool_type {
11251 */
11252 struct fsl_mc_resource {
11253 enum fsl_mc_pool_type type;
11254 - int32_t id;
11255 + s32 id;
11256 void *data;
11257 struct fsl_mc_resource_pool *parent_pool;
11258 struct list_head node;
11259 @@ -122,6 +122,7 @@ struct fsl_mc_device_irq {
11260 * @regions: pointer to array of MMIO region entries
11261 * @irqs: pointer to array of pointers to interrupts allocated to this device
11262 * @resource: generic resource associated with this MC object device, if any.
11263 + * @driver_override: Driver name to force a match
11264 *
11265 * Generic device object for MC object devices that are "attached" to a
11266 * MC bus.
11267 @@ -154,6 +155,7 @@ struct fsl_mc_device {
11268 struct resource *regions;
11269 struct fsl_mc_device_irq **irqs;
11270 struct fsl_mc_resource *resource;
11271 + const char *driver_override;
11272 };
11273  
11274 #define to_fsl_mc_device(_dev) \
11275 @@ -175,6 +177,8 @@ struct fsl_mc_device {
11276 #define fsl_mc_driver_register(drv) \
11277 __fsl_mc_driver_register(drv, THIS_MODULE)
11278  
11279 +void fsl_mc_device_remove(struct fsl_mc_device *mc_dev);
11280 +
11281 int __must_check __fsl_mc_driver_register(struct fsl_mc_driver *fsl_mc_driver,
11282 struct module *owner);
11283  
11284 @@ -198,4 +202,13 @@ int __must_check fsl_mc_allocate_irqs(st
11285  
11286 void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev);
11287  
11288 +void fsl_mc_dma_configure(struct fsl_mc_device *mc_dev,
11289 + struct device_node *fsl_mc_platform_node, int coherent);
11290 +
11291 +#ifdef CONFIG_FSL_MC_BUS
11292 +struct iommu_group *fsl_mc_device_group(struct device *dev);
11293 +#else
11294 +#define fsl_mc_device_group(__dev) NULL
11295 +#endif
11296 +
11297 #endif /* _FSL_MC_H_ */