OpenWrt – Blame information for rev 4

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Rev Author Line No. Line
4 office 1 From 1806d342beb334c8cb0a438315ad5529262b2791 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Wed, 17 Jan 2018 14:52:50 +0800
4 Subject: [PATCH 04/30] dts: support layercape
5  
6 This is an integrated patch for layerscape dts support.
7  
8 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
9 Signed-off-by: Alison Wang <b18965@freescale.com>
10 Signed-off-by: Li Yang <leoyang.li@nxp.com>
11 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
12 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
15 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
16 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
17 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
18 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
19 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
20 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
21 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
22 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
23 Signed-off-by: Meng Yi <meng.yi@nxp.com>
24 Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
25 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
26 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
27 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
28 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
29 ---
30 arch/arm/boot/dts/alpine.dtsi | 2 +-
31 arch/arm/boot/dts/axm55xx.dtsi | 2 +-
32 arch/arm/boot/dts/ecx-2000.dts | 2 +-
33 arch/arm/boot/dts/imx6ul.dtsi | 4 +-
34 arch/arm/boot/dts/keystone.dtsi | 4 +-
35 arch/arm/boot/dts/ls1021a-qds.dts | 21 +
36 arch/arm/boot/dts/ls1021a-twr.dts | 25 +
37 arch/arm/boot/dts/ls1021a.dtsi | 197 +++--
38 arch/arm/boot/dts/mt6580.dtsi | 2 +-
39 arch/arm/boot/dts/mt6589.dtsi | 2 +-
40 arch/arm/boot/dts/mt8127.dtsi | 2 +-
41 arch/arm/boot/dts/mt8135.dtsi | 2 +-
42 arch/arm/boot/dts/rk3288.dtsi | 2 +-
43 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
44 arch/arm/boot/dts/sun7i-a20.dtsi | 4 +-
45 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
46 arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
47 arch/arm64/boot/dts/freescale/Makefile | 17 +
48 .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 123 +++
49 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 177 ++++
50 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 202 +++++
51 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 138 ++++
52 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 602 ++++++++++++++
53 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi | 45 +
54 .../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 69 ++
55 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 171 +++-
56 .../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 69 ++
57 .../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++
58 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 113 ++-
59 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 308 ++++++-
60 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi | 48 ++
61 .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 110 +++
62 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 363 ++++++++
63 .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 83 ++
64 .../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++
65 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 218 +++++
66 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 800 ++++++++++++++++++
67 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 173 ++++
68 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 236 ++++++
69 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 825 ++++++++++++++++++
70 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 191 ++---
71 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 169 ++--
72 arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 9 +-
73 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 763 +++--------------
74 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 161 ++++
75 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 162 ++++
76 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 140 ++++
77 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 195 +++++
78 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 198 +++++
79 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 161 ++++
80 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 919 +++++++++++++++++++++
81 .../boot/dts/freescale/qoriq-bman1-portals.dtsi | 81 ++
82 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 73 ++
83 .../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 +
84 .../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 +
85 .../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 +
86 .../boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi | 42 +
87 .../boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi | 42 +
88 .../boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi | 42 +
89 .../boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi | 42 +
90 .../boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi | 42 +
91 .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 ++
92 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi | 130 +++
93 .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 104 +++
94 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 +
95 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
96 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
97 67 files changed, 8231 insertions(+), 1022 deletions(-)
98 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
99 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
100 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
101 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
102 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
103 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
104 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
105 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
106 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
107 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
108 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
109 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
110 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
111 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
112 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
113 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
114 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
115 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
116 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
117 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
118 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
119 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
120 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
121 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
122 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
123 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
124 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
125 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
126 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
127 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
128 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
129 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
130 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
131 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
132 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
133 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
134 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
135 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
136 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
137  
138 --- a/arch/arm/boot/dts/alpine.dtsi
139 +++ b/arch/arm/boot/dts/alpine.dtsi
140 @@ -93,7 +93,7 @@
141 interrupt-controller;
142 reg = <0x0 0xfb001000 0x0 0x1000>,
143 <0x0 0xfb002000 0x0 0x2000>,
144 - <0x0 0xfb004000 0x0 0x1000>,
145 + <0x0 0xfb004000 0x0 0x2000>,
146 <0x0 0xfb006000 0x0 0x2000>;
147 interrupts =
148 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 --- a/arch/arm/boot/dts/axm55xx.dtsi
150 +++ b/arch/arm/boot/dts/axm55xx.dtsi
151 @@ -62,7 +62,7 @@
152 #address-cells = <0>;
153 interrupt-controller;
154 reg = <0x20 0x01001000 0 0x1000>,
155 - <0x20 0x01002000 0 0x1000>,
156 + <0x20 0x01002000 0 0x2000>,
157 <0x20 0x01004000 0 0x2000>,
158 <0x20 0x01006000 0 0x2000>;
159 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
160 --- a/arch/arm/boot/dts/ecx-2000.dts
161 +++ b/arch/arm/boot/dts/ecx-2000.dts
162 @@ -99,7 +99,7 @@
163 interrupt-controller;
164 interrupts = <1 9 0xf04>;
165 reg = <0xfff11000 0x1000>,
166 - <0xfff12000 0x1000>,
167 + <0xfff12000 0x2000>,
168 <0xfff14000 0x2000>,
169 <0xfff16000 0x2000>;
170 };
171 --- a/arch/arm/boot/dts/imx6ul.dtsi
172 +++ b/arch/arm/boot/dts/imx6ul.dtsi
173 @@ -89,11 +89,11 @@
174 };
175  
176 intc: interrupt-controller@00a01000 {
177 - compatible = "arm,cortex-a7-gic";
178 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
179 #interrupt-cells = <3>;
180 interrupt-controller;
181 reg = <0x00a01000 0x1000>,
182 - <0x00a02000 0x1000>,
183 + <0x00a02000 0x2000>,
184 <0x00a04000 0x2000>,
185 <0x00a06000 0x2000>;
186 };
187 --- a/arch/arm/boot/dts/keystone.dtsi
188 +++ b/arch/arm/boot/dts/keystone.dtsi
189 @@ -30,12 +30,12 @@
190 };
191  
192 gic: interrupt-controller {
193 - compatible = "arm,cortex-a15-gic";
194 + compatible = "arm,gic-400", "arm,cortex-a15-gic";
195 #interrupt-cells = <3>;
196 interrupt-controller;
197 reg = <0x0 0x02561000 0x0 0x1000>,
198 <0x0 0x02562000 0x0 0x2000>,
199 - <0x0 0x02564000 0x0 0x1000>,
200 + <0x0 0x02564000 0x0 0x2000>,
201 <0x0 0x02566000 0x0 0x2000>;
202 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
203 IRQ_TYPE_LEVEL_HIGH)>;
204 --- a/arch/arm/boot/dts/ls1021a-qds.dts
205 +++ b/arch/arm/boot/dts/ls1021a-qds.dts
206 @@ -124,6 +124,19 @@
207 };
208 };
209  
210 +&qspi {
211 + num-cs = <2>;
212 + status = "okay";
213 +
214 + qflash0: s25fl128s@0 {
215 + compatible = "spansion,m25p80";
216 + #address-cells = <1>;
217 + #size-cells = <1>;
218 + spi-max-frequency = <20000000>;
219 + reg = <0>;
220 + };
221 +};
222 +
223 &enet0 {
224 tbi-handle = <&tbi0>;
225 phy-handle = <&sgmii_phy1c>;
226 @@ -331,3 +344,11 @@
227 &uart1 {
228 status = "okay";
229 };
230 +
231 +&can0 {
232 + status = "okay";
233 +};
234 +
235 +&can1 {
236 + status = "okay";
237 +};
238 --- a/arch/arm/boot/dts/ls1021a-twr.dts
239 +++ b/arch/arm/boot/dts/ls1021a-twr.dts
240 @@ -142,6 +142,19 @@
241 };
242 };
243  
244 +&qspi {
245 + num-cs = <2>;
246 + status = "okay";
247 +
248 + qflash0: n25q128a13@0 {
249 + compatible = "n25q128a13", "jedec,spi-nor";
250 + #address-cells = <1>;
251 + #size-cells = <1>;
252 + spi-max-frequency = <20000000>;
253 + reg = <0>;
254 + };
255 +};
256 +
257 &enet0 {
258 tbi-handle = <&tbi1>;
259 phy-handle = <&sgmii_phy2>;
260 @@ -228,6 +241,10 @@
261 };
262 };
263  
264 +&esdhc {
265 + status = "okay";
266 +};
267 +
268 &sai1 {
269 status = "okay";
270 };
271 @@ -243,3 +260,11 @@
272 &uart1 {
273 status = "okay";
274 };
275 +
276 +&can0 {
277 + status = "okay";
278 +};
279 +
280 +&can1 {
281 + status = "okay";
282 +};
283 --- a/arch/arm/boot/dts/ls1021a.dtsi
284 +++ b/arch/arm/boot/dts/ls1021a.dtsi
285 @@ -74,17 +74,24 @@
286 compatible = "arm,cortex-a7";
287 device_type = "cpu";
288 reg = <0xf00>;
289 - clocks = <&cluster1_clk>;
290 + clocks = <&clockgen 1 0>;
291 };
292  
293 cpu@f01 {
294 compatible = "arm,cortex-a7";
295 device_type = "cpu";
296 reg = <0xf01>;
297 - clocks = <&cluster1_clk>;
298 + clocks = <&clockgen 1 0>;
299 };
300 };
301  
302 + sysclk: sysclk {
303 + compatible = "fixed-clock";
304 + #clock-cells = <0>;
305 + clock-frequency = <100000000>;
306 + clock-output-names = "sysclk";
307 + };
308 +
309 timer {
310 compatible = "arm,armv7-timer";
311 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
312 @@ -108,11 +115,11 @@
313 ranges;
314  
315 gic: interrupt-controller@1400000 {
316 - compatible = "arm,cortex-a7-gic";
317 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
318 #interrupt-cells = <3>;
319 interrupt-controller;
320 reg = <0x0 0x1401000 0x0 0x1000>,
321 - <0x0 0x1402000 0x0 0x1000>,
322 + <0x0 0x1402000 0x0 0x2000>,
323 <0x0 0x1404000 0x0 0x2000>,
324 <0x0 0x1406000 0x0 0x2000>;
325 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
326 @@ -120,14 +127,14 @@
327 };
328  
329 msi1: msi-controller@1570e00 {
330 - compatible = "fsl,1s1021a-msi";
331 + compatible = "fsl,ls1021a-msi";
332 reg = <0x0 0x1570e00 0x0 0x8>;
333 msi-controller;
334 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
335 };
336  
337 msi2: msi-controller@1570e08 {
338 - compatible = "fsl,1s1021a-msi";
339 + compatible = "fsl,ls1021a-msi";
340 reg = <0x0 0x1570e08 0x0 0x8>;
341 msi-controller;
342 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
343 @@ -137,11 +144,12 @@
344 compatible = "fsl,ifc", "simple-bus";
345 reg = <0x0 0x1530000 0x0 0x10000>;
346 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
347 + big-endian;
348 };
349  
350 dcfg: dcfg@1ee0000 {
351 compatible = "fsl,ls1021a-dcfg", "syscon";
352 - reg = <0x0 0x1ee0000 0x0 0x10000>;
353 + reg = <0x0 0x1ee0000 0x0 0x1000>;
354 big-endian;
355 };
356  
357 @@ -163,7 +171,7 @@
358 <0x0 0x20220520 0x0 0x4>;
359 reg-names = "ahci", "sata-ecc";
360 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
361 - clocks = <&platform_clk 1>;
362 + clocks = <&clockgen 4 1>;
363 dma-coherent;
364 status = "disabled";
365 };
366 @@ -214,41 +222,10 @@
367 };
368  
369 clockgen: clocking@1ee1000 {
370 - #address-cells = <1>;
371 - #size-cells = <1>;
372 - ranges = <0x0 0x0 0x1ee1000 0x10000>;
373 -
374 - sysclk: sysclk {
375 - compatible = "fixed-clock";
376 - #clock-cells = <0>;
377 - clock-output-names = "sysclk";
378 - };
379 -
380 - cga_pll1: pll@800 {
381 - compatible = "fsl,qoriq-core-pll-2.0";
382 - #clock-cells = <1>;
383 - reg = <0x800 0x10>;
384 - clocks = <&sysclk>;
385 - clock-output-names = "cga-pll1", "cga-pll1-div2",
386 - "cga-pll1-div4";
387 - };
388 -
389 - platform_clk: pll@c00 {
390 - compatible = "fsl,qoriq-core-pll-2.0";
391 - #clock-cells = <1>;
392 - reg = <0xc00 0x10>;
393 - clocks = <&sysclk>;
394 - clock-output-names = "platform-clk", "platform-clk-div2";
395 - };
396 -
397 - cluster1_clk: clk0c0@0 {
398 - compatible = "fsl,qoriq-core-mux-2.0";
399 - #clock-cells = <0>;
400 - reg = <0x0 0x10>;
401 - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
402 - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
403 - clock-output-names = "cluster1-clk";
404 - };
405 + compatible = "fsl,ls1021a-clockgen";
406 + reg = <0x0 0x1ee1000 0x0 0x1000>;
407 + #clock-cells = <2>;
408 + clocks = <&sysclk>;
409 };
410  
411 dspi0: dspi@2100000 {
412 @@ -258,7 +235,7 @@
413 reg = <0x0 0x2100000 0x0 0x10000>;
414 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
415 clock-names = "dspi";
416 - clocks = <&platform_clk 1>;
417 + clocks = <&clockgen 4 1>;
418 spi-num-chipselects = <6>;
419 big-endian;
420 status = "disabled";
421 @@ -271,12 +248,27 @@
422 reg = <0x0 0x2110000 0x0 0x10000>;
423 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
424 clock-names = "dspi";
425 - clocks = <&platform_clk 1>;
426 + clocks = <&clockgen 4 1>;
427 spi-num-chipselects = <6>;
428 big-endian;
429 status = "disabled";
430 };
431  
432 + qspi: quadspi@1550000 {
433 + compatible = "fsl,ls1021a-qspi";
434 + #address-cells = <1>;
435 + #size-cells = <0>;
436 + reg = <0x0 0x1550000 0x0 0x10000>,
437 + <0x0 0x40000000 0x0 0x4000000>;
438 + reg-names = "QuadSPI", "QuadSPI-memory";
439 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
440 + clock-names = "qspi_en", "qspi";
441 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
442 + big-endian;
443 + amba-base = <0x40000000>;
444 + status = "disabled";
445 + };
446 +
447 i2c0: i2c@2180000 {
448 compatible = "fsl,vf610-i2c";
449 #address-cells = <1>;
450 @@ -284,7 +276,7 @@
451 reg = <0x0 0x2180000 0x0 0x10000>;
452 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
453 clock-names = "i2c";
454 - clocks = <&platform_clk 1>;
455 + clocks = <&clockgen 4 1>;
456 status = "disabled";
457 };
458  
459 @@ -295,7 +287,7 @@
460 reg = <0x0 0x2190000 0x0 0x10000>;
461 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
462 clock-names = "i2c";
463 - clocks = <&platform_clk 1>;
464 + clocks = <&clockgen 4 1>;
465 status = "disabled";
466 };
467  
468 @@ -306,7 +298,7 @@
469 reg = <0x0 0x21a0000 0x0 0x10000>;
470 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
471 clock-names = "i2c";
472 - clocks = <&platform_clk 1>;
473 + clocks = <&clockgen 4 1>;
474 status = "disabled";
475 };
476  
477 @@ -399,7 +391,7 @@
478 compatible = "fsl,ls1021a-lpuart";
479 reg = <0x0 0x2960000 0x0 0x1000>;
480 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
481 - clocks = <&platform_clk 1>;
482 + clocks = <&clockgen 4 1>;
483 clock-names = "ipg";
484 status = "disabled";
485 };
486 @@ -408,7 +400,7 @@
487 compatible = "fsl,ls1021a-lpuart";
488 reg = <0x0 0x2970000 0x0 0x1000>;
489 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
490 - clocks = <&platform_clk 1>;
491 + clocks = <&clockgen 4 1>;
492 clock-names = "ipg";
493 status = "disabled";
494 };
495 @@ -417,7 +409,7 @@
496 compatible = "fsl,ls1021a-lpuart";
497 reg = <0x0 0x2980000 0x0 0x1000>;
498 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
499 - clocks = <&platform_clk 1>;
500 + clocks = <&clockgen 4 1>;
501 clock-names = "ipg";
502 status = "disabled";
503 };
504 @@ -426,7 +418,7 @@
505 compatible = "fsl,ls1021a-lpuart";
506 reg = <0x0 0x2990000 0x0 0x1000>;
507 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
508 - clocks = <&platform_clk 1>;
509 + clocks = <&clockgen 4 1>;
510 clock-names = "ipg";
511 status = "disabled";
512 };
513 @@ -435,16 +427,26 @@
514 compatible = "fsl,ls1021a-lpuart";
515 reg = <0x0 0x29a0000 0x0 0x1000>;
516 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
517 - clocks = <&platform_clk 1>;
518 + clocks = <&clockgen 4 1>;
519 clock-names = "ipg";
520 status = "disabled";
521 };
522  
523 + ftm0: ftm0@29d0000 {
524 + compatible = "fsl,ls1021a-ftm";
525 + reg = <0x0 0x29d0000 0x0 0x10000>,
526 + <0x0 0x1ee2140 0x0 0x4>;
527 + reg-names = "ftm", "FlexTimer1";
528 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
529 + big-endian;
530 + status = "okay";
531 + };
532 +
533 wdog0: watchdog@2ad0000 {
534 compatible = "fsl,imx21-wdt";
535 reg = <0x0 0x2ad0000 0x0 0x10000>;
536 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
537 - clocks = <&platform_clk 1>;
538 + clocks = <&clockgen 4 1>;
539 clock-names = "wdog-en";
540 big-endian;
541 };
542 @@ -454,8 +456,8 @@
543 compatible = "fsl,vf610-sai";
544 reg = <0x0 0x2b50000 0x0 0x10000>;
545 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
546 - clocks = <&platform_clk 1>, <&platform_clk 1>,
547 - <&platform_clk 1>, <&platform_clk 1>;
548 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
549 + <&clockgen 4 1>, <&clockgen 4 1>;
550 clock-names = "bus", "mclk1", "mclk2", "mclk3";
551 dma-names = "tx", "rx";
552 dmas = <&edma0 1 47>,
553 @@ -468,8 +470,8 @@
554 compatible = "fsl,vf610-sai";
555 reg = <0x0 0x2b60000 0x0 0x10000>;
556 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
557 - clocks = <&platform_clk 1>, <&platform_clk 1>,
558 - <&platform_clk 1>, <&platform_clk 1>;
559 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
560 + <&clockgen 4 1>, <&clockgen 4 1>;
561 clock-names = "bus", "mclk1", "mclk2", "mclk3";
562 dma-names = "tx", "rx";
563 dmas = <&edma0 1 45>,
564 @@ -489,16 +491,31 @@
565 dma-channels = <32>;
566 big-endian;
567 clock-names = "dmamux0", "dmamux1";
568 - clocks = <&platform_clk 1>,
569 - <&platform_clk 1>;
570 + clocks = <&clockgen 4 1>,
571 + <&clockgen 4 1>;
572 + };
573 +
574 + qdma: qdma@8390000 {
575 + compatible = "fsl,ls1021a-qdma";
576 + reg = <0x0 0x8398000 0x0 0x1000>, /* Controller regs */
577 + <0x0 0x8399000 0x0 0x1000>, /* Status regs */
578 + <0x0 0x839a000 0x0 0x2000>; /* Block regs */
579 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
580 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
581 + interrupt-names = "qdma-error", "qdma-queue";
582 + channels = <8>;
583 + queues = <2>;
584 + status-sizes = <64>;
585 + queue-sizes = <64 64>;
586 + big-endian;
587 };
588  
589 dcu: dcu@2ce0000 {
590 compatible = "fsl,ls1021a-dcu";
591 reg = <0x0 0x2ce0000 0x0 0x10000>;
592 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
593 - clocks = <&platform_clk 0>,
594 - <&platform_clk 0>;
595 + clocks = <&clockgen 4 0>,
596 + <&clockgen 4 0>;
597 clock-names = "dcu", "pix";
598 big-endian;
599 status = "disabled";
600 @@ -626,6 +643,8 @@
601 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
602 dr_mode = "host";
603 snps,quirk-frame-length-adjustment = <0x20>;
604 + configure-gfladj;
605 + dma-coherent;
606 snps,dis_rxdet_inp3_quirk;
607 };
608  
609 @@ -634,7 +653,9 @@
610 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
611 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
612 reg-names = "regs", "config";
613 - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
614 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
615 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
616 + interrupt-names = "pme", "aer";
617 fsl,pcie-scfg = <&scfg 0>;
618 #address-cells = <3>;
619 #size-cells = <2>;
620 @@ -643,7 +664,7 @@
621 bus-range = <0x0 0xff>;
622 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
623 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
624 - msi-parent = <&msi1>;
625 + msi-parent = <&msi1>, <&msi2>;
626 #interrupt-cells = <1>;
627 interrupt-map-mask = <0 0 0 7>;
628 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
629 @@ -657,7 +678,9 @@
630 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
631 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
632 reg-names = "regs", "config";
633 - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
634 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
635 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
636 + interrupt-names = "pme", "aer";
637 fsl,pcie-scfg = <&scfg 1>;
638 #address-cells = <3>;
639 #size-cells = <2>;
640 @@ -666,7 +689,7 @@
641 bus-range = <0x0 0xff>;
642 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
643 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
644 - msi-parent = <&msi2>;
645 + msi-parent = <&msi1>, <&msi2>;
646 #interrupt-cells = <1>;
647 interrupt-map-mask = <0 0 0 7>;
648 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
649 @@ -674,5 +697,45 @@
650 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
651 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
652 };
653 +
654 + can0: can@2a70000 {
655 + compatible = "fsl,ls1021ar2-flexcan";
656 + reg = <0x0 0x2a70000 0x0 0x1000>;
657 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
658 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
659 + clock-names = "ipg", "per";
660 + big-endian;
661 + status = "disabled";
662 + };
663 +
664 + can1: can@2a80000 {
665 + compatible = "fsl,ls1021ar2-flexcan";
666 + reg = <0x0 0x2a80000 0x0 0x1000>;
667 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
668 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
669 + clock-names = "ipg", "per";
670 + big-endian;
671 + status = "disabled";
672 + };
673 +
674 + can2: can@2a90000 {
675 + compatible = "fsl,ls1021ar2-flexcan";
676 + reg = <0x0 0x2a90000 0x0 0x1000>;
677 + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
678 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
679 + clock-names = "ipg", "per";
680 + big-endian;
681 + status = "disabled";
682 + };
683 +
684 + can3: can@2aa0000 {
685 + compatible = "fsl,ls1021ar2-flexcan";
686 + reg = <0x0 0x2aa0000 0x0 0x1000>;
687 + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
688 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
689 + clock-names = "ipg", "per";
690 + big-endian;
691 + status = "disabled";
692 + };
693 };
694 };
695 --- a/arch/arm/boot/dts/mt6580.dtsi
696 +++ b/arch/arm/boot/dts/mt6580.dtsi
697 @@ -91,7 +91,7 @@
698 #interrupt-cells = <3>;
699 interrupt-parent = <&gic>;
700 reg = <0x10211000 0x1000>,
701 - <0x10212000 0x1000>,
702 + <0x10212000 0x2000>,
703 <0x10214000 0x2000>,
704 <0x10216000 0x2000>;
705 };
706 --- a/arch/arm/boot/dts/mt6589.dtsi
707 +++ b/arch/arm/boot/dts/mt6589.dtsi
708 @@ -102,7 +102,7 @@
709 #interrupt-cells = <3>;
710 interrupt-parent = <&gic>;
711 reg = <0x10211000 0x1000>,
712 - <0x10212000 0x1000>,
713 + <0x10212000 0x2000>,
714 <0x10214000 0x2000>,
715 <0x10216000 0x2000>;
716 };
717 --- a/arch/arm/boot/dts/mt8127.dtsi
718 +++ b/arch/arm/boot/dts/mt8127.dtsi
719 @@ -129,7 +129,7 @@
720 #interrupt-cells = <3>;
721 interrupt-parent = <&gic>;
722 reg = <0 0x10211000 0 0x1000>,
723 - <0 0x10212000 0 0x1000>,
724 + <0 0x10212000 0 0x2000>,
725 <0 0x10214000 0 0x2000>,
726 <0 0x10216000 0 0x2000>;
727 };
728 --- a/arch/arm/boot/dts/mt8135.dtsi
729 +++ b/arch/arm/boot/dts/mt8135.dtsi
730 @@ -221,7 +221,7 @@
731 #interrupt-cells = <3>;
732 interrupt-parent = <&gic>;
733 reg = <0 0x10211000 0 0x1000>,
734 - <0 0x10212000 0 0x1000>,
735 + <0 0x10212000 0 0x2000>,
736 <0 0x10214000 0 0x2000>,
737 <0 0x10216000 0 0x2000>;
738 };
739 --- a/arch/arm/boot/dts/rk3288.dtsi
740 +++ b/arch/arm/boot/dts/rk3288.dtsi
741 @@ -1109,7 +1109,7 @@
742 #address-cells = <0>;
743  
744 reg = <0xffc01000 0x1000>,
745 - <0xffc02000 0x1000>,
746 + <0xffc02000 0x2000>,
747 <0xffc04000 0x2000>,
748 <0xffc06000 0x2000>;
749 interrupts = <GIC_PPI 9 0xf04>;
750 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
751 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
752 @@ -791,7 +791,7 @@
753 gic: interrupt-controller@01c81000 {
754 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
755 reg = <0x01c81000 0x1000>,
756 - <0x01c82000 0x1000>,
757 + <0x01c82000 0x2000>,
758 <0x01c84000 0x2000>,
759 <0x01c86000 0x2000>;
760 interrupt-controller;
761 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
762 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
763 @@ -1685,9 +1685,9 @@
764 };
765  
766 gic: interrupt-controller@01c81000 {
767 - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
768 + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
769 reg = <0x01c81000 0x1000>,
770 - <0x01c82000 0x1000>,
771 + <0x01c82000 0x2000>,
772 <0x01c84000 0x2000>,
773 <0x01c86000 0x2000>;
774 interrupt-controller;
775 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
776 +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
777 @@ -488,7 +488,7 @@
778 gic: interrupt-controller@01c81000 {
779 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
780 reg = <0x01c81000 0x1000>,
781 - <0x01c82000 0x1000>,
782 + <0x01c82000 0x2000>,
783 <0x01c84000 0x2000>,
784 <0x01c86000 0x2000>;
785 interrupt-controller;
786 --- a/arch/arm/boot/dts/sun9i-a80.dtsi
787 +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
788 @@ -613,7 +613,7 @@
789 gic: interrupt-controller@01c41000 {
790 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
791 reg = <0x01c41000 0x1000>,
792 - <0x01c42000 0x1000>,
793 + <0x01c42000 0x2000>,
794 <0x01c44000 0x2000>,
795 <0x01c46000 0x2000>;
796 interrupt-controller;
797 --- a/arch/arm64/boot/dts/freescale/Makefile
798 +++ b/arch/arm64/boot/dts/freescale/Makefile
799 @@ -1,8 +1,25 @@
800 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
801 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
802 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
803 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
804 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
805 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
806 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
807 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
808 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
809 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
810 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
811 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
812 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
813 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
814 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
815 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
816 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
817 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
818 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
819 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
820 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
821 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
822  
823 always := $(dtb-y)
824 subdir-y := $(dts-dirs)
825 --- /dev/null
826 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
827 @@ -0,0 +1,123 @@
828 +/*
829 + * Device Tree file for NXP LS1012A 2G5RDB Board.
830 + *
831 + * Copyright 2017 NXP
832 + *
833 + * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
834 + *
835 + * This file is dual-licensed: you can use it either under the terms
836 + * of the GPLv2 or the X11 license, at your option. Note that this dual
837 + * licensing only applies to this file, and not this project as a
838 + * whole.
839 + *
840 + * a) This library is free software; you can redistribute it and/or
841 + * modify it under the terms of the GNU General Public License as
842 + * published by the Free Software Foundation; either version 2 of the
843 + * License, or (at your option) any later version.
844 + *
845 + * This library is distributed in the hope that it will be useful,
846 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
847 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
848 + * GNU General Public License for more details.
849 + *
850 + * Or, alternatively,
851 + *
852 + * b) Permission is hereby granted, free of charge, to any person
853 + * obtaining a copy of this software and associated documentation
854 + * files (the "Software"), to deal in the Software without
855 + * restriction, including without limitation the rights to use,
856 + * copy, modify, merge, publish, distribute, sublicense, and/or
857 + * sell copies of the Software, and to permit persons to whom the
858 + * Software is furnished to do so, subject to the following
859 + * conditions:
860 + *
861 + * The above copyright notice and this permission notice shall be
862 + * included in all copies or substantial portions of the Software.
863 + *
864 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
865 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
866 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
867 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
868 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
869 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
870 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
871 + * OTHER DEALINGS IN THE SOFTWARE.
872 + */
873 +/dts-v1/;
874 +
875 +#include "fsl-ls1012a.dtsi"
876 +
877 +/ {
878 + model = "LS1012A 2G5RDB Board";
879 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
880 +
881 + aliases {
882 + ethernet0 = &pfe_mac0;
883 + ethernet1 = &pfe_mac1;
884 + };
885 +};
886 +
887 +&duart0 {
888 + status = "okay";
889 +};
890 +
891 +&i2c0 {
892 + status = "okay";
893 +};
894 +
895 +&qspi {
896 + num-cs = <2>;
897 + bus-num = <0>;
898 + status = "okay";
899 +
900 + qflash0: s25fs512s@0 {
901 + compatible = "spansion,m25p80";
902 + #address-cells = <1>;
903 + #size-cells = <1>;
904 + spi-max-frequency = <20000000>;
905 + m25p,fast-read;
906 + reg = <0>;
907 + };
908 +};
909 +
910 +&sata {
911 + status = "okay";
912 +};
913 +
914 +&pfe {
915 + status = "okay";
916 + #address-cells = <1>;
917 + #size-cells = <0>;
918 +
919 + ethernet@0 {
920 + compatible = "fsl,pfe-gemac-port";
921 + #address-cells = <1>;
922 + #size-cells = <0>;
923 + reg = <0x0>; /* GEM_ID */
924 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
925 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
926 + fsl,mdio-mux-val = <0x0>;
927 + phy-mode = "sgmii-2500";
928 + fsl,pfe-phy-if-flags = <0x0>;
929 +
930 + mdio@0 {
931 + reg = <0x1>; /* enabled/disabled */
932 + };
933 + };
934 +
935 + ethernet@1 {
936 + compatible = "fsl,pfe-gemac-port";
937 + #address-cells = <1>;
938 + #size-cells = <0>;
939 + reg = <0x1>; /* GEM_ID */
940 + fsl,gemac-bus-id = < 0x0>; /* BUS_ID */
941 + fsl,gemac-phy-id = < 0x2>; /* PHY_ID */
942 + fsl,mdio-mux-val = <0x0>;
943 + phy-mode = "sgmii-2500";
944 + fsl,pfe-phy-if-flags = <0x0>;
945 +
946 + mdio@0 {
947 + reg = <0x0>; /* enabled/disabled */
948 + };
949 + };
950 +};
951 --- /dev/null
952 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
953 @@ -0,0 +1,177 @@
954 +/*
955 + * Device Tree file for Freescale LS1012A Freedom Board.
956 + *
957 + * Copyright 2016 Freescale Semiconductor, Inc.
958 + *
959 + * This file is dual-licensed: you can use it either under the terms
960 + * of the GPLv2 or the X11 license, at your option. Note that this dual
961 + * licensing only applies to this file, and not this project as a
962 + * whole.
963 + *
964 + * a) This library is free software; you can redistribute it and/or
965 + * modify it under the terms of the GNU General Public License as
966 + * published by the Free Software Foundation; either version 2 of the
967 + * License, or (at your option) any later version.
968 + *
969 + * This library is distributed in the hope that it will be useful,
970 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
971 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
972 + * GNU General Public License for more details.
973 + *
974 + * Or, alternatively,
975 + *
976 + * b) Permission is hereby granted, free of charge, to any person
977 + * obtaining a copy of this software and associated documentation
978 + * files (the "Software"), to deal in the Software without
979 + * restriction, including without limitation the rights to use,
980 + * copy, modify, merge, publish, distribute, sublicense, and/or
981 + * sell copies of the Software, and to permit persons to whom the
982 + * Software is furnished to do so, subject to the following
983 + * conditions:
984 + *
985 + * The above copyright notice and this permission notice shall be
986 + * included in all copies or substantial portions of the Software.
987 + *
988 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
989 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
990 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
991 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
992 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
993 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
994 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
995 + * OTHER DEALINGS IN THE SOFTWARE.
996 + */
997 +/dts-v1/;
998 +
999 +#include "fsl-ls1012a.dtsi"
1000 +
1001 +/ {
1002 + model = "LS1012A Freedom Board";
1003 + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
1004 +
1005 + aliases {
1006 + ethernet0 = &pfe_mac0;
1007 + ethernet1 = &pfe_mac1;
1008 + };
1009 +
1010 + sys_mclk: clock-mclk {
1011 + compatible = "fixed-clock";
1012 + #clock-cells = <0>;
1013 + clock-frequency = <25000000>;
1014 + };
1015 +
1016 + reg_1p8v: regulator-1p8v {
1017 + compatible = "regulator-fixed";
1018 + regulator-name = "1P8V";
1019 + regulator-min-microvolt = <1800000>;
1020 + regulator-max-microvolt = <1800000>;
1021 + regulator-always-on;
1022 + };
1023 +
1024 + sound {
1025 + compatible = "simple-audio-card";
1026 + simple-audio-card,format = "i2s";
1027 + simple-audio-card,widgets =
1028 + "Microphone", "Microphone Jack",
1029 + "Headphone", "Headphone Jack",
1030 + "Speaker", "Speaker Ext",
1031 + "Line", "Line In Jack";
1032 + simple-audio-card,routing =
1033 + "MIC_IN", "Microphone Jack",
1034 + "Microphone Jack", "Mic Bias",
1035 + "LINE_IN", "Line In Jack",
1036 + "Headphone Jack", "HP_OUT",
1037 + "Speaker Ext", "LINE_OUT";
1038 +
1039 + simple-audio-card,cpu {
1040 + sound-dai = <&sai2>;
1041 + frame-master;
1042 + bitclock-master;
1043 + };
1044 +
1045 + simple-audio-card,codec {
1046 + sound-dai = <&codec>;
1047 + frame-master;
1048 + bitclock-master;
1049 + system-clock-frequency = <25000000>;
1050 + };
1051 + };
1052 +};
1053 +
1054 +&duart0 {
1055 + status = "okay";
1056 +};
1057 +
1058 +&i2c0 {
1059 + status = "okay";
1060 +
1061 + codec: sgtl5000@a {
1062 + #sound-dai-cells = <0>;
1063 + compatible = "fsl,sgtl5000";
1064 + reg = <0xa>;
1065 + VDDA-supply = <&reg_1p8v>;
1066 + VDDIO-supply = <&reg_1p8v>;
1067 + clocks = <&sys_mclk>;
1068 + };
1069 +};
1070 +
1071 +&qspi {
1072 + num-cs = <1>;
1073 + bus-num = <0>;
1074 + status = "okay";
1075 +
1076 + qflash0: s25fs512s@0 {
1077 + compatible = "spansion,m25p80";
1078 + #address-cells = <1>;
1079 + #size-cells = <1>;
1080 + m25p,fast-read;
1081 + spi-max-frequency = <20000000>;
1082 + reg = <0>;
1083 + };
1084 +};
1085 +
1086 +&pfe {
1087 + status = "okay";
1088 + #address-cells = <1>;
1089 + #size-cells = <0>;
1090 +
1091 + ethernet@0 {
1092 + compatible = "fsl,pfe-gemac-port";
1093 + #address-cells = <1>;
1094 + #size-cells = <0>;
1095 + reg = <0x0>; /* GEM_ID */
1096 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1097 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1098 + fsl,mdio-mux-val = <0x0>;
1099 + phy-mode = "sgmii";
1100 + fsl,pfe-phy-if-flags = <0x0>;
1101 +
1102 + mdio@0 {
1103 + reg = <0x1>; /* enabled/disabled */
1104 + };
1105 + };
1106 +
1107 + ethernet@1 {
1108 + compatible = "fsl,pfe-gemac-port";
1109 + #address-cells = <1>;
1110 + #size-cells = <0>;
1111 + reg = <0x1>; /* GEM_ID */
1112 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1113 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1114 + fsl,mdio-mux-val = <0x0>;
1115 + phy-mode = "sgmii";
1116 + fsl,pfe-phy-if-flags = <0x0>;
1117 +
1118 + mdio@0 {
1119 + reg = <0x0>; /* enabled/disabled */
1120 + };
1121 + };
1122 +};
1123 +
1124 +&sai2 {
1125 + status = "okay";
1126 +};
1127 +
1128 +&sata {
1129 + status = "okay";
1130 +};
1131 --- /dev/null
1132 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
1133 @@ -0,0 +1,202 @@
1134 +/*
1135 + * Device Tree file for Freescale LS1012A QDS Board.
1136 + *
1137 + * Copyright 2016 Freescale Semiconductor, Inc.
1138 + *
1139 + * This file is dual-licensed: you can use it either under the terms
1140 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1141 + * licensing only applies to this file, and not this project as a
1142 + * whole.
1143 + *
1144 + * a) This library is free software; you can redistribute it and/or
1145 + * modify it under the terms of the GNU General Public License as
1146 + * published by the Free Software Foundation; either version 2 of the
1147 + * License, or (at your option) any later version.
1148 + *
1149 + * This library is distributed in the hope that it will be useful,
1150 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1151 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1152 + * GNU General Public License for more details.
1153 + *
1154 + * Or, alternatively,
1155 + *
1156 + * b) Permission is hereby granted, free of charge, to any person
1157 + * obtaining a copy of this software and associated documentation
1158 + * files (the "Software"), to deal in the Software without
1159 + * restriction, including without limitation the rights to use,
1160 + * copy, modify, merge, publish, distribute, sublicense, and/or
1161 + * sell copies of the Software, and to permit persons to whom the
1162 + * Software is furnished to do so, subject to the following
1163 + * conditions:
1164 + *
1165 + * The above copyright notice and this permission notice shall be
1166 + * included in all copies or substantial portions of the Software.
1167 + *
1168 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1169 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1170 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1171 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1172 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1173 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1174 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1175 + * OTHER DEALINGS IN THE SOFTWARE.
1176 + */
1177 +/dts-v1/;
1178 +
1179 +#include "fsl-ls1012a.dtsi"
1180 +
1181 +/ {
1182 + model = "LS1012A QDS Board";
1183 + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
1184 +
1185 + aliases {
1186 + ethernet0 = &pfe_mac0;
1187 + ethernet1 = &pfe_mac1;
1188 + };
1189 +
1190 + sys_mclk: clock-mclk {
1191 + compatible = "fixed-clock";
1192 + #clock-cells = <0>;
1193 + clock-frequency = <24576000>;
1194 + };
1195 +
1196 + reg_3p3v: regulator-3p3v {
1197 + compatible = "regulator-fixed";
1198 + regulator-name = "3P3V";
1199 + regulator-min-microvolt = <3300000>;
1200 + regulator-max-microvolt = <3300000>;
1201 + regulator-always-on;
1202 + };
1203 +
1204 + sound {
1205 + compatible = "simple-audio-card";
1206 + simple-audio-card,format = "i2s";
1207 + simple-audio-card,widgets =
1208 + "Microphone", "Microphone Jack",
1209 + "Headphone", "Headphone Jack",
1210 + "Speaker", "Speaker Ext",
1211 + "Line", "Line In Jack";
1212 + simple-audio-card,routing =
1213 + "MIC_IN", "Microphone Jack",
1214 + "Microphone Jack", "Mic Bias",
1215 + "LINE_IN", "Line In Jack",
1216 + "Headphone Jack", "HP_OUT",
1217 + "Speaker Ext", "LINE_OUT";
1218 +
1219 + simple-audio-card,cpu {
1220 + sound-dai = <&sai2>;
1221 + frame-master;
1222 + bitclock-master;
1223 + };
1224 +
1225 + simple-audio-card,codec {
1226 + sound-dai = <&codec>;
1227 + frame-master;
1228 + bitclock-master;
1229 + system-clock-frequency = <24576000>;
1230 + };
1231 + };
1232 +};
1233 +
1234 +&pcie {
1235 + status = "okay";
1236 +};
1237 +
1238 +&duart0 {
1239 + status = "okay";
1240 +};
1241 +
1242 +&i2c0 {
1243 + status = "okay";
1244 +
1245 + pca9547@77 {
1246 + compatible = "nxp,pca9547";
1247 + reg = <0x77>;
1248 + #address-cells = <1>;
1249 + #size-cells = <0>;
1250 +
1251 + i2c@4 {
1252 + #address-cells = <1>;
1253 + #size-cells = <0>;
1254 + reg = <0x4>;
1255 +
1256 + codec: sgtl5000@a {
1257 + #sound-dai-cells = <0>;
1258 + compatible = "fsl,sgtl5000";
1259 + reg = <0xa>;
1260 + VDDA-supply = <&reg_3p3v>;
1261 + VDDIO-supply = <&reg_3p3v>;
1262 + clocks = <&sys_mclk>;
1263 + };
1264 + };
1265 + };
1266 +};
1267 +
1268 +&qspi {
1269 + num-cs = <2>;
1270 + bus-num = <0>;
1271 + status = "okay";
1272 +
1273 + qflash0: s25fs512s@0 {
1274 + compatible = "spansion,m25p80";
1275 + #address-cells = <1>;
1276 + #size-cells = <1>;
1277 + spi-max-frequency = <20000000>;
1278 + m25p,fast-read;
1279 + reg = <0>;
1280 + };
1281 +};
1282 +
1283 +&pfe {
1284 + status = "okay";
1285 + #address-cells = <1>;
1286 + #size-cells = <0>;
1287 +
1288 + ethernet@0 {
1289 + compatible = "fsl,pfe-gemac-port";
1290 + #address-cells = <1>;
1291 + #size-cells = <0>;
1292 + reg = <0x0>; /* GEM_ID */
1293 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1294 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1295 + fsl,mdio-mux-val = <0x2>;
1296 + phy-mode = "sgmii-2500";
1297 + fsl,pfe-phy-if-flags = <0x0>;
1298 +
1299 + mdio@0 {
1300 + reg = <0x1>; /* enabled/disabled */
1301 + };
1302 + };
1303 +
1304 + ethernet@1 {
1305 + compatible = "fsl,pfe-gemac-port";
1306 + #address-cells = <1>;
1307 + #size-cells = <0>;
1308 + reg = <0x1>; /* GEM_ID */
1309 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1310 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1311 + fsl,mdio-mux-val = <0x3>;
1312 + phy-mode = "sgmii-2500";
1313 + fsl,pfe-phy-if-flags = <0x0>;
1314 +
1315 + mdio@0 {
1316 + reg = <0x0>; /* enabled/disabled */
1317 + };
1318 + };
1319 +};
1320 +
1321 +&sai2 {
1322 + status = "okay";
1323 +};
1324 +
1325 +&sata {
1326 + status = "okay";
1327 +};
1328 +
1329 +&esdhc0 {
1330 + status = "okay";
1331 +};
1332 +
1333 +&esdhc1 {
1334 + status = "okay";
1335 +};
1336 --- /dev/null
1337 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1338 @@ -0,0 +1,138 @@
1339 +/*
1340 + * Device Tree file for Freescale LS1012A RDB Board.
1341 + *
1342 + * Copyright 2016 Freescale Semiconductor, Inc.
1343 + *
1344 + * This file is dual-licensed: you can use it either under the terms
1345 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1346 + * licensing only applies to this file, and not this project as a
1347 + * whole.
1348 + *
1349 + * a) This library is free software; you can redistribute it and/or
1350 + * modify it under the terms of the GNU General Public License as
1351 + * published by the Free Software Foundation; either version 2 of the
1352 + * License, or (at your option) any later version.
1353 + *
1354 + * This library is distributed in the hope that it will be useful,
1355 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1356 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1357 + * GNU General Public License for more details.
1358 + *
1359 + * Or, alternatively,
1360 + *
1361 + * b) Permission is hereby granted, free of charge, to any person
1362 + * obtaining a copy of this software and associated documentation
1363 + * files (the "Software"), to deal in the Software without
1364 + * restriction, including without limitation the rights to use,
1365 + * copy, modify, merge, publish, distribute, sublicense, and/or
1366 + * sell copies of the Software, and to permit persons to whom the
1367 + * Software is furnished to do so, subject to the following
1368 + * conditions:
1369 + *
1370 + * The above copyright notice and this permission notice shall be
1371 + * included in all copies or substantial portions of the Software.
1372 + *
1373 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1374 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1375 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1376 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1377 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1378 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1379 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1380 + * OTHER DEALINGS IN THE SOFTWARE.
1381 + */
1382 +/dts-v1/;
1383 +
1384 +#include "fsl-ls1012a.dtsi"
1385 +
1386 +/ {
1387 + model = "LS1012A RDB Board";
1388 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
1389 +
1390 + aliases {
1391 + ethernet0 = &pfe_mac0;
1392 + ethernet1 = &pfe_mac1;
1393 + };
1394 +};
1395 +
1396 +&pcie {
1397 + status = "okay";
1398 +};
1399 +
1400 +&duart0 {
1401 + status = "okay";
1402 +};
1403 +
1404 +&i2c0 {
1405 + status = "okay";
1406 +};
1407 +
1408 +&qspi {
1409 + num-cs = <2>;
1410 + bus-num = <0>;
1411 + status = "okay";
1412 +
1413 + qflash0: s25fs512s@0 {
1414 + compatible = "spansion,m25p80";
1415 + #address-cells = <1>;
1416 + #size-cells = <1>;
1417 + spi-max-frequency = <20000000>;
1418 + m25p,fast-read;
1419 + reg = <0>;
1420 + };
1421 +};
1422 +
1423 +&sata {
1424 + status = "okay";
1425 +};
1426 +
1427 +&esdhc0 {
1428 + sd-uhs-sdr104;
1429 + sd-uhs-sdr50;
1430 + sd-uhs-sdr25;
1431 + sd-uhs-sdr12;
1432 + status = "okay";
1433 +};
1434 +
1435 +&esdhc1 {
1436 + mmc-hs200-1_8v;
1437 + status = "okay";
1438 +};
1439 +
1440 +&pfe {
1441 + status = "okay";
1442 + #address-cells = <1>;
1443 + #size-cells = <0>;
1444 +
1445 + ethernet@0 {
1446 + compatible = "fsl,pfe-gemac-port";
1447 + #address-cells = <1>;
1448 + #size-cells = <0>;
1449 + reg = <0x0>; /* GEM_ID */
1450 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1451 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1452 + fsl,mdio-mux-val = <0x0>;
1453 + phy-mode = "sgmii";
1454 + fsl,pfe-phy-if-flags = <0x0>;
1455 +
1456 + mdio@0 {
1457 + reg = <0x1>; /* enabled/disabled */
1458 + };
1459 + };
1460 +
1461 + ethernet@1 {
1462 + compatible = "fsl,pfe-gemac-port";
1463 + #address-cells = <1>;
1464 + #size-cells = <0>;
1465 + reg = <0x1>; /* GEM_ID */
1466 + fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
1467 + fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
1468 + fsl,mdio-mux-val = <0x0>;
1469 + phy-mode = "rgmii-txid";
1470 + fsl,pfe-phy-if-flags = <0x0>;
1471 +
1472 + mdio@0 {
1473 + reg = <0x0>; /* enabled/disabled */
1474 + };
1475 + };
1476 +};
1477 --- /dev/null
1478 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1479 @@ -0,0 +1,602 @@
1480 +/*
1481 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
1482 + *
1483 + * Copyright 2016 Freescale Semiconductor, Inc.
1484 + *
1485 + * This file is dual-licensed: you can use it either under the terms
1486 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1487 + * licensing only applies to this file, and not this project as a
1488 + * whole.
1489 + *
1490 + * a) This library is free software; you can redistribute it and/or
1491 + * modify it under the terms of the GNU General Public License as
1492 + * published by the Free Software Foundation; either version 2 of the
1493 + * License, or (at your option) any later version.
1494 + *
1495 + * This library is distributed in the hope that it will be useful,
1496 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1497 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1498 + * GNU General Public License for more details.
1499 + *
1500 + * Or, alternatively,
1501 + *
1502 + * b) Permission is hereby granted, free of charge, to any person
1503 + * obtaining a copy of this software and associated documentation
1504 + * files (the "Software"), to deal in the Software without
1505 + * restriction, including without limitation the rights to use,
1506 + * copy, modify, merge, publish, distribute, sublicense, and/or
1507 + * sell copies of the Software, and to permit persons to whom the
1508 + * Software is furnished to do so, subject to the following
1509 + * conditions:
1510 + *
1511 + * The above copyright notice and this permission notice shall be
1512 + * included in all copies or substantial portions of the Software.
1513 + *
1514 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1515 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1516 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1517 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1518 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1519 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1520 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1521 + * OTHER DEALINGS IN THE SOFTWARE.
1522 + */
1523 +
1524 +#include <dt-bindings/interrupt-controller/arm-gic.h>
1525 +#include <dt-bindings/thermal/thermal.h>
1526 +
1527 +/ {
1528 + compatible = "fsl,ls1012a";
1529 + interrupt-parent = <&gic>;
1530 + #address-cells = <2>;
1531 + #size-cells = <2>;
1532 +
1533 + aliases {
1534 + crypto = &crypto;
1535 + rtic_a = &rtic_a;
1536 + rtic_b = &rtic_b;
1537 + rtic_c = &rtic_c;
1538 + rtic_d = &rtic_d;
1539 + sec_mon = &sec_mon;
1540 + };
1541 +
1542 + cpus {
1543 + #address-cells = <1>;
1544 + #size-cells = <0>;
1545 +
1546 + cpu0: cpu@0 {
1547 + device_type = "cpu";
1548 + compatible = "arm,cortex-a53";
1549 + reg = <0x0>;
1550 + clocks = <&clockgen 1 0>;
1551 + #cooling-cells = <2>;
1552 + cpu-idle-states = <&CPU_PH20>;
1553 + };
1554 + };
1555 +
1556 + idle-states {
1557 + /*
1558 + * PSCI node is not added default, U-boot will add missing
1559 + * parts if it determines to use PSCI.
1560 + */
1561 + entry-method = "arm,psci";
1562 +
1563 + CPU_PH20: cpu-ph20 {
1564 + compatible = "arm,idle-state";
1565 + idle-state-name = "PH20";
1566 + arm,psci-suspend-param = <0x0>;
1567 + entry-latency-us = <1000>;
1568 + exit-latency-us = <1000>;
1569 + min-residency-us = <3000>;
1570 + };
1571 + };
1572 +
1573 + sysclk: sysclk {
1574 + compatible = "fixed-clock";
1575 + #clock-cells = <0>;
1576 + clock-frequency = <125000000>;
1577 + clock-output-names = "sysclk";
1578 + };
1579 +
1580 + coreclk: coreclk {
1581 + compatible = "fixed-clock";
1582 + #clock-cells = <0>;
1583 + clock-frequency = <100000000>;
1584 + clock-output-names = "coreclk";
1585 + };
1586 +
1587 + timer {
1588 + compatible = "arm,armv8-timer";
1589 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
1590 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
1591 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
1592 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
1593 + };
1594 +
1595 + pmu {
1596 + compatible = "arm,armv8-pmuv3";
1597 + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1598 + };
1599 +
1600 + gic: interrupt-controller@1400000 {
1601 + compatible = "arm,gic-400";
1602 + #interrupt-cells = <3>;
1603 + interrupt-controller;
1604 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
1605 + <0x0 0x1402000 0 0x2000>, /* GICC */
1606 + <0x0 0x1404000 0 0x2000>, /* GICH */
1607 + <0x0 0x1406000 0 0x2000>; /* GICV */
1608 + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
1609 + };
1610 +
1611 + reboot {
1612 + compatible = "syscon-reboot";
1613 + regmap = <&dcfg>;
1614 + offset = <0xb0>;
1615 + mask = <0x02>;
1616 + };
1617 +
1618 + soc {
1619 + compatible = "simple-bus";
1620 + #address-cells = <2>;
1621 + #size-cells = <2>;
1622 + ranges;
1623 +
1624 + scfg: scfg@1570000 {
1625 + compatible = "fsl,ls1012a-scfg", "syscon";
1626 + reg = <0x0 0x1570000 0x0 0x10000>;
1627 + big-endian;
1628 + };
1629 +
1630 + crypto: crypto@1700000 {
1631 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
1632 + "fsl,sec-v4.0";
1633 + fsl,sec-era = <8>;
1634 + #address-cells = <1>;
1635 + #size-cells = <1>;
1636 + ranges = <0x0 0x00 0x1700000 0x100000>;
1637 + reg = <0x00 0x1700000 0x0 0x100000>;
1638 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1639 +
1640 + sec_jr0: jr@10000 {
1641 + compatible = "fsl,sec-v5.4-job-ring",
1642 + "fsl,sec-v5.0-job-ring",
1643 + "fsl,sec-v4.0-job-ring";
1644 + reg = <0x10000 0x10000>;
1645 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1646 + };
1647 +
1648 + sec_jr1: jr@20000 {
1649 + compatible = "fsl,sec-v5.4-job-ring",
1650 + "fsl,sec-v5.0-job-ring",
1651 + "fsl,sec-v4.0-job-ring";
1652 + reg = <0x20000 0x10000>;
1653 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1654 + };
1655 +
1656 + sec_jr2: jr@30000 {
1657 + compatible = "fsl,sec-v5.4-job-ring",
1658 + "fsl,sec-v5.0-job-ring",
1659 + "fsl,sec-v4.0-job-ring";
1660 + reg = <0x30000 0x10000>;
1661 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1662 + };
1663 +
1664 + sec_jr3: jr@40000 {
1665 + compatible = "fsl,sec-v5.4-job-ring",
1666 + "fsl,sec-v5.0-job-ring",
1667 + "fsl,sec-v4.0-job-ring";
1668 + reg = <0x40000 0x10000>;
1669 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1670 + };
1671 +
1672 + caam-dma {
1673 + compatible = "fsl,sec-v5.4-dma",
1674 + "fsl,sec-v5.0-dma",
1675 + "fsl,sec-v4.0-dma";
1676 + };
1677 +
1678 + rtic@60000 {
1679 + compatible = "fsl,sec-v5.4-rtic",
1680 + "fsl,sec-v5.0-rtic",
1681 + "fsl,sec-v4.0-rtic";
1682 + #address-cells = <1>;
1683 + #size-cells = <1>;
1684 + reg = <0x60000 0x100 0x60e00 0x18>;
1685 + ranges = <0x0 0x60100 0x500>;
1686 +
1687 + rtic_a: rtic-a@0 {
1688 + compatible = "fsl,sec-v5.4-rtic-memory",
1689 + "fsl,sec-v5.0-rtic-memory",
1690 + "fsl,sec-v4.0-rtic-memory";
1691 + reg = <0x00 0x20 0x100 0x100>;
1692 + };
1693 +
1694 + rtic_b: rtic-b@20 {
1695 + compatible = "fsl,sec-v5.4-rtic-memory",
1696 + "fsl,sec-v5.0-rtic-memory",
1697 + "fsl,sec-v4.0-rtic-memory";
1698 + reg = <0x20 0x20 0x200 0x100>;
1699 + };
1700 +
1701 + rtic_c: rtic-c@40 {
1702 + compatible = "fsl,sec-v5.4-rtic-memory",
1703 + "fsl,sec-v5.0-rtic-memory",
1704 + "fsl,sec-v4.0-rtic-memory";
1705 + reg = <0x40 0x20 0x300 0x100>;
1706 + };
1707 +
1708 + rtic_d: rtic-d@60 {
1709 + compatible = "fsl,sec-v5.4-rtic-memory",
1710 + "fsl,sec-v5.0-rtic-memory",
1711 + "fsl,sec-v4.0-rtic-memory";
1712 + reg = <0x60 0x20 0x400 0x100>;
1713 + };
1714 + };
1715 + };
1716 +
1717 + sec_mon: sec_mon@1e90000 {
1718 + compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
1719 + "fsl,sec-v4.0-mon";
1720 + reg = <0x0 0x1e90000 0x0 0x10000>;
1721 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
1722 + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1723 + };
1724 +
1725 + dcfg: dcfg@1ee0000 {
1726 + compatible = "fsl,ls1012a-dcfg",
1727 + "syscon";
1728 + reg = <0x0 0x1ee0000 0x0 0x10000>;
1729 + big-endian;
1730 + };
1731 +
1732 + clockgen: clocking@1ee1000 {
1733 + compatible = "fsl,ls1012a-clockgen";
1734 + reg = <0x0 0x1ee1000 0x0 0x1000>;
1735 + #clock-cells = <2>;
1736 + clocks = <&sysclk &coreclk>;
1737 + clock-names = "sysclk", "coreclk";
1738 + };
1739 +
1740 + tmu: tmu@1f00000 {
1741 + compatible = "fsl,qoriq-tmu";
1742 + reg = <0x0 0x1f00000 0x0 0x10000>;
1743 + interrupts = <0 33 0x4>;
1744 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
1745 + fsl,tmu-calibration = <0x00000000 0x00000026
1746 + 0x00000001 0x0000002d
1747 + 0x00000002 0x00000032
1748 + 0x00000003 0x00000039
1749 + 0x00000004 0x0000003f
1750 + 0x00000005 0x00000046
1751 + 0x00000006 0x0000004d
1752 + 0x00000007 0x00000054
1753 + 0x00000008 0x0000005a
1754 + 0x00000009 0x00000061
1755 + 0x0000000a 0x0000006a
1756 + 0x0000000b 0x00000071
1757 +
1758 + 0x00010000 0x00000025
1759 + 0x00010001 0x0000002c
1760 + 0x00010002 0x00000035
1761 + 0x00010003 0x0000003d
1762 + 0x00010004 0x00000045
1763 + 0x00010005 0x0000004e
1764 + 0x00010006 0x00000057
1765 + 0x00010007 0x00000061
1766 + 0x00010008 0x0000006b
1767 + 0x00010009 0x00000076
1768 +
1769 + 0x00020000 0x00000029
1770 + 0x00020001 0x00000033
1771 + 0x00020002 0x0000003d
1772 + 0x00020003 0x00000049
1773 + 0x00020004 0x00000056
1774 + 0x00020005 0x00000061
1775 + 0x00020006 0x0000006d
1776 +
1777 + 0x00030000 0x00000021
1778 + 0x00030001 0x0000002a
1779 + 0x00030002 0x0000003c
1780 + 0x00030003 0x0000004e>;
1781 + big-endian;
1782 + #thermal-sensor-cells = <1>;
1783 + };
1784 +
1785 + thermal-zones {
1786 + cpu_thermal: cpu-thermal {
1787 + polling-delay-passive = <1000>;
1788 + polling-delay = <5000>;
1789 + thermal-sensors = <&tmu 0>;
1790 +
1791 + trips {
1792 + cpu_alert: cpu-alert {
1793 + temperature = <85000>;
1794 + hysteresis = <2000>;
1795 + type = "passive";
1796 + };
1797 +
1798 + cpu_crit: cpu-crit {
1799 + temperature = <95000>;
1800 + hysteresis = <2000>;
1801 + type = "critical";
1802 + };
1803 + };
1804 +
1805 + cooling-maps {
1806 + map0 {
1807 + trip = <&cpu_alert>;
1808 + cooling-device =
1809 + <&cpu0 THERMAL_NO_LIMIT
1810 + THERMAL_NO_LIMIT>;
1811 + };
1812 + };
1813 + };
1814 + };
1815 +
1816 + esdhc0: esdhc@1560000 {
1817 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1818 + reg = <0x0 0x1560000 0x0 0x10000>;
1819 + interrupts = <0 62 0x4>;
1820 + clocks = <&clockgen 4 0>;
1821 + voltage-ranges = <1800 1800 3300 3300>;
1822 + sdhci,auto-cmd12;
1823 + big-endian;
1824 + bus-width = <4>;
1825 + status = "disabled";
1826 + };
1827 +
1828 + esdhc1: esdhc@1580000 {
1829 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1830 + reg = <0x0 0x1580000 0x0 0x10000>;
1831 + interrupts = <0 65 0x4>;
1832 + clocks = <&clockgen 4 0>;
1833 + voltage-ranges = <1800 1800 3300 3300>;
1834 + sdhci,auto-cmd12;
1835 + big-endian;
1836 + broken-cd;
1837 + bus-width = <4>;
1838 + status = "disabled";
1839 + };
1840 +
1841 + rcpm: rcpm@1ee2000 {
1842 + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
1843 + reg = <0x0 0x1ee2000 0x0 0x1000>;
1844 + fsl,#rcpm-wakeup-cells = <1>;
1845 + };
1846 +
1847 + ftm0: ftm0@29d0000 {
1848 + compatible = "fsl,ls1012a-ftm";
1849 + reg = <0x0 0x29d0000 0x0 0x10000>,
1850 + <0x0 0x1ee2140 0x0 0x4>;
1851 + reg-names = "ftm", "FlexTimer1";
1852 + interrupts = <0 86 0x4>;
1853 + big-endian;
1854 + };
1855 +
1856 + i2c0: i2c@2180000 {
1857 + compatible = "fsl,vf610-i2c";
1858 + #address-cells = <1>;
1859 + #size-cells = <0>;
1860 + reg = <0x0 0x2180000 0x0 0x10000>;
1861 + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
1862 + clocks = <&clockgen 4 3>;
1863 + status = "disabled";
1864 + };
1865 +
1866 + i2c1: i2c@2190000 {
1867 + compatible = "fsl,vf610-i2c";
1868 + #address-cells = <1>;
1869 + #size-cells = <0>;
1870 + reg = <0x0 0x2190000 0x0 0x10000>;
1871 + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
1872 + clocks = <&clockgen 4 3>;
1873 + status = "disabled";
1874 + };
1875 +
1876 + duart0: serial@21c0500 {
1877 + compatible = "fsl,ns16550", "ns16550a";
1878 + reg = <0x00 0x21c0500 0x0 0x100>;
1879 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1880 + clocks = <&clockgen 4 0>;
1881 + status = "disabled";
1882 + };
1883 +
1884 + duart1: serial@21c0600 {
1885 + compatible = "fsl,ns16550", "ns16550a";
1886 + reg = <0x00 0x21c0600 0x0 0x100>;
1887 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1888 + clocks = <&clockgen 4 0>;
1889 + status = "disabled";
1890 + };
1891 +
1892 + gpio0: gpio@2300000 {
1893 + compatible = "fsl,qoriq-gpio";
1894 + reg = <0x0 0x2300000 0x0 0x10000>;
1895 + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
1896 + gpio-controller;
1897 + #gpio-cells = <2>;
1898 + interrupt-controller;
1899 + #interrupt-cells = <2>;
1900 + };
1901 +
1902 + gpio1: gpio@2310000 {
1903 + compatible = "fsl,qoriq-gpio";
1904 + reg = <0x0 0x2310000 0x0 0x10000>;
1905 + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
1906 + gpio-controller;
1907 + #gpio-cells = <2>;
1908 + interrupt-controller;
1909 + #interrupt-cells = <2>;
1910 + };
1911 +
1912 + qspi: quadspi@1550000 {
1913 + compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
1914 + #address-cells = <1>;
1915 + #size-cells = <0>;
1916 + reg = <0x0 0x1550000 0x0 0x10000>,
1917 + <0x0 0x40000000 0x0 0x10000000>;
1918 + reg-names = "QuadSPI", "QuadSPI-memory";
1919 + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1920 + clock-names = "qspi_en", "qspi";
1921 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
1922 + big-endian;
1923 + fsl,qspi-has-second-chip;
1924 + status = "disabled";
1925 + };
1926 +
1927 + wdog0: wdog@2ad0000 {
1928 + compatible = "fsl,ls1012a-wdt",
1929 + "fsl,imx21-wdt";
1930 + reg = <0x0 0x2ad0000 0x0 0x10000>;
1931 + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
1932 + clocks = <&clockgen 4 0>;
1933 + big-endian;
1934 + };
1935 +
1936 + sai1: sai@2b50000 {
1937 + #sound-dai-cells = <0>;
1938 + compatible = "fsl,vf610-sai";
1939 + reg = <0x0 0x2b50000 0x0 0x10000>;
1940 + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
1941 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1942 + <&clockgen 4 3>, <&clockgen 4 3>;
1943 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1944 + dma-names = "tx", "rx";
1945 + dmas = <&edma0 1 47>,
1946 + <&edma0 1 46>;
1947 + status = "disabled";
1948 + };
1949 +
1950 + sai2: sai@2b60000 {
1951 + #sound-dai-cells = <0>;
1952 + compatible = "fsl,vf610-sai";
1953 + reg = <0x0 0x2b60000 0x0 0x10000>;
1954 + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
1955 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1956 + <&clockgen 4 3>, <&clockgen 4 3>;
1957 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1958 + dma-names = "tx", "rx";
1959 + dmas = <&edma0 1 45>,
1960 + <&edma0 1 44>;
1961 + status = "disabled";
1962 + };
1963 +
1964 + edma0: edma@2c00000 {
1965 + #dma-cells = <2>;
1966 + compatible = "fsl,vf610-edma";
1967 + reg = <0x0 0x2c00000 0x0 0x10000>,
1968 + <0x0 0x2c10000 0x0 0x10000>,
1969 + <0x0 0x2c20000 0x0 0x10000>;
1970 + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
1971 + <0 103 IRQ_TYPE_LEVEL_HIGH>;
1972 + interrupt-names = "edma-tx", "edma-err";
1973 + dma-channels = <32>;
1974 + big-endian;
1975 + clock-names = "dmamux0", "dmamux1";
1976 + clocks = <&clockgen 4 3>,
1977 + <&clockgen 4 3>;
1978 + };
1979 +
1980 + usb0: usb3@2f00000 {
1981 + compatible = "snps,dwc3";
1982 + reg = <0x0 0x2f00000 0x0 0x10000>;
1983 + interrupts = <0 60 0x4>;
1984 + dr_mode = "host";
1985 + snps,quirk-frame-length-adjustment = <0x20>;
1986 + snps,dis_rxdet_inp3_quirk;
1987 + };
1988 +
1989 + usb1: usb2@8600000 {
1990 + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
1991 + reg = <0x0 0x8600000 0x0 0x1000>;
1992 + interrupts = <0 139 0x4>;
1993 + dr_mode = "host";
1994 + phy_type = "ulpi";
1995 + };
1996 +
1997 + sata: sata@3200000 {
1998 + compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
1999 + reg = <0x0 0x3200000 0x0 0x10000>,
2000 + <0x0 0x20140520 0x0 0x4>;
2001 + reg-names = "ahci", "sata-ecc";
2002 + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
2003 + clocks = <&clockgen 4 0>;
2004 + dma-coherent;
2005 + status = "disabled";
2006 + };
2007 +
2008 + msi: msi-controller1@1572000 {
2009 + compatible = "fsl,ls1012a-msi";
2010 + reg = <0x0 0x1572000 0x0 0x8>;
2011 + msi-controller;
2012 + interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
2013 + };
2014 +
2015 + pcie: pcie@3400000 {
2016 + compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
2017 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
2018 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
2019 + reg-names = "regs", "config";
2020 + interrupts = <0 118 0x4>, /* AER interrupt */
2021 + <0 117 0x4>; /* PME interrupt */
2022 + interrupt-names = "aer", "pme";
2023 + #address-cells = <3>;
2024 + #size-cells = <2>;
2025 + device_type = "pci";
2026 + num-lanes = <4>;
2027 + bus-range = <0x0 0xff>;
2028 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
2029 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2030 + msi-parent = <&msi>;
2031 + #interrupt-cells = <1>;
2032 + interrupt-map-mask = <0 0 0 7>;
2033 + interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
2034 + <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
2035 + <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
2036 + <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
2037 + status = "disabled";
2038 + };
2039 + };
2040 +
2041 + reserved-memory {
2042 + #address-cells = <2>;
2043 + #size-cells = <2>;
2044 + ranges;
2045 +
2046 + pfe_reserved: packetbuffer@83400000 {
2047 + reg = <0 0x83400000 0 0xc00000>;
2048 + };
2049 + };
2050 +
2051 + pfe: pfe@04000000 {
2052 + compatible = "fsl,pfe";
2053 + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
2054 + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
2055 + reg-names = "pfe", "pfe-ddr";
2056 + fsl,pfe-num-interfaces = <0x2>;
2057 + interrupts = <0 172 0x4>, /* HIF interrupt */
2058 + <0 173 0x4>, /*HIF_NOCPY interrupt */
2059 + <0 174 0x4>; /* WoL interrupt */
2060 + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
2061 + memory-region = <&pfe_reserved>;
2062 + fsl,pfe-scfg = <&scfg 0>;
2063 + fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
2064 + clocks = <&clockgen 4 0>;
2065 + clock-names = "pfe";
2066 +
2067 + status = "okay";
2068 + pfe_mac0: ethernet@0 {
2069 + };
2070 +
2071 + pfe_mac1: ethernet@1 {
2072 + };
2073 + };
2074 +
2075 + firmware {
2076 + optee {
2077 + compatible = "linaro,optee-tz";
2078 + method = "smc";
2079 + };
2080 + };
2081 +};
2082 --- /dev/null
2083 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
2084 @@ -0,0 +1,45 @@
2085 +/*
2086 + * QorIQ FMan v3 device tree nodes for ls1043
2087 + *
2088 + * Copyright 2015-2016 Freescale Semiconductor Inc.
2089 + *
2090 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2091 + */
2092 +
2093 +&soc {
2094 +
2095 +/* include used FMan blocks */
2096 +#include "qoriq-fman3-0.dtsi"
2097 +#include "qoriq-fman3-0-1g-0.dtsi"
2098 +#include "qoriq-fman3-0-1g-1.dtsi"
2099 +#include "qoriq-fman3-0-1g-2.dtsi"
2100 +#include "qoriq-fman3-0-1g-3.dtsi"
2101 +#include "qoriq-fman3-0-1g-4.dtsi"
2102 +#include "qoriq-fman3-0-1g-5.dtsi"
2103 +#include "qoriq-fman3-0-10g-0.dtsi"
2104 +
2105 +};
2106 +
2107 +&fman0 {
2108 + /* these aliases provide the FMan ports mapping */
2109 + enet0: ethernet@e0000 {
2110 + };
2111 +
2112 + enet1: ethernet@e2000 {
2113 + };
2114 +
2115 + enet2: ethernet@e4000 {
2116 + };
2117 +
2118 + enet3: ethernet@e6000 {
2119 + };
2120 +
2121 + enet4: ethernet@e8000 {
2122 + };
2123 +
2124 + enet5: ethernet@ea000 {
2125 + };
2126 +
2127 + enet6: ethernet@f0000 {
2128 + };
2129 +};
2130 --- /dev/null
2131 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
2132 @@ -0,0 +1,69 @@
2133 +/*
2134 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2135 + *
2136 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2137 + *
2138 + * Mingkai Hu <Mingkai.hu@freescale.com>
2139 + *
2140 + * This file is dual-licensed: you can use it either under the terms
2141 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2142 + * licensing only applies to this file, and not this project as a
2143 + * whole.
2144 + *
2145 + * a) This library is free software; you can redistribute it and/or
2146 + * modify it under the terms of the GNU General Public License as
2147 + * published by the Free Software Foundation; either version 2 of the
2148 + * License, or (at your option) any later version.
2149 + *
2150 + * This library is distributed in the hope that it will be useful,
2151 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2152 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2153 + * GNU General Public License for more details.
2154 + *
2155 + * Or, alternatively,
2156 + *
2157 + * b) Permission is hereby granted, free of charge, to any person
2158 + * obtaining a copy of this software and associated documentation
2159 + * files (the "Software"), to deal in the Software without
2160 + * restriction, including without limitation the rights to use,
2161 + * copy, modify, merge, publish, distribute, sublicense, and/or
2162 + * sell copies of the Software, and to permit persons to whom the
2163 + * Software is furnished to do so, subject to the following
2164 + * conditions:
2165 + *
2166 + * The above copyright notice and this permission notice shall be
2167 + * included in all copies or substantial portions of the Software.
2168 + *
2169 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2170 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2171 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2172 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2173 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2174 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2175 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2176 + * OTHER DEALINGS IN THE SOFTWARE.
2177 + */
2178 +
2179 +#include "fsl-ls1043a-qds.dts"
2180 +
2181 +&bman_fbpr {
2182 + compatible = "fsl,bman-fbpr";
2183 + alloc-ranges = <0 0 0x10000 0>;
2184 +};
2185 +&qman_fqd {
2186 + compatible = "fsl,qman-fqd";
2187 + alloc-ranges = <0 0 0x10000 0>;
2188 +};
2189 +&qman_pfdr {
2190 + compatible = "fsl,qman-pfdr";
2191 + alloc-ranges = <0 0 0x10000 0>;
2192 +};
2193 +
2194 +&soc {
2195 +#include "qoriq-dpaa-eth.dtsi"
2196 +#include "qoriq-fman3-0-6oh.dtsi"
2197 +};
2198 +
2199 +&fman0 {
2200 + compatible = "fsl,fman", "simple-bus";
2201 +};
2202 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2203 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2204 @@ -1,7 +1,7 @@
2205 /*
2206 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2207 *
2208 - * Copyright 2014-2015, Freescale Semiconductor
2209 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2210 *
2211 * Mingkai Hu <Mingkai.hu@freescale.com>
2212 *
2213 @@ -45,7 +45,7 @@
2214 */
2215  
2216 /dts-v1/;
2217 -/include/ "fsl-ls1043a.dtsi"
2218 +#include "fsl-ls1043a.dtsi"
2219  
2220 / {
2221 model = "LS1043A QDS Board";
2222 @@ -60,6 +60,22 @@
2223 serial1 = &duart1;
2224 serial2 = &duart2;
2225 serial3 = &duart3;
2226 + sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
2227 + sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
2228 + sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
2229 + sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
2230 + qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
2231 + qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
2232 + qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
2233 + qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
2234 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
2235 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
2236 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
2237 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
2238 + emi1_slot1 = &ls1043mdio_s1;
2239 + emi1_slot2 = &ls1043mdio_s2;
2240 + emi1_slot3 = &ls1043mdio_s3;
2241 + emi1_slot4 = &ls1043mdio_s4;
2242 };
2243  
2244 chosen {
2245 @@ -97,8 +113,11 @@
2246 };
2247  
2248 fpga: board-control@2,0 {
2249 - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
2250 + #address-cells = <1>;
2251 + #size-cells = <1>;
2252 + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
2253 reg = <0x2 0x0 0x0000100>;
2254 + ranges = <0 2 0 0x100>;
2255 };
2256 };
2257  
2258 @@ -181,3 +200,149 @@
2259 reg = <0>;
2260 };
2261 };
2262 +
2263 +#include "fsl-ls1043-post.dtsi"
2264 +
2265 +&fman0 {
2266 + ethernet@e0000 {
2267 + phy-handle = <&qsgmii_phy_s2_p1>;
2268 + phy-connection-type = "sgmii";
2269 + };
2270 +
2271 + ethernet@e2000 {
2272 + phy-handle = <&qsgmii_phy_s2_p2>;
2273 + phy-connection-type = "sgmii";
2274 + };
2275 +
2276 + ethernet@e4000 {
2277 + phy-handle = <&rgmii_phy1>;
2278 + phy-connection-type = "rgmii";
2279 + };
2280 +
2281 + ethernet@e6000 {
2282 + phy-handle = <&rgmii_phy2>;
2283 + phy-connection-type = "rgmii";
2284 + };
2285 +
2286 + ethernet@e8000 {
2287 + phy-handle = <&qsgmii_phy_s2_p3>;
2288 + phy-connection-type = "sgmii";
2289 + };
2290 +
2291 + ethernet@ea000 {
2292 + phy-handle = <&qsgmii_phy_s2_p4>;
2293 + phy-connection-type = "sgmii";
2294 + };
2295 +
2296 + ethernet@f0000 { /* DTSEC9/10GEC1 */
2297 + fixed-link = <1 1 10000 0 0>;
2298 + phy-connection-type = "xgmii";
2299 + };
2300 +};
2301 +
2302 +&fpga {
2303 + mdio-mux-emi1 {
2304 + compatible = "mdio-mux-mmioreg", "mdio-mux";
2305 + mdio-parent-bus = <&mdio0>;
2306 + #address-cells = <1>;
2307 + #size-cells = <0>;
2308 + reg = <0x54 1>; /* BRDCFG4 */
2309 + mux-mask = <0xe0>; /* EMI1 */
2310 +
2311 + /* On-board RGMII1 PHY */
2312 + ls1043mdio0: mdio@0 {
2313 + reg = <0>;
2314 + #address-cells = <1>;
2315 + #size-cells = <0>;
2316 +
2317 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
2318 + reg = <0x1>;
2319 + };
2320 + };
2321 +
2322 + /* On-board RGMII2 PHY */
2323 + ls1043mdio1: mdio@1 {
2324 + reg = <0x20>;
2325 + #address-cells = <1>;
2326 + #size-cells = <0>;
2327 +
2328 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
2329 + reg = <0x2>;
2330 + };
2331 + };
2332 +
2333 + /* Slot 1 */
2334 + ls1043mdio_s1: mdio@2 {
2335 + reg = <0x40>;
2336 + #address-cells = <1>;
2337 + #size-cells = <0>;
2338 + status = "disabled";
2339 +
2340 + qsgmii_phy_s1_p1: ethernet-phy@4 {
2341 + reg = <0x4>;
2342 + };
2343 + qsgmii_phy_s1_p2: ethernet-phy@5 {
2344 + reg = <0x5>;
2345 + };
2346 + qsgmii_phy_s1_p3: ethernet-phy@6 {
2347 + reg = <0x6>;
2348 + };
2349 + qsgmii_phy_s1_p4: ethernet-phy@7 {
2350 + reg = <0x7>;
2351 + };
2352 +
2353 + sgmii_phy_s1_p1: ethernet-phy@1c {
2354 + reg = <0x1c>;
2355 + };
2356 + };
2357 +
2358 + /* Slot 2 */
2359 + ls1043mdio_s2: mdio@3 {
2360 + reg = <0x60>;
2361 + #address-cells = <1>;
2362 + #size-cells = <0>;
2363 + status = "disabled";
2364 +
2365 + qsgmii_phy_s2_p1: ethernet-phy@8 {
2366 + reg = <0x8>;
2367 + };
2368 + qsgmii_phy_s2_p2: ethernet-phy@9 {
2369 + reg = <0x9>;
2370 + };
2371 + qsgmii_phy_s2_p3: ethernet-phy@a {
2372 + reg = <0xa>;
2373 + };
2374 + qsgmii_phy_s2_p4: ethernet-phy@b {
2375 + reg = <0xb>;
2376 + };
2377 +
2378 + sgmii_phy_s2_p1: ethernet-phy@1c {
2379 + reg = <0x1c>;
2380 + };
2381 + };
2382 +
2383 + /* Slot 3 */
2384 + ls1043mdio_s3: mdio@4 {
2385 + reg = <0x80>;
2386 + #address-cells = <1>;
2387 + #size-cells = <0>;
2388 + status = "disabled";
2389 +
2390 + sgmii_phy_s3_p1: ethernet-phy@1c {
2391 + reg = <0x1c>;
2392 + };
2393 + };
2394 +
2395 + /* Slot 4 */
2396 + ls1043mdio_s4: mdio@5 {
2397 + reg = <0xa0>;
2398 + #address-cells = <1>;
2399 + #size-cells = <0>;
2400 + status = "disabled";
2401 +
2402 + sgmii_phy_s4_p1: ethernet-phy@1c {
2403 + reg = <0x1c>;
2404 + };
2405 + };
2406 + };
2407 +};
2408 --- /dev/null
2409 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2410 @@ -0,0 +1,69 @@
2411 +/*
2412 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2413 + *
2414 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2415 + *
2416 + * Mingkai Hu <Mingkai.hu@freescale.com>
2417 + *
2418 + * This file is dual-licensed: you can use it either under the terms
2419 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2420 + * licensing only applies to this file, and not this project as a
2421 + * whole.
2422 + *
2423 + * a) This library is free software; you can redistribute it and/or
2424 + * modify it under the terms of the GNU General Public License as
2425 + * published by the Free Software Foundation; either version 2 of the
2426 + * License, or (at your option) any later version.
2427 + *
2428 + * This library is distributed in the hope that it will be useful,
2429 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2430 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2431 + * GNU General Public License for more details.
2432 + *
2433 + * Or, alternatively,
2434 + *
2435 + * b) Permission is hereby granted, free of charge, to any person
2436 + * obtaining a copy of this software and associated documentation
2437 + * files (the "Software"), to deal in the Software without
2438 + * restriction, including without limitation the rights to use,
2439 + * copy, modify, merge, publish, distribute, sublicense, and/or
2440 + * sell copies of the Software, and to permit persons to whom the
2441 + * Software is furnished to do so, subject to the following
2442 + * conditions:
2443 + *
2444 + * The above copyright notice and this permission notice shall be
2445 + * included in all copies or substantial portions of the Software.
2446 + *
2447 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2448 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2449 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2450 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2451 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2452 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2453 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2454 + * OTHER DEALINGS IN THE SOFTWARE.
2455 + */
2456 +
2457 +#include "fsl-ls1043a-rdb.dts"
2458 +
2459 +&bman_fbpr {
2460 + compatible = "fsl,bman-fbpr";
2461 + alloc-ranges = <0 0 0x10000 0>;
2462 +};
2463 +&qman_fqd {
2464 + compatible = "fsl,qman-fqd";
2465 + alloc-ranges = <0 0 0x10000 0>;
2466 +};
2467 +&qman_pfdr {
2468 + compatible = "fsl,qman-pfdr";
2469 + alloc-ranges = <0 0 0x10000 0>;
2470 +};
2471 +
2472 +&soc {
2473 +#include "qoriq-dpaa-eth.dtsi"
2474 +#include "qoriq-fman3-0-6oh.dtsi"
2475 +};
2476 +
2477 +&fman0 {
2478 + compatible = "fsl,fman", "simple-bus";
2479 +};
2480 --- /dev/null
2481 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2482 @@ -0,0 +1,117 @@
2483 +/*
2484 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2485 + *
2486 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2487 + *
2488 + * This file is licensed under the terms of the GNU General Public
2489 + * License version 2. This program is licensed "as is" without any
2490 + * warranty of any kind, whether express or implied.
2491 + */
2492 +
2493 +#include "fsl-ls1043a-rdb-sdk.dts"
2494 +
2495 +&soc {
2496 + bp7: buffer-pool@7 {
2497 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2498 + fsl,bpid = <7>;
2499 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
2500 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
2501 + };
2502 +
2503 + bp8: buffer-pool@8 {
2504 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2505 + fsl,bpid = <8>;
2506 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
2507 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2508 + };
2509 +
2510 + bp9: buffer-pool@9 {
2511 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2512 + fsl,bpid = <9>;
2513 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
2514 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2515 + };
2516 +
2517 + fsl,dpaa {
2518 + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
2519 +
2520 + ethernet@0 {
2521 + compatible = "fsl,dpa-ethernet-init";
2522 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2523 + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
2524 + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
2525 + };
2526 +
2527 + ethernet@1 {
2528 + compatible = "fsl,dpa-ethernet-init";
2529 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2530 + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
2531 + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
2532 + };
2533 +
2534 + ethernet@2 {
2535 + compatible = "fsl,dpa-ethernet-init";
2536 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2537 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
2538 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
2539 + };
2540 +
2541 + ethernet@3 {
2542 + compatible = "fsl,dpa-ethernet-init";
2543 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2544 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
2545 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
2546 + };
2547 +
2548 + ethernet@4 {
2549 + compatible = "fsl,dpa-ethernet-init";
2550 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2551 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
2552 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
2553 + };
2554 +
2555 + ethernet@5 {
2556 + compatible = "fsl,dpa-ethernet-init";
2557 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2558 + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
2559 + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
2560 + };
2561 +
2562 + ethernet@8 {
2563 + compatible = "fsl,dpa-ethernet-init";
2564 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2565 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
2566 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
2567 +
2568 + };
2569 + dpa-fman0-oh@2 {
2570 + compatible = "fsl,dpa-oh";
2571 + /* Define frame queues for the OH port*/
2572 + /* <OH Rx error, OH Rx default> */
2573 + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
2574 + fsl,fman-oh-port = <&fman0_oh2>;
2575 + };
2576 + };
2577 +};
2578 +/ {
2579 + reserved-memory {
2580 + #address-cells = <2>;
2581 + #size-cells = <2>;
2582 + ranges;
2583 +
2584 + usdpaa_mem: usdpaa_mem {
2585 + compatible = "fsl,usdpaa-mem";
2586 + alloc-ranges = <0 0 0x10000 0>;
2587 + size = <0 0x10000000>;
2588 + alignment = <0 0x10000000>;
2589 + };
2590 + };
2591 +};
2592 +
2593 +&fman0 {
2594 + fman0_oh2: port@83000 {
2595 + cell-index = <1>;
2596 + compatible = "fsl,fman-port-oh";
2597 + reg = <0x83000 0x1000>;
2598 + };
2599 +};
2600 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2601 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2602 @@ -1,7 +1,7 @@
2603 /*
2604 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2605 *
2606 - * Copyright 2014-2015, Freescale Semiconductor
2607 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2608 *
2609 * Mingkai Hu <Mingkai.hu@freescale.com>
2610 *
2611 @@ -45,7 +45,7 @@
2612 */
2613  
2614 /dts-v1/;
2615 -/include/ "fsl-ls1043a.dtsi"
2616 +#include "fsl-ls1043a.dtsi"
2617  
2618 / {
2619 model = "LS1043A RDB Board";
2620 @@ -86,6 +86,10 @@
2621 compatible = "pericom,pt7c4338";
2622 reg = <0x68>;
2623 };
2624 + rtc@51 {
2625 + compatible = "nxp,pcf85263";
2626 + reg = <0x51>;
2627 + };
2628 };
2629  
2630 &ifc {
2631 @@ -130,6 +134,38 @@
2632 reg = <0>;
2633 spi-max-frequency = <1000000>; /* input clock */
2634 };
2635 +
2636 + slic@2 {
2637 + compatible = "maxim,ds26522";
2638 + reg = <2>;
2639 + spi-max-frequency = <2000000>;
2640 + fsl,spi-cs-sck-delay = <100>;
2641 + fsl,spi-sck-cs-delay = <50>;
2642 + };
2643 +
2644 + slic@3 {
2645 + compatible = "maxim,ds26522";
2646 + reg = <3>;
2647 + spi-max-frequency = <2000000>;
2648 + fsl,spi-cs-sck-delay = <100>;
2649 + fsl,spi-sck-cs-delay = <50>;
2650 + };
2651 +};
2652 +
2653 +&uqe {
2654 + ucc_hdlc: ucc@2000 {
2655 + compatible = "fsl,ucc-hdlc";
2656 + rx-clock-name = "clk8";
2657 + tx-clock-name = "clk9";
2658 + fsl,rx-sync-clock = "rsync_pin";
2659 + fsl,tx-sync-clock = "tsync_pin";
2660 + fsl,tx-timeslot-mask = <0xfffffffe>;
2661 + fsl,rx-timeslot-mask = <0xfffffffe>;
2662 + fsl,tdm-framer-type = "e1";
2663 + fsl,tdm-id = <0>;
2664 + fsl,siram-entry-id = <0>;
2665 + fsl,tdm-interface;
2666 + };
2667 };
2668  
2669 &duart0 {
2670 @@ -139,3 +175,76 @@
2671 &duart1 {
2672 status = "okay";
2673 };
2674 +
2675 +#include "fsl-ls1043-post.dtsi"
2676 +
2677 +&fman0 {
2678 + ethernet@e0000 {
2679 + phy-handle = <&qsgmii_phy1>;
2680 + phy-connection-type = "qsgmii";
2681 + };
2682 +
2683 + ethernet@e2000 {
2684 + phy-handle = <&qsgmii_phy2>;
2685 + phy-connection-type = "qsgmii";
2686 + };
2687 +
2688 + ethernet@e4000 {
2689 + phy-handle = <&rgmii_phy1>;
2690 + phy-connection-type = "rgmii-txid";
2691 + };
2692 +
2693 + ethernet@e6000 {
2694 + phy-handle = <&rgmii_phy2>;
2695 + phy-connection-type = "rgmii-txid";
2696 + };
2697 +
2698 + ethernet@e8000 {
2699 + phy-handle = <&qsgmii_phy3>;
2700 + phy-connection-type = "qsgmii";
2701 + };
2702 +
2703 + ethernet@ea000 {
2704 + phy-handle = <&qsgmii_phy4>;
2705 + phy-connection-type = "qsgmii";
2706 + };
2707 +
2708 + ethernet@f0000 { /* 10GEC1 */
2709 + phy-handle = <&aqr105_phy>;
2710 + phy-connection-type = "xgmii";
2711 + };
2712 +
2713 + mdio@fc000 {
2714 + rgmii_phy1: ethernet-phy@1 {
2715 + reg = <0x1>;
2716 + };
2717 +
2718 + rgmii_phy2: ethernet-phy@2 {
2719 + reg = <0x2>;
2720 + };
2721 +
2722 + qsgmii_phy1: ethernet-phy@4 {
2723 + reg = <0x4>;
2724 + };
2725 +
2726 + qsgmii_phy2: ethernet-phy@5 {
2727 + reg = <0x5>;
2728 + };
2729 +
2730 + qsgmii_phy3: ethernet-phy@6 {
2731 + reg = <0x6>;
2732 + };
2733 +
2734 + qsgmii_phy4: ethernet-phy@7 {
2735 + reg = <0x7>;
2736 + };
2737 + };
2738 +
2739 + mdio@fd000 {
2740 + aqr105_phy: ethernet-phy@1 {
2741 + compatible = "ethernet-phy-ieee802.3-c45";
2742 + interrupts = <0 132 4>;
2743 + reg = <0x1>;
2744 + };
2745 + };
2746 +};
2747 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2748 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2749 @@ -1,7 +1,7 @@
2750 /*
2751 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2752 *
2753 - * Copyright 2014-2015, Freescale Semiconductor
2754 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2755 *
2756 * Mingkai Hu <Mingkai.hu@freescale.com>
2757 *
2758 @@ -44,12 +44,25 @@
2759 * OTHER DEALINGS IN THE SOFTWARE.
2760 */
2761  
2762 +#include <dt-bindings/thermal/thermal.h>
2763 +
2764 / {
2765 compatible = "fsl,ls1043a";
2766 interrupt-parent = <&gic>;
2767 #address-cells = <2>;
2768 #size-cells = <2>;
2769  
2770 + aliases {
2771 + fman0 = &fman0;
2772 + ethernet0 = &enet0;
2773 + ethernet1 = &enet1;
2774 + ethernet2 = &enet2;
2775 + ethernet3 = &enet3;
2776 + ethernet4 = &enet4;
2777 + ethernet5 = &enet5;
2778 + ethernet6 = &enet6;
2779 + };
2780 +
2781 cpus {
2782 #address-cells = <1>;
2783 #size-cells = <0>;
2784 @@ -66,6 +79,8 @@
2785 reg = <0x0>;
2786 clocks = <&clockgen 1 0>;
2787 next-level-cache = <&l2>;
2788 + #cooling-cells = <2>;
2789 + cpu-idle-states = <&CPU_PH20>;
2790 };
2791  
2792 cpu1: cpu@1 {
2793 @@ -74,6 +89,7 @@
2794 reg = <0x1>;
2795 clocks = <&clockgen 1 0>;
2796 next-level-cache = <&l2>;
2797 + cpu-idle-states = <&CPU_PH20>;
2798 };
2799  
2800 cpu2: cpu@2 {
2801 @@ -82,6 +98,7 @@
2802 reg = <0x2>;
2803 clocks = <&clockgen 1 0>;
2804 next-level-cache = <&l2>;
2805 + cpu-idle-states = <&CPU_PH20>;
2806 };
2807  
2808 cpu3: cpu@3 {
2809 @@ -90,6 +107,7 @@
2810 reg = <0x3>;
2811 clocks = <&clockgen 1 0>;
2812 next-level-cache = <&l2>;
2813 + cpu-idle-states = <&CPU_PH20>;
2814 };
2815  
2816 l2: l2-cache {
2817 @@ -97,12 +115,56 @@
2818 };
2819 };
2820  
2821 + idle-states {
2822 + /*
2823 + * PSCI node is not added default, U-boot will add missing
2824 + * parts if it determines to use PSCI.
2825 + */
2826 + entry-method = "arm,psci";
2827 +
2828 + CPU_PH20: cpu-ph20 {
2829 + compatible = "arm,idle-state";
2830 + idle-state-name = "PH20";
2831 + arm,psci-suspend-param = <0x0>;
2832 + entry-latency-us = <1000>;
2833 + exit-latency-us = <1000>;
2834 + min-residency-us = <3000>;
2835 + };
2836 + };
2837 +
2838 memory@80000000 {
2839 device_type = "memory";
2840 reg = <0x0 0x80000000 0 0x80000000>;
2841 /* DRAM space 1, size: 2GiB DRAM */
2842 };
2843  
2844 + reserved-memory {
2845 + #address-cells = <2>;
2846 + #size-cells = <2>;
2847 + ranges;
2848 +
2849 + bman_fbpr: bman-fbpr {
2850 + compatible = "shared-dma-pool";
2851 + size = <0 0x1000000>;
2852 + alignment = <0 0x1000000>;
2853 + no-map;
2854 + };
2855 +
2856 + qman_fqd: qman-fqd {
2857 + compatible = "shared-dma-pool";
2858 + size = <0 0x400000>;
2859 + alignment = <0 0x400000>;
2860 + no-map;
2861 + };
2862 +
2863 + qman_pfdr: qman-pfdr {
2864 + compatible = "shared-dma-pool";
2865 + size = <0 0x2000000>;
2866 + alignment = <0 0x2000000>;
2867 + no-map;
2868 + };
2869 + };
2870 +
2871 sysclk: sysclk {
2872 compatible = "fixed-clock";
2873 #clock-cells = <0>;
2874 @@ -149,7 +211,7 @@
2875 interrupts = <1 9 0xf08>;
2876 };
2877  
2878 - soc {
2879 + soc: soc {
2880 compatible = "simple-bus";
2881 #address-cells = <2>;
2882 #size-cells = <2>;
2883 @@ -213,13 +275,14 @@
2884  
2885 dcfg: dcfg@1ee0000 {
2886 compatible = "fsl,ls1043a-dcfg", "syscon";
2887 - reg = <0x0 0x1ee0000 0x0 0x10000>;
2888 + reg = <0x0 0x1ee0000 0x0 0x1000>;
2889 big-endian;
2890 };
2891  
2892 ifc: ifc@1530000 {
2893 compatible = "fsl,ifc", "simple-bus";
2894 reg = <0x0 0x1530000 0x0 0x10000>;
2895 + big-endian;
2896 interrupts = <0 43 0x4>;
2897 };
2898  
2899 @@ -255,6 +318,103 @@
2900 big-endian;
2901 };
2902  
2903 + tmu: tmu@1f00000 {
2904 + compatible = "fsl,qoriq-tmu";
2905 + reg = <0x0 0x1f00000 0x0 0x10000>;
2906 + interrupts = <0 33 0x4>;
2907 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
2908 + fsl,tmu-calibration = <0x00000000 0x00000026
2909 + 0x00000001 0x0000002d
2910 + 0x00000002 0x00000032
2911 + 0x00000003 0x00000039
2912 + 0x00000004 0x0000003f
2913 + 0x00000005 0x00000046
2914 + 0x00000006 0x0000004d
2915 + 0x00000007 0x00000054
2916 + 0x00000008 0x0000005a
2917 + 0x00000009 0x00000061
2918 + 0x0000000a 0x0000006a
2919 + 0x0000000b 0x00000071
2920 +
2921 + 0x00010000 0x00000025
2922 + 0x00010001 0x0000002c
2923 + 0x00010002 0x00000035
2924 + 0x00010003 0x0000003d
2925 + 0x00010004 0x00000045
2926 + 0x00010005 0x0000004e
2927 + 0x00010006 0x00000057
2928 + 0x00010007 0x00000061
2929 + 0x00010008 0x0000006b
2930 + 0x00010009 0x00000076
2931 +
2932 + 0x00020000 0x00000029
2933 + 0x00020001 0x00000033
2934 + 0x00020002 0x0000003d
2935 + 0x00020003 0x00000049
2936 + 0x00020004 0x00000056
2937 + 0x00020005 0x00000061
2938 + 0x00020006 0x0000006d
2939 +
2940 + 0x00030000 0x00000021
2941 + 0x00030001 0x0000002a
2942 + 0x00030002 0x0000003c
2943 + 0x00030003 0x0000004e>;
2944 + #thermal-sensor-cells = <1>;
2945 + };
2946 +
2947 + thermal-zones {
2948 + cpu_thermal: cpu-thermal {
2949 + polling-delay-passive = <1000>;
2950 + polling-delay = <5000>;
2951 +
2952 + thermal-sensors = <&tmu 3>;
2953 +
2954 + trips {
2955 + cpu_alert: cpu-alert {
2956 + temperature = <85000>;
2957 + hysteresis = <2000>;
2958 + type = "passive";
2959 + };
2960 + cpu_crit: cpu-crit {
2961 + temperature = <95000>;
2962 + hysteresis = <2000>;
2963 + type = "critical";
2964 + };
2965 + };
2966 +
2967 + cooling-maps {
2968 + map0 {
2969 + trip = <&cpu_alert>;
2970 + cooling-device =
2971 + <&cpu0 THERMAL_NO_LIMIT
2972 + THERMAL_NO_LIMIT>;
2973 + };
2974 + };
2975 + };
2976 + };
2977 +
2978 + qman: qman@1880000 {
2979 + compatible = "fsl,qman";
2980 + reg = <0x00 0x1880000 0x0 0x10000>;
2981 + interrupts = <0 45 0x4>;
2982 + memory-region = <&qman_fqd &qman_pfdr>;
2983 + };
2984 +
2985 + bman: bman@1890000 {
2986 + compatible = "fsl,bman";
2987 + reg = <0x00 0x1890000 0x0 0x10000>;
2988 + interrupts = <0 45 0x4>;
2989 + memory-region = <&bman_fbpr>;
2990 + };
2991 +
2992 + bportals: bman-portals@508000000 {
2993 + ranges = <0x0 0x5 0x08000000 0x8000000>;
2994 + };
2995 +
2996 + qportals: qman-portals@500000000 {
2997 + ranges = <0x0 0x5 0x00000000 0x8000000>;
2998 + };
2999 +
3000 dspi0: dspi@2100000 {
3001 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
3002 #address-cells = <1>;
3003 @@ -396,6 +556,72 @@
3004 #interrupt-cells = <2>;
3005 };
3006  
3007 + uqe: uqe@2400000 {
3008 + #address-cells = <1>;
3009 + #size-cells = <1>;
3010 + device_type = "qe";
3011 + compatible = "fsl,qe", "simple-bus";
3012 + ranges = <0x0 0x0 0x2400000 0x40000>;
3013 + reg = <0x0 0x2400000 0x0 0x480>;
3014 + brg-frequency = <100000000>;
3015 + bus-frequency = <200000000>;
3016 +
3017 + fsl,qe-num-riscs = <1>;
3018 + fsl,qe-num-snums = <28>;
3019 +
3020 + qeic: qeic@80 {
3021 + compatible = "fsl,qe-ic";
3022 + reg = <0x80 0x80>;
3023 + #address-cells = <0>;
3024 + interrupt-controller;
3025 + #interrupt-cells = <1>;
3026 + interrupts = <0 77 0x04 0 77 0x04>;
3027 + };
3028 +
3029 + si1: si@700 {
3030 + #address-cells = <1>;
3031 + #size-cells = <0>;
3032 + compatible = "fsl,ls1043-qe-si",
3033 + "fsl,t1040-qe-si";
3034 + reg = <0x700 0x80>;
3035 + };
3036 +
3037 + siram1: siram@1000 {
3038 + #address-cells = <1>;
3039 + #size-cells = <1>;
3040 + compatible = "fsl,ls1043-qe-siram",
3041 + "fsl,t1040-qe-siram";
3042 + reg = <0x1000 0x800>;
3043 + };
3044 +
3045 + ucc@2000 {
3046 + cell-index = <1>;
3047 + reg = <0x2000 0x200>;
3048 + interrupts = <32>;
3049 + interrupt-parent = <&qeic>;
3050 + };
3051 +
3052 + ucc@2200 {
3053 + cell-index = <3>;
3054 + reg = <0x2200 0x200>;
3055 + interrupts = <34>;
3056 + interrupt-parent = <&qeic>;
3057 + };
3058 +
3059 + muram@10000 {
3060 + #address-cells = <1>;
3061 + #size-cells = <1>;
3062 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
3063 + ranges = <0x0 0x10000 0x6000>;
3064 +
3065 + data-only@0 {
3066 + compatible = "fsl,qe-muram-data",
3067 + "fsl,cpm-muram-data";
3068 + reg = <0x0 0x6000>;
3069 + };
3070 + };
3071 + };
3072 +
3073 lpuart0: serial@2950000 {
3074 compatible = "fsl,ls1021a-lpuart";
3075 reg = <0x0 0x2950000 0x0 0x1000>;
3076 @@ -450,6 +676,16 @@
3077 status = "disabled";
3078 };
3079  
3080 + ftm0: ftm0@29d0000 {
3081 + compatible = "fsl,ls1043a-ftm";
3082 + reg = <0x0 0x29d0000 0x0 0x10000>,
3083 + <0x0 0x1ee2140 0x0 0x4>;
3084 + reg-names = "ftm", "FlexTimer1";
3085 + interrupts = <0 86 0x4>;
3086 + big-endian;
3087 + status = "okay";
3088 + };
3089 +
3090 wdog0: wdog@2ad0000 {
3091 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
3092 reg = <0x0 0x2ad0000 0x0 0x10000>;
3093 @@ -482,6 +718,8 @@
3094 dr_mode = "host";
3095 snps,quirk-frame-length-adjustment = <0x20>;
3096 snps,dis_rxdet_inp3_quirk;
3097 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
3098 + snps,dma-snooping;
3099 };
3100  
3101 usb1: usb3@3000000 {
3102 @@ -491,6 +729,9 @@
3103 dr_mode = "host";
3104 snps,quirk-frame-length-adjustment = <0x20>;
3105 snps,dis_rxdet_inp3_quirk;
3106 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
3107 + snps,dma-snooping;
3108 + configure-gfladj;
3109 };
3110  
3111 usb2: usb3@3100000 {
3112 @@ -500,32 +741,52 @@
3113 dr_mode = "host";
3114 snps,quirk-frame-length-adjustment = <0x20>;
3115 snps,dis_rxdet_inp3_quirk;
3116 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
3117 + snps,dma-snooping;
3118 + configure-gfladj;
3119 };
3120  
3121 sata: sata@3200000 {
3122 compatible = "fsl,ls1043a-ahci";
3123 - reg = <0x0 0x3200000 0x0 0x10000>;
3124 + reg = <0x0 0x3200000 0x0 0x10000>,
3125 + <0x0 0x20140520 0x0 0x4>;
3126 + reg-names = "ahci", "sata-ecc";
3127 interrupts = <0 69 0x4>;
3128 clocks = <&clockgen 4 0>;
3129 dma-coherent;
3130 };
3131  
3132 + qdma: qdma@8380000 {
3133 + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
3134 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
3135 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
3136 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
3137 + interrupts = <0 152 0x4>,
3138 + <0 39 0x4>;
3139 + interrupt-names = "qdma-error", "qdma-queue";
3140 + channels = <8>;
3141 + queues = <2>;
3142 + status-sizes = <64>;
3143 + queue-sizes = <64 64>;
3144 + big-endian;
3145 + };
3146 +
3147 msi1: msi-controller1@1571000 {
3148 - compatible = "fsl,1s1043a-msi";
3149 + compatible = "fsl,ls1043a-msi";
3150 reg = <0x0 0x1571000 0x0 0x8>;
3151 msi-controller;
3152 interrupts = <0 116 0x4>;
3153 };
3154  
3155 msi2: msi-controller2@1572000 {
3156 - compatible = "fsl,1s1043a-msi";
3157 + compatible = "fsl,ls1043a-msi";
3158 reg = <0x0 0x1572000 0x0 0x8>;
3159 msi-controller;
3160 interrupts = <0 126 0x4>;
3161 };
3162  
3163 msi3: msi-controller3@1573000 {
3164 - compatible = "fsl,1s1043a-msi";
3165 + compatible = "fsl,ls1043a-msi";
3166 reg = <0x0 0x1573000 0x0 0x8>;
3167 msi-controller;
3168 interrupts = <0 160 0x4>;
3169 @@ -536,9 +797,9 @@
3170 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
3171 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
3172 reg-names = "regs", "config";
3173 - interrupts = <0 118 0x4>, /* controller interrupt */
3174 - <0 117 0x4>; /* PME interrupt */
3175 - interrupt-names = "intr", "pme";
3176 + interrupts = <0 117 0x4>, /* PME interrupt */
3177 + <0 118 0x4>; /* aer interrupt */
3178 + interrupt-names = "pme", "aer";
3179 #address-cells = <3>;
3180 #size-cells = <2>;
3181 device_type = "pci";
3182 @@ -547,7 +808,7 @@
3183 bus-range = <0x0 0xff>;
3184 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
3185 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3186 - msi-parent = <&msi1>;
3187 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3188 #interrupt-cells = <1>;
3189 interrupt-map-mask = <0 0 0 7>;
3190 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
3191 @@ -561,9 +822,9 @@
3192 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
3193 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
3194 reg-names = "regs", "config";
3195 - interrupts = <0 128 0x4>,
3196 - <0 127 0x4>;
3197 - interrupt-names = "intr", "pme";
3198 + interrupts = <0 127 0x4>,
3199 + <0 128 0x4>;
3200 + interrupt-names = "pme", "aer";
3201 #address-cells = <3>;
3202 #size-cells = <2>;
3203 device_type = "pci";
3204 @@ -572,7 +833,7 @@
3205 bus-range = <0x0 0xff>;
3206 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
3207 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3208 - msi-parent = <&msi2>;
3209 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3210 #interrupt-cells = <1>;
3211 interrupt-map-mask = <0 0 0 7>;
3212 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
3213 @@ -586,9 +847,9 @@
3214 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
3215 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
3216 reg-names = "regs", "config";
3217 - interrupts = <0 162 0x4>,
3218 - <0 161 0x4>;
3219 - interrupt-names = "intr", "pme";
3220 + interrupts = <0 161 0x4>,
3221 + <0 162 0x4>;
3222 + interrupt-names = "pme", "aer";
3223 #address-cells = <3>;
3224 #size-cells = <2>;
3225 device_type = "pci";
3226 @@ -597,7 +858,7 @@
3227 bus-range = <0x0 0xff>;
3228 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
3229 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3230 - msi-parent = <&msi3>;
3231 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3232 #interrupt-cells = <1>;
3233 interrupt-map-mask = <0 0 0 7>;
3234 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
3235 @@ -607,4 +868,13 @@
3236 };
3237 };
3238  
3239 + firmware {
3240 + optee {
3241 + compatible = "linaro,optee-tz";
3242 + method = "smc";
3243 + };
3244 + };
3245 };
3246 +
3247 +#include "qoriq-qman1-portals.dtsi"
3248 +#include "qoriq-bman1-portals.dtsi"
3249 --- /dev/null
3250 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
3251 @@ -0,0 +1,48 @@
3252 +/*
3253 + * QorIQ FMan v3 device tree nodes for ls1046
3254 + *
3255 + * Copyright 2015-2016 Freescale Semiconductor Inc.
3256 + *
3257 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3258 + */
3259 +
3260 +&soc {
3261 +
3262 +/* include used FMan blocks */
3263 +#include "qoriq-fman3-0.dtsi"
3264 +#include "qoriq-fman3-0-1g-0.dtsi"
3265 +#include "qoriq-fman3-0-1g-1.dtsi"
3266 +#include "qoriq-fman3-0-1g-2.dtsi"
3267 +#include "qoriq-fman3-0-1g-3.dtsi"
3268 +#include "qoriq-fman3-0-1g-4.dtsi"
3269 +#include "qoriq-fman3-0-1g-5.dtsi"
3270 +#include "qoriq-fman3-0-10g-0.dtsi"
3271 +#include "qoriq-fman3-0-10g-1.dtsi"
3272 +};
3273 +
3274 +&fman0 {
3275 + /* these aliases provide the FMan ports mapping */
3276 + enet0: ethernet@e0000 {
3277 + };
3278 +
3279 + enet1: ethernet@e2000 {
3280 + };
3281 +
3282 + enet2: ethernet@e4000 {
3283 + };
3284 +
3285 + enet3: ethernet@e6000 {
3286 + };
3287 +
3288 + enet4: ethernet@e8000 {
3289 + };
3290 +
3291 + enet5: ethernet@ea000 {
3292 + };
3293 +
3294 + enet6: ethernet@f0000 {
3295 + };
3296 +
3297 + enet7: ethernet@f2000 {
3298 + };
3299 +};
3300 --- /dev/null
3301 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
3302 @@ -0,0 +1,110 @@
3303 +/*
3304 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3305 + *
3306 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3307 + *
3308 + * Mingkai Hu <Mingkai.hu@freescale.com>
3309 + *
3310 + * This file is dual-licensed: you can use it either under the terms
3311 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3312 + * licensing only applies to this file, and not this project as a
3313 + * whole.
3314 + *
3315 + * a) This library is free software; you can redistribute it and/or
3316 + * modify it under the terms of the GNU General Public License as
3317 + * published by the Free Software Foundation; either version 2 of the
3318 + * License, or (at your option) any later version.
3319 + *
3320 + * This library is distributed in the hope that it will be useful,
3321 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3322 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3323 + * GNU General Public License for more details.
3324 + *
3325 + * Or, alternatively,
3326 + *
3327 + * b) Permission is hereby granted, free of charge, to any person
3328 + * obtaining a copy of this software and associated documentation
3329 + * files (the "Software"), to deal in the Software without
3330 + * restriction, including without limitation the rights to use,
3331 + * copy, modify, merge, publish, distribute, sublicense, and/or
3332 + * sell copies of the Software, and to permit persons to whom the
3333 + * Software is furnished to do so, subject to the following
3334 + * conditions:
3335 + *
3336 + * The above copyright notice and this permission notice shall be
3337 + * included in all copies or substantial portions of the Software.
3338 + *
3339 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3340 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3341 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3342 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3343 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3344 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3345 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3346 + * OTHER DEALINGS IN THE SOFTWARE.
3347 + */
3348 +
3349 +#include "fsl-ls1046a-qds.dts"
3350 +
3351 +&bman_fbpr {
3352 + compatible = "fsl,bman-fbpr";
3353 + alloc-ranges = <0 0 0x10000 0>;
3354 +};
3355 +&qman_fqd {
3356 + compatible = "fsl,qman-fqd";
3357 + alloc-ranges = <0 0 0x10000 0>;
3358 +};
3359 +&qman_pfdr {
3360 + compatible = "fsl,qman-pfdr";
3361 + alloc-ranges = <0 0 0x10000 0>;
3362 +};
3363 +
3364 +&soc {
3365 +#include "qoriq-dpaa-eth.dtsi"
3366 +#include "qoriq-fman3-0-6oh.dtsi"
3367 +};
3368 +
3369 +&fsldpaa {
3370 + ethernet@9 {
3371 + compatible = "fsl,dpa-ethernet";
3372 + fsl,fman-mac = <&enet7>;
3373 + dma-coherent;
3374 + };
3375 +};
3376 +
3377 +&fman0 {
3378 + compatible = "fsl,fman", "simple-bus";
3379 +};
3380 +
3381 +&dspi {
3382 + bus-num = <0>;
3383 + status = "okay";
3384 +
3385 + flash@0 {
3386 + #address-cells = <1>;
3387 + #size-cells = <1>;
3388 + compatible = "n25q128a11", "jedec,spi-nor";
3389 + reg = <0>;
3390 + spi-max-frequency = <10000000>;
3391 + };
3392 +
3393 + flash@1 {
3394 + #address-cells = <1>;
3395 + #size-cells = <1>;
3396 + compatible = "sst25wf040b", "jedec,spi-nor";
3397 + spi-cpol;
3398 + spi-cpha;
3399 + reg = <1>;
3400 + spi-max-frequency = <10000000>;
3401 + };
3402 +
3403 + flash@2 {
3404 + #address-cells = <1>;
3405 + #size-cells = <1>;
3406 + compatible = "en25s64", "jedec,spi-nor";
3407 + spi-cpol;
3408 + spi-cpha;
3409 + reg = <2>;
3410 + spi-max-frequency = <10000000>;
3411 + };
3412 +};
3413 --- /dev/null
3414 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3415 @@ -0,0 +1,363 @@
3416 +/*
3417 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3418 + *
3419 + * Copyright 2016 Freescale Semiconductor, Inc.
3420 + *
3421 + * Shaohui Xie <Shaohui.Xie@nxp.com>
3422 + *
3423 + * This file is dual-licensed: you can use it either under the terms
3424 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3425 + * licensing only applies to this file, and not this project as a
3426 + * whole.
3427 + *
3428 + * a) This library is free software; you can redistribute it and/or
3429 + * modify it under the terms of the GNU General Public License as
3430 + * published by the Free Software Foundation; either version 2 of the
3431 + * License, or (at your option) any later version.
3432 + *
3433 + * This library is distributed in the hope that it will be useful,
3434 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3435 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3436 + * GNU General Public License for more details.
3437 + *
3438 + * Or, alternatively,
3439 + *
3440 + * b) Permission is hereby granted, free of charge, to any person
3441 + * obtaining a copy of this software and associated documentation
3442 + * files (the "Software"), to deal in the Software without
3443 + * restriction, including without limitation the rights to use,
3444 + * copy, modify, merge, publish, distribute, sublicense, and/or
3445 + * sell copies of the Software, and to permit persons to whom the
3446 + * Software is furnished to do so, subject to the following
3447 + * conditions:
3448 + *
3449 + * The above copyright notice and this permission notice shall be
3450 + * included in all copies or substantial portions of the Software.
3451 + *
3452 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3453 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3454 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3455 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3456 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3457 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3458 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3459 + * OTHER DEALINGS IN THE SOFTWARE.
3460 + */
3461 +
3462 +/dts-v1/;
3463 +
3464 +#include "fsl-ls1046a.dtsi"
3465 +
3466 +/ {
3467 + model = "LS1046A QDS Board";
3468 + compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
3469 +
3470 + aliases {
3471 + gpio0 = &gpio0;
3472 + gpio1 = &gpio1;
3473 + gpio2 = &gpio2;
3474 + gpio3 = &gpio3;
3475 + serial0 = &duart0;
3476 + serial1 = &duart1;
3477 + serial2 = &duart2;
3478 + serial3 = &duart3;
3479 +
3480 + emi1_slot1 = &ls1046mdio_s1;
3481 + emi1_slot2 = &ls1046mdio_s2;
3482 + emi1_slot4 = &ls1046mdio_s4;
3483 +
3484 + sgmii_s1_p1 = &sgmii_phy_s1_p1;
3485 + sgmii_s1_p2 = &sgmii_phy_s1_p2;
3486 + sgmii_s1_p3 = &sgmii_phy_s1_p3;
3487 + sgmii_s1_p4 = &sgmii_phy_s1_p4;
3488 + sgmii_s4_p1 = &sgmii_phy_s4_p1;
3489 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
3490 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
3491 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
3492 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
3493 + };
3494 +
3495 + chosen {
3496 + stdout-path = "serial0:115200n8";
3497 + };
3498 +};
3499 +
3500 +&dspi {
3501 + bus-num = <0>;
3502 + status = "okay";
3503 +
3504 + flash@0 {
3505 + #address-cells = <1>;
3506 + #size-cells = <1>;
3507 + compatible = "n25q128a11", "jedec,spi-nor";
3508 + reg = <0>;
3509 + spi-max-frequency = <10000000>;
3510 + };
3511 +
3512 + flash@1 {
3513 + #address-cells = <1>;
3514 + #size-cells = <1>;
3515 + compatible = "sst25wf040b", "jedec,spi-nor";
3516 + spi-cpol;
3517 + spi-cpha;
3518 + reg = <1>;
3519 + spi-max-frequency = <10000000>;
3520 + };
3521 +
3522 + flash@2 {
3523 + #address-cells = <1>;
3524 + #size-cells = <1>;
3525 + compatible = "en25s64", "jedec,spi-nor";
3526 + spi-cpol;
3527 + spi-cpha;
3528 + reg = <2>;
3529 + spi-max-frequency = <10000000>;
3530 + };
3531 +};
3532 +
3533 +&duart0 {
3534 + status = "okay";
3535 +};
3536 +
3537 +&duart1 {
3538 + status = "okay";
3539 +};
3540 +
3541 +&i2c0 {
3542 + status = "okay";
3543 +
3544 + pca9547@77 {
3545 + compatible = "nxp,pca9547";
3546 + reg = <0x77>;
3547 + #address-cells = <1>;
3548 + #size-cells = <0>;
3549 +
3550 + i2c@2 {
3551 + #address-cells = <1>;
3552 + #size-cells = <0>;
3553 + reg = <0x2>;
3554 +
3555 + ina220@40 {
3556 + compatible = "ti,ina220";
3557 + reg = <0x40>;
3558 + shunt-resistor = <1000>;
3559 + };
3560 +
3561 + ina220@41 {
3562 + compatible = "ti,ina220";
3563 + reg = <0x41>;
3564 + shunt-resistor = <1000>;
3565 + };
3566 + };
3567 +
3568 + i2c@3 {
3569 + #address-cells = <1>;
3570 + #size-cells = <0>;
3571 + reg = <0x3>;
3572 +
3573 + rtc@51 {
3574 + compatible = "nxp,pcf2129";
3575 + reg = <0x51>;
3576 + /* IRQ10_B */
3577 + interrupts = <0 150 0x4>;
3578 + };
3579 +
3580 + eeprom@56 {
3581 + compatible = "atmel,24c512";
3582 + reg = <0x56>;
3583 + };
3584 +
3585 + eeprom@57 {
3586 + compatible = "atmel,24c512";
3587 + reg = <0x57>;
3588 + };
3589 +
3590 + temp-sensor@4c {
3591 + compatible = "adi,adt7461a";
3592 + reg = <0x4c>;
3593 + };
3594 + };
3595 + };
3596 +};
3597 +
3598 +&ifc {
3599 + #address-cells = <2>;
3600 + #size-cells = <1>;
3601 + /* NOR, NAND Flashes and FPGA on board */
3602 + ranges = <0x0 0x0 0x0 0x60000000 0x08000000
3603 + 0x1 0x0 0x0 0x7e800000 0x00010000
3604 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3605 + status = "okay";
3606 +
3607 + nor@0,0 {
3608 + compatible = "cfi-flash";
3609 + reg = <0x0 0x0 0x8000000>;
3610 + bank-width = <2>;
3611 + device-width = <1>;
3612 + };
3613 +
3614 + nand@1,0 {
3615 + compatible = "fsl,ifc-nand";
3616 + reg = <0x1 0x0 0x10000>;
3617 + };
3618 +
3619 + fpga: board-control@2,0 {
3620 + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
3621 + reg = <0x2 0x0 0x0000100>;
3622 + ranges = <0 2 0 0x100>;
3623 + };
3624 +};
3625 +
3626 +&lpuart0 {
3627 + status = "okay";
3628 +};
3629 +
3630 +&qspi {
3631 + num-cs = <2>;
3632 + bus-num = <0>;
3633 + status = "okay";
3634 +
3635 + qflash0: s25fl128s@0 {
3636 + compatible = "spansion,m25p80";
3637 + #address-cells = <1>;
3638 + #size-cells = <1>;
3639 + spi-max-frequency = <20000000>;
3640 + reg = <0>;
3641 + };
3642 +};
3643 +
3644 +#include "fsl-ls1046-post.dtsi"
3645 +
3646 +&fman0 {
3647 + ethernet@e0000 {
3648 + phy-handle = <&qsgmii_phy_s2_p1>;
3649 + phy-connection-type = "sgmii";
3650 + };
3651 +
3652 + ethernet@e2000 {
3653 + phy-handle = <&sgmii_phy_s4_p1>;
3654 + phy-connection-type = "sgmii";
3655 + };
3656 +
3657 + ethernet@e4000 {
3658 + phy-handle = <&rgmii_phy1>;
3659 + phy-connection-type = "rgmii";
3660 + };
3661 +
3662 + ethernet@e6000 {
3663 + phy-handle = <&rgmii_phy2>;
3664 + phy-connection-type = "rgmii";
3665 + };
3666 +
3667 + ethernet@e8000 {
3668 + phy-handle = <&sgmii_phy_s1_p3>;
3669 + phy-connection-type = "sgmii";
3670 + };
3671 +
3672 + ethernet@ea000 {
3673 + phy-handle = <&sgmii_phy_s1_p4>;
3674 + phy-connection-type = "sgmii";
3675 + };
3676 +
3677 + ethernet@f0000 { /* DTSEC9/10GEC1 */
3678 + phy-handle = <&sgmii_phy_s1_p1>;
3679 + phy-connection-type = "xgmii";
3680 + };
3681 +
3682 + ethernet@f2000 { /* DTSEC10/10GEC2 */
3683 + phy-handle = <&sgmii_phy_s1_p2>;
3684 + phy-connection-type = "xgmii";
3685 + };
3686 +};
3687 +
3688 +&fpga {
3689 + #address-cells = <1>;
3690 + #size-cells = <1>;
3691 + mdio-mux-emi1 {
3692 + compatible = "mdio-mux-mmioreg", "mdio-mux";
3693 + mdio-parent-bus = <&mdio0>;
3694 + #address-cells = <1>;
3695 + #size-cells = <0>;
3696 + reg = <0x54 1>; /* BRDCFG4 */
3697 + mux-mask = <0xe0>; /* EMI1 */
3698 +
3699 + /* On-board RGMII1 PHY */
3700 + ls1046mdio0: mdio@0 {
3701 + reg = <0>;
3702 + #address-cells = <1>;
3703 + #size-cells = <0>;
3704 +
3705 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
3706 + reg = <0x1>;
3707 + };
3708 + };
3709 +
3710 + /* On-board RGMII2 PHY */
3711 + ls1046mdio1: mdio@1 {
3712 + reg = <0x20>;
3713 + #address-cells = <1>;
3714 + #size-cells = <0>;
3715 +
3716 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
3717 + reg = <0x2>;
3718 + };
3719 + };
3720 +
3721 + /* Slot 1 */
3722 + ls1046mdio_s1: mdio@2 {
3723 + reg = <0x40>;
3724 + #address-cells = <1>;
3725 + #size-cells = <0>;
3726 + status = "disabled";
3727 +
3728 + sgmii_phy_s1_p1: ethernet-phy@1c {
3729 + reg = <0x1c>;
3730 + };
3731 +
3732 + sgmii_phy_s1_p2: ethernet-phy@1d {
3733 + reg = <0x1d>;
3734 + };
3735 +
3736 + sgmii_phy_s1_p3: ethernet-phy@1e {
3737 + reg = <0x1e>;
3738 + };
3739 +
3740 + sgmii_phy_s1_p4: ethernet-phy@1f {
3741 + reg = <0x1f>;
3742 + };
3743 + };
3744 +
3745 + /* Slot 2 */
3746 + ls1046mdio_s2: mdio@3 {
3747 + reg = <0x60>;
3748 + #address-cells = <1>;
3749 + #size-cells = <0>;
3750 + status = "disabled";
3751 +
3752 + qsgmii_phy_s2_p1: ethernet-phy@8 {
3753 + reg = <0x8>;
3754 + };
3755 + qsgmii_phy_s2_p2: ethernet-phy@9 {
3756 + reg = <0x9>;
3757 + };
3758 + qsgmii_phy_s2_p3: ethernet-phy@a {
3759 + reg = <0xa>;
3760 + };
3761 + qsgmii_phy_s2_p4: ethernet-phy@b {
3762 + reg = <0xb>;
3763 + };
3764 + };
3765 +
3766 + /* Slot 4 */
3767 + ls1046mdio_s4: mdio@5 {
3768 + reg = <0x80>;
3769 + #address-cells = <1>;
3770 + #size-cells = <0>;
3771 + status = "disabled";
3772 +
3773 + sgmii_phy_s4_p1: ethernet-phy@1c {
3774 + reg = <0x1c>;
3775 + };
3776 + };
3777 + };
3778 +};
3779 --- /dev/null
3780 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
3781 @@ -0,0 +1,83 @@
3782 +/*
3783 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3784 + *
3785 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3786 + *
3787 + * Mingkai Hu <Mingkai.hu@freescale.com>
3788 + *
3789 + * This file is dual-licensed: you can use it either under the terms
3790 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3791 + * licensing only applies to this file, and not this project as a
3792 + * whole.
3793 + *
3794 + * a) This library is free software; you can redistribute it and/or
3795 + * modify it under the terms of the GNU General Public License as
3796 + * published by the Free Software Foundation; either version 2 of the
3797 + * License, or (at your option) any later version.
3798 + *
3799 + * This library is distributed in the hope that it will be useful,
3800 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3801 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3802 + * GNU General Public License for more details.
3803 + *
3804 + * Or, alternatively,
3805 + *
3806 + * b) Permission is hereby granted, free of charge, to any person
3807 + * obtaining a copy of this software and associated documentation
3808 + * files (the "Software"), to deal in the Software without
3809 + * restriction, including without limitation the rights to use,
3810 + * copy, modify, merge, publish, distribute, sublicense, and/or
3811 + * sell copies of the Software, and to permit persons to whom the
3812 + * Software is furnished to do so, subject to the following
3813 + * conditions:
3814 + *
3815 + * The above copyright notice and this permission notice shall be
3816 + * included in all copies or substantial portions of the Software.
3817 + *
3818 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3819 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3820 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3821 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3822 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3823 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3824 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3825 + * OTHER DEALINGS IN THE SOFTWARE.
3826 + */
3827 +
3828 +#include "fsl-ls1046a-rdb.dts"
3829 +
3830 +&bman_fbpr {
3831 + compatible = "fsl,bman-fbpr";
3832 + alloc-ranges = <0 0 0x10000 0>;
3833 +};
3834 +&qman_fqd {
3835 + compatible = "fsl,qman-fqd";
3836 + alloc-ranges = <0 0 0x10000 0>;
3837 +};
3838 +&qman_pfdr {
3839 + compatible = "fsl,qman-pfdr";
3840 + alloc-ranges = <0 0 0x10000 0>;
3841 +};
3842 +
3843 +&soc {
3844 +#include "qoriq-dpaa-eth.dtsi"
3845 +#include "qoriq-fman3-0-6oh.dtsi"
3846 +};
3847 +
3848 +&fsldpaa {
3849 + ethernet@0 {
3850 + status = "disabled";
3851 + };
3852 + ethernet@1 {
3853 + status = "disabled";
3854 + };
3855 + ethernet@9 {
3856 + compatible = "fsl,dpa-ethernet";
3857 + fsl,fman-mac = <&enet7>;
3858 + dma-coherent;
3859 + };
3860 +};
3861 +
3862 +&fman0 {
3863 + compatible = "fsl,fman", "simple-bus";
3864 +};
3865 --- /dev/null
3866 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
3867 @@ -0,0 +1,110 @@
3868 +/*
3869 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3870 + *
3871 + * Copyright 2016 Freescale Semiconductor, Inc.
3872 + *
3873 + * This file is licensed under the terms of the GNU General Public
3874 + * License version 2. This program is licensed "as is" without any
3875 + * warranty of any kind, whether express or implied.
3876 + */
3877 +
3878 +#include "fsl-ls1046a-rdb-sdk.dts"
3879 +
3880 +&soc {
3881 + bp7: buffer-pool@7 {
3882 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3883 + fsl,bpid = <7>;
3884 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
3885 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
3886 + };
3887 +
3888 + bp8: buffer-pool@8 {
3889 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3890 + fsl,bpid = <8>;
3891 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
3892 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3893 + };
3894 +
3895 + bp9: buffer-pool@9 {
3896 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3897 + fsl,bpid = <9>;
3898 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
3899 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3900 + };
3901 +
3902 + fsl,dpaa {
3903 + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
3904 +
3905 + ethernet@2 {
3906 + compatible = "fsl,dpa-ethernet-init";
3907 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3908 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
3909 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
3910 + };
3911 +
3912 + ethernet@3 {
3913 + compatible = "fsl,dpa-ethernet-init";
3914 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3915 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
3916 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
3917 + };
3918 +
3919 + ethernet@4 {
3920 + compatible = "fsl,dpa-ethernet-init";
3921 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3922 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
3923 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
3924 + };
3925 +
3926 + ethernet@5 {
3927 + compatible = "fsl,dpa-ethernet-init";
3928 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3929 + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
3930 + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
3931 + };
3932 +
3933 + ethernet@8 {
3934 + compatible = "fsl,dpa-ethernet-init";
3935 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3936 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
3937 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
3938 + };
3939 +
3940 + ethernet@9 {
3941 + compatible = "fsl,dpa-ethernet-init";
3942 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3943 + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
3944 + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
3945 + };
3946 +
3947 + dpa-fman0-oh@2 {
3948 + compatible = "fsl,dpa-oh";
3949 + /* Define frame queues for the OH port*/
3950 + /* <OH Rx error, OH Rx default> */
3951 + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
3952 + fsl,fman-oh-port = <&fman0_oh2>;
3953 + };
3954 + };
3955 +};
3956 +/ {
3957 + reserved-memory {
3958 + #address-cells = <2>;
3959 + #size-cells = <2>;
3960 + ranges;
3961 +
3962 + usdpaa_mem: usdpaa_mem {
3963 + compatible = "fsl,usdpaa-mem";
3964 + alloc-ranges = <0 0 0x10000 0>;
3965 + size = <0 0x10000000>;
3966 + alignment = <0 0x10000000>;
3967 + };
3968 + };
3969 +};
3970 +
3971 +&fman0 {
3972 + fman0_oh2: port@83000 {
3973 + cell-index = <1>;
3974 + compatible = "fsl,fman-port-oh";
3975 + reg = <0x83000 0x1000>;
3976 + };
3977 +};
3978 --- /dev/null
3979 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
3980 @@ -0,0 +1,218 @@
3981 +/*
3982 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3983 + *
3984 + * Copyright 2016 Freescale Semiconductor, Inc.
3985 + *
3986 + * Mingkai Hu <mingkai.hu@nxp.com>
3987 + *
3988 + * This file is dual-licensed: you can use it either under the terms
3989 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3990 + * licensing only applies to this file, and not this project as a
3991 + * whole.
3992 + *
3993 + * a) This library is free software; you can redistribute it and/or
3994 + * modify it under the terms of the GNU General Public License as
3995 + * published by the Free Software Foundation; either version 2 of the
3996 + * License, or (at your option) any later version.
3997 + *
3998 + * This library is distributed in the hope that it will be useful,
3999 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4000 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4001 + * GNU General Public License for more details.
4002 + *
4003 + * Or, alternatively,
4004 + *
4005 + * b) Permission is hereby granted, free of charge, to any person
4006 + * obtaining a copy of this software and associated documentation
4007 + * files (the "Software"), to deal in the Software without
4008 + * restriction, including without limitation the rights to use,
4009 + * copy, modify, merge, publish, distribute, sublicense, and/or
4010 + * sell copies of the Software, and to permit persons to whom the
4011 + * Software is furnished to do so, subject to the following
4012 + * conditions:
4013 + *
4014 + * The above copyright notice and this permission notice shall be
4015 + * included in all copies or substantial portions of the Software.
4016 + *
4017 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4018 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4019 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4020 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4021 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4022 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4023 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4024 + * OTHER DEALINGS IN THE SOFTWARE.
4025 + */
4026 +
4027 +/dts-v1/;
4028 +
4029 +#include "fsl-ls1046a.dtsi"
4030 +
4031 +/ {
4032 + model = "LS1046A RDB Board";
4033 + compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
4034 +
4035 + aliases {
4036 + serial0 = &duart0;
4037 + serial1 = &duart1;
4038 + serial2 = &duart2;
4039 + serial3 = &duart3;
4040 + };
4041 +
4042 + chosen {
4043 + stdout-path = "serial0:115200n8";
4044 + };
4045 +};
4046 +
4047 +&esdhc {
4048 + mmc-hs200-1_8v;
4049 + sd-uhs-sdr104;
4050 + sd-uhs-sdr50;
4051 + sd-uhs-sdr25;
4052 + sd-uhs-sdr12;
4053 +};
4054 +
4055 +&duart0 {
4056 + status = "okay";
4057 +};
4058 +
4059 +&duart1 {
4060 + status = "okay";
4061 +};
4062 +
4063 +&i2c0 {
4064 + status = "okay";
4065 +
4066 + ina220@40 {
4067 + compatible = "ti,ina220";
4068 + reg = <0x40>;
4069 + shunt-resistor = <1000>;
4070 + };
4071 +
4072 + temp-sensor@4c {
4073 + compatible = "adi,adt7461";
4074 + reg = <0x4c>;
4075 + };
4076 +
4077 + eeprom@56 {
4078 + compatible = "atmel,24c512";
4079 + reg = <0x52>;
4080 + };
4081 +
4082 + eeprom@57 {
4083 + compatible = "atmel,24c512";
4084 + reg = <0x53>;
4085 + };
4086 +};
4087 +
4088 +&i2c3 {
4089 + status = "okay";
4090 +
4091 + rtc@51 {
4092 + compatible = "nxp,pcf2129";
4093 + reg = <0x51>;
4094 + };
4095 +};
4096 +
4097 +&ifc {
4098 + #address-cells = <2>;
4099 + #size-cells = <1>;
4100 + /* NAND Flashe and CPLD on board */
4101 + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
4102 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
4103 + status = "okay";
4104 +
4105 + nand@0,0 {
4106 + compatible = "fsl,ifc-nand";
4107 + #address-cells = <1>;
4108 + #size-cells = <1>;
4109 + reg = <0x0 0x0 0x10000>;
4110 + };
4111 +
4112 + cpld: board-control@2,0 {
4113 + compatible = "fsl,ls1046ardb-cpld";
4114 + reg = <0x2 0x0 0x0000100>;
4115 + };
4116 +};
4117 +
4118 +&qspi {
4119 + num-cs = <2>;
4120 + bus-num = <0>;
4121 + status = "okay";
4122 +
4123 + qflash0: s25fs512s@0 {
4124 + compatible = "spansion,m25p80";
4125 + #address-cells = <1>;
4126 + #size-cells = <1>;
4127 + spi-max-frequency = <20000000>;
4128 + reg = <0>;
4129 + };
4130 +
4131 + qflash1: s25fs512s@1 {
4132 + compatible = "spansion,m25p80";
4133 + #address-cells = <1>;
4134 + #size-cells = <1>;
4135 + spi-max-frequency = <20000000>;
4136 + reg = <1>;
4137 + };
4138 +};
4139 +
4140 +#include "fsl-ls1046-post.dtsi"
4141 +
4142 +&fman0 {
4143 + ethernet@e4000 {
4144 + phy-handle = <&rgmii_phy1>;
4145 + phy-connection-type = "rgmii";
4146 + };
4147 +
4148 + ethernet@e6000 {
4149 + phy-handle = <&rgmii_phy2>;
4150 + phy-connection-type = "rgmii";
4151 + };
4152 +
4153 + ethernet@e8000 {
4154 + phy-handle = <&sgmii_phy1>;
4155 + phy-connection-type = "sgmii";
4156 + };
4157 +
4158 + ethernet@ea000 {
4159 + phy-handle = <&sgmii_phy2>;
4160 + phy-connection-type = "sgmii";
4161 + };
4162 +
4163 + ethernet@f0000 { /* 10GEC1 */
4164 + phy-handle = <&aqr106_phy>;
4165 + phy-connection-type = "xgmii";
4166 + };
4167 +
4168 + ethernet@f2000 { /* 10GEC2 */
4169 + fixed-link = <0 1 1000 0 0>;
4170 + phy-connection-type = "xgmii";
4171 + };
4172 +
4173 + mdio@fc000 {
4174 + rgmii_phy1: ethernet-phy@1 {
4175 + reg = <0x1>;
4176 + };
4177 +
4178 + rgmii_phy2: ethernet-phy@2 {
4179 + reg = <0x2>;
4180 + };
4181 +
4182 + sgmii_phy1: ethernet-phy@3 {
4183 + reg = <0x3>;
4184 + };
4185 +
4186 + sgmii_phy2: ethernet-phy@4 {
4187 + reg = <0x4>;
4188 + };
4189 + };
4190 +
4191 + mdio@fd000 {
4192 + aqr106_phy: ethernet-phy@0 {
4193 + compatible = "ethernet-phy-ieee802.3-c45";
4194 + interrupts = <0 131 4>;
4195 + reg = <0x0>;
4196 + };
4197 + };
4198 +};
4199 --- /dev/null
4200 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
4201 @@ -0,0 +1,800 @@
4202 +/*
4203 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4204 + *
4205 + * Copyright 2016 Freescale Semiconductor, Inc.
4206 + *
4207 + * Mingkai Hu <mingkai.hu@nxp.com>
4208 + *
4209 + * This file is dual-licensed: you can use it either under the terms
4210 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4211 + * licensing only applies to this file, and not this project as a
4212 + * whole.
4213 + *
4214 + * a) This library is free software; you can redistribute it and/or
4215 + * modify it under the terms of the GNU General Public License as
4216 + * published by the Free Software Foundation; either version 2 of the
4217 + * License, or (at your option) any later version.
4218 + *
4219 + * This library is distributed in the hope that it will be useful,
4220 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4221 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4222 + * GNU General Public License for more details.
4223 + *
4224 + * Or, alternatively,
4225 + *
4226 + * b) Permission is hereby granted, free of charge, to any person
4227 + * obtaining a copy of this software and associated documentation
4228 + * files (the "Software"), to deal in the Software without
4229 + * restriction, including without limitation the rights to use,
4230 + * copy, modify, merge, publish, distribute, sublicense, and/or
4231 + * sell copies of the Software, and to permit persons to whom the
4232 + * Software is furnished to do so, subject to the following
4233 + * conditions:
4234 + *
4235 + * The above copyright notice and this permission notice shall be
4236 + * included in all copies or substantial portions of the Software.
4237 + *
4238 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4239 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4240 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4241 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4242 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4243 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4244 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4245 + * OTHER DEALINGS IN THE SOFTWARE.
4246 + */
4247 +
4248 +#include <dt-bindings/interrupt-controller/arm-gic.h>
4249 +#include <dt-bindings/thermal/thermal.h>
4250 +
4251 +/ {
4252 + compatible = "fsl,ls1046a";
4253 + interrupt-parent = <&gic>;
4254 + #address-cells = <2>;
4255 + #size-cells = <2>;
4256 +
4257 + aliases {
4258 + crypto = &crypto;
4259 + fman0 = &fman0;
4260 + ethernet0 = &enet0;
4261 + ethernet1 = &enet1;
4262 + ethernet2 = &enet2;
4263 + ethernet3 = &enet3;
4264 + ethernet4 = &enet4;
4265 + ethernet5 = &enet5;
4266 + ethernet6 = &enet6;
4267 + ethernet7 = &enet7;
4268 + };
4269 +
4270 + cpus {
4271 + #address-cells = <1>;
4272 + #size-cells = <0>;
4273 +
4274 + cpu0: cpu@0 {
4275 + device_type = "cpu";
4276 + compatible = "arm,cortex-a72";
4277 + reg = <0x0>;
4278 + clocks = <&clockgen 1 0>;
4279 + next-level-cache = <&l2>;
4280 + cpu-idle-states = <&CPU_PH20>;
4281 + #cooling-cells = <2>;
4282 + };
4283 +
4284 + cpu1: cpu@1 {
4285 + device_type = "cpu";
4286 + compatible = "arm,cortex-a72";
4287 + reg = <0x1>;
4288 + clocks = <&clockgen 1 0>;
4289 + next-level-cache = <&l2>;
4290 + cpu-idle-states = <&CPU_PH20>;
4291 + };
4292 +
4293 + cpu2: cpu@2 {
4294 + device_type = "cpu";
4295 + compatible = "arm,cortex-a72";
4296 + reg = <0x2>;
4297 + clocks = <&clockgen 1 0>;
4298 + next-level-cache = <&l2>;
4299 + cpu-idle-states = <&CPU_PH20>;
4300 + };
4301 +
4302 + cpu3: cpu@3 {
4303 + device_type = "cpu";
4304 + compatible = "arm,cortex-a72";
4305 + reg = <0x3>;
4306 + clocks = <&clockgen 1 0>;
4307 + next-level-cache = <&l2>;
4308 + cpu-idle-states = <&CPU_PH20>;
4309 + };
4310 +
4311 + l2: l2-cache {
4312 + compatible = "cache";
4313 + };
4314 + };
4315 +
4316 + idle-states {
4317 + /*
4318 + * PSCI node is not added default, U-boot will add missing
4319 + * parts if it determines to use PSCI.
4320 + */
4321 + entry-method = "arm,psci";
4322 +
4323 + CPU_PH20: cpu-ph20 {
4324 + compatible = "arm,idle-state";
4325 + idle-state-name = "PH20";
4326 + arm,psci-suspend-param = <0x0>;
4327 + entry-latency-us = <1000>;
4328 + exit-latency-us = <1000>;
4329 + min-residency-us = <3000>;
4330 + };
4331 + };
4332 +
4333 + memory@80000000 {
4334 + device_type = "memory";
4335 + };
4336 +
4337 + sysclk: sysclk {
4338 + compatible = "fixed-clock";
4339 + #clock-cells = <0>;
4340 + clock-frequency = <100000000>;
4341 + clock-output-names = "sysclk";
4342 + };
4343 +
4344 + reboot {
4345 + compatible ="syscon-reboot";
4346 + regmap = <&dcfg>;
4347 + offset = <0xb0>;
4348 + mask = <0x02>;
4349 + };
4350 +
4351 + timer {
4352 + compatible = "arm,armv8-timer";
4353 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
4354 + IRQ_TYPE_LEVEL_LOW)>,
4355 + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
4356 + IRQ_TYPE_LEVEL_LOW)>,
4357 + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
4358 + IRQ_TYPE_LEVEL_LOW)>,
4359 + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
4360 + IRQ_TYPE_LEVEL_LOW)>;
4361 + };
4362 +
4363 + pmu {
4364 + compatible = "arm,cortex-a72-pmu";
4365 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4366 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4367 + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
4368 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
4369 + interrupt-affinity = <&cpu0>,
4370 + <&cpu1>,
4371 + <&cpu2>,
4372 + <&cpu3>;
4373 + };
4374 +
4375 + gic: interrupt-controller@1400000 {
4376 + compatible = "arm,gic-400";
4377 + #interrupt-cells = <3>;
4378 + interrupt-controller;
4379 + reg = <0x0 0x1410000 0 0x10000>, /* GICD */
4380 + <0x0 0x1420000 0 0x20000>, /* GICC */
4381 + <0x0 0x1440000 0 0x20000>, /* GICH */
4382 + <0x0 0x1460000 0 0x20000>; /* GICV */
4383 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
4384 + IRQ_TYPE_LEVEL_LOW)>;
4385 + };
4386 +
4387 + soc: soc {
4388 + compatible = "simple-bus";
4389 + #address-cells = <2>;
4390 + #size-cells = <2>;
4391 + ranges;
4392 +
4393 + ddr: memory-controller@1080000 {
4394 + compatible = "fsl,qoriq-memory-controller";
4395 + reg = <0x0 0x1080000 0x0 0x1000>;
4396 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
4397 + big-endian;
4398 + };
4399 +
4400 + ifc: ifc@1530000 {
4401 + compatible = "fsl,ifc", "simple-bus";
4402 + reg = <0x0 0x1530000 0x0 0x10000>;
4403 + big-endian;
4404 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
4405 + };
4406 +
4407 + qspi: quadspi@1550000 {
4408 + compatible = "fsl,ls1021a-qspi";
4409 + #address-cells = <1>;
4410 + #size-cells = <0>;
4411 + reg = <0x0 0x1550000 0x0 0x10000>,
4412 + <0x0 0x40000000 0x0 0x10000000>;
4413 + reg-names = "QuadSPI", "QuadSPI-memory";
4414 + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
4415 + clock-names = "qspi_en", "qspi";
4416 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
4417 + big-endian;
4418 + fsl,qspi-has-second-chip;
4419 + status = "disabled";
4420 + };
4421 +
4422 + esdhc: esdhc@1560000 {
4423 + compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
4424 + reg = <0x0 0x1560000 0x0 0x10000>;
4425 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
4426 + clocks = <&clockgen 2 1>;
4427 + voltage-ranges = <1800 1800 3300 3300>;
4428 + sdhci,auto-cmd12;
4429 + big-endian;
4430 + bus-width = <4>;
4431 + };
4432 +
4433 + scfg: scfg@1570000 {
4434 + compatible = "fsl,ls1046a-scfg", "syscon";
4435 + reg = <0x0 0x1570000 0x0 0x10000>;
4436 + big-endian;
4437 + };
4438 +
4439 + crypto: crypto@1700000 {
4440 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
4441 + "fsl,sec-v4.0";
4442 + fsl,sec-era = <8>;
4443 + #address-cells = <1>;
4444 + #size-cells = <1>;
4445 + ranges = <0x0 0x00 0x1700000 0x100000>;
4446 + reg = <0x00 0x1700000 0x0 0x100000>;
4447 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4448 +
4449 + sec_jr0: jr@10000 {
4450 + compatible = "fsl,sec-v5.4-job-ring",
4451 + "fsl,sec-v5.0-job-ring",
4452 + "fsl,sec-v4.0-job-ring";
4453 + reg = <0x10000 0x10000>;
4454 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
4455 + };
4456 +
4457 + sec_jr1: jr@20000 {
4458 + compatible = "fsl,sec-v5.4-job-ring",
4459 + "fsl,sec-v5.0-job-ring",
4460 + "fsl,sec-v4.0-job-ring";
4461 + reg = <0x20000 0x10000>;
4462 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4463 + };
4464 +
4465 + sec_jr2: jr@30000 {
4466 + compatible = "fsl,sec-v5.4-job-ring",
4467 + "fsl,sec-v5.0-job-ring",
4468 + "fsl,sec-v4.0-job-ring";
4469 + reg = <0x30000 0x10000>;
4470 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
4471 + };
4472 +
4473 + sec_jr3: jr@40000 {
4474 + compatible = "fsl,sec-v5.4-job-ring",
4475 + "fsl,sec-v5.0-job-ring",
4476 + "fsl,sec-v4.0-job-ring";
4477 + reg = <0x40000 0x10000>;
4478 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
4479 + };
4480 + };
4481 +
4482 + qman: qman@1880000 {
4483 + compatible = "fsl,qman";
4484 + reg = <0x00 0x1880000 0x0 0x10000>;
4485 + interrupts = <0 45 0x4>;
4486 + memory-region = <&qman_fqd &qman_pfdr>;
4487 +
4488 + };
4489 +
4490 + bman: bman@1890000 {
4491 + compatible = "fsl,bman";
4492 + reg = <0x00 0x1890000 0x0 0x10000>;
4493 + interrupts = <0 45 0x4>;
4494 + memory-region = <&bman_fbpr>;
4495 +
4496 + };
4497 +
4498 + qportals: qman-portals@500000000 {
4499 + ranges = <0x0 0x5 0x00000000 0x8000000>;
4500 + };
4501 +
4502 + bportals: bman-portals@508000000 {
4503 + ranges = <0x0 0x5 0x08000000 0x8000000>;
4504 + };
4505 +
4506 + dcfg: dcfg@1ee0000 {
4507 + compatible = "fsl,ls1046a-dcfg", "syscon";
4508 + reg = <0x0 0x1ee0000 0x0 0x1000>;
4509 + big-endian;
4510 + };
4511 +
4512 + clockgen: clocking@1ee1000 {
4513 + compatible = "fsl,ls1046a-clockgen";
4514 + reg = <0x0 0x1ee1000 0x0 0x1000>;
4515 + #clock-cells = <2>;
4516 + clocks = <&sysclk>;
4517 + };
4518 +
4519 + tmu: tmu@1f00000 {
4520 + compatible = "fsl,qoriq-tmu";
4521 + reg = <0x0 0x1f00000 0x0 0x10000>;
4522 + interrupts = <0 33 0x4>;
4523 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
4524 + fsl,tmu-calibration =
4525 + /* Calibration data group 1 */
4526 + <0x00000000 0x00000026
4527 + 0x00000001 0x0000002d
4528 + 0x00000002 0x00000032
4529 + 0x00000003 0x00000039
4530 + 0x00000004 0x0000003f
4531 + 0x00000005 0x00000046
4532 + 0x00000006 0x0000004d
4533 + 0x00000007 0x00000054
4534 + 0x00000008 0x0000005a
4535 + 0x00000009 0x00000061
4536 + 0x0000000a 0x0000006a
4537 + 0x0000000b 0x00000071
4538 + /* Calibration data group 2 */
4539 + 0x00010000 0x00000025
4540 + 0x00010001 0x0000002c
4541 + 0x00010002 0x00000035
4542 + 0x00010003 0x0000003d
4543 + 0x00010004 0x00000045
4544 + 0x00010005 0x0000004e
4545 + 0x00010006 0x00000057
4546 + 0x00010007 0x00000061
4547 + 0x00010008 0x0000006b
4548 + 0x00010009 0x00000076
4549 + /* Calibration data group 3 */
4550 + 0x00020000 0x00000029
4551 + 0x00020001 0x00000033
4552 + 0x00020002 0x0000003d
4553 + 0x00020003 0x00000049
4554 + 0x00020004 0x00000056
4555 + 0x00020005 0x00000061
4556 + 0x00020006 0x0000006d
4557 + /* Calibration data group 4 */
4558 + 0x00030000 0x00000021
4559 + 0x00030001 0x0000002a
4560 + 0x00030002 0x0000003c
4561 + 0x00030003 0x0000004e>;
4562 + big-endian;
4563 + #thermal-sensor-cells = <1>;
4564 + };
4565 +
4566 + thermal-zones {
4567 + cpu_thermal: cpu-thermal {
4568 + polling-delay-passive = <1000>;
4569 + polling-delay = <5000>;
4570 + thermal-sensors = <&tmu 3>;
4571 +
4572 + trips {
4573 + cpu_alert: cpu-alert {
4574 + temperature = <85000>;
4575 + hysteresis = <2000>;
4576 + type = "passive";
4577 + };
4578 +
4579 + cpu_crit: cpu-crit {
4580 + temperature = <95000>;
4581 + hysteresis = <2000>;
4582 + type = "critical";
4583 + };
4584 + };
4585 +
4586 + cooling-maps {
4587 + map0 {
4588 + trip = <&cpu_alert>;
4589 + cooling-device =
4590 + <&cpu0 THERMAL_NO_LIMIT
4591 + THERMAL_NO_LIMIT>;
4592 + };
4593 + };
4594 + };
4595 + };
4596 +
4597 + dspi: dspi@2100000 {
4598 + compatible = "fsl,ls1021a-v1.0-dspi";
4599 + #address-cells = <1>;
4600 + #size-cells = <0>;
4601 + reg = <0x0 0x2100000 0x0 0x10000>;
4602 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
4603 + clock-names = "dspi";
4604 + clocks = <&clockgen 4 1>;
4605 + spi-num-chipselects = <5>;
4606 + big-endian;
4607 + status = "disabled";
4608 + };
4609 +
4610 + i2c0: i2c@2180000 {
4611 + compatible = "fsl,vf610-i2c";
4612 + #address-cells = <1>;
4613 + #size-cells = <0>;
4614 + reg = <0x0 0x2180000 0x0 0x10000>;
4615 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
4616 + clocks = <&clockgen 4 1>;
4617 + dmas = <&edma0 1 39>,
4618 + <&edma0 1 38>;
4619 + dma-names = "tx", "rx";
4620 + status = "disabled";
4621 + };
4622 +
4623 + i2c1: i2c@2190000 {
4624 + compatible = "fsl,vf610-i2c";
4625 + #address-cells = <1>;
4626 + #size-cells = <0>;
4627 + reg = <0x0 0x2190000 0x0 0x10000>;
4628 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
4629 + clocks = <&clockgen 4 1>;
4630 + status = "disabled";
4631 + };
4632 +
4633 + i2c2: i2c@21a0000 {
4634 + compatible = "fsl,vf610-i2c";
4635 + #address-cells = <1>;
4636 + #size-cells = <0>;
4637 + reg = <0x0 0x21a0000 0x0 0x10000>;
4638 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
4639 + clocks = <&clockgen 4 1>;
4640 + status = "disabled";
4641 + };
4642 +
4643 + i2c3: i2c@21b0000 {
4644 + compatible = "fsl,vf610-i2c";
4645 + #address-cells = <1>;
4646 + #size-cells = <0>;
4647 + reg = <0x0 0x21b0000 0x0 0x10000>;
4648 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
4649 + clocks = <&clockgen 4 1>;
4650 + status = "disabled";
4651 + };
4652 +
4653 + duart0: serial@21c0500 {
4654 + compatible = "fsl,ns16550", "ns16550a";
4655 + reg = <0x00 0x21c0500 0x0 0x100>;
4656 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4657 + clocks = <&clockgen 4 1>;
4658 + };
4659 +
4660 + duart1: serial@21c0600 {
4661 + compatible = "fsl,ns16550", "ns16550a";
4662 + reg = <0x00 0x21c0600 0x0 0x100>;
4663 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4664 + clocks = <&clockgen 4 1>;
4665 + };
4666 +
4667 + duart2: serial@21d0500 {
4668 + compatible = "fsl,ns16550", "ns16550a";
4669 + reg = <0x0 0x21d0500 0x0 0x100>;
4670 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4671 + clocks = <&clockgen 4 1>;
4672 + };
4673 +
4674 + duart3: serial@21d0600 {
4675 + compatible = "fsl,ns16550", "ns16550a";
4676 + reg = <0x0 0x21d0600 0x0 0x100>;
4677 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4678 + clocks = <&clockgen 4 1>;
4679 + };
4680 +
4681 + gpio0: gpio@2300000 {
4682 + compatible = "fsl,qoriq-gpio";
4683 + reg = <0x0 0x2300000 0x0 0x10000>;
4684 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
4685 + gpio-controller;
4686 + #gpio-cells = <2>;
4687 + interrupt-controller;
4688 + #interrupt-cells = <2>;
4689 + };
4690 +
4691 + gpio1: gpio@2310000 {
4692 + compatible = "fsl,qoriq-gpio";
4693 + reg = <0x0 0x2310000 0x0 0x10000>;
4694 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
4695 + gpio-controller;
4696 + #gpio-cells = <2>;
4697 + interrupt-controller;
4698 + #interrupt-cells = <2>;
4699 + };
4700 +
4701 + gpio2: gpio@2320000 {
4702 + compatible = "fsl,qoriq-gpio";
4703 + reg = <0x0 0x2320000 0x0 0x10000>;
4704 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
4705 + gpio-controller;
4706 + #gpio-cells = <2>;
4707 + interrupt-controller;
4708 + #interrupt-cells = <2>;
4709 + };
4710 +
4711 + gpio3: gpio@2330000 {
4712 + compatible = "fsl,qoriq-gpio";
4713 + reg = <0x0 0x2330000 0x0 0x10000>;
4714 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
4715 + gpio-controller;
4716 + #gpio-cells = <2>;
4717 + interrupt-controller;
4718 + #interrupt-cells = <2>;
4719 + };
4720 +
4721 + lpuart0: serial@2950000 {
4722 + compatible = "fsl,ls1021a-lpuart";
4723 + reg = <0x0 0x2950000 0x0 0x1000>;
4724 + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
4725 + clocks = <&clockgen 4 0>;
4726 + clock-names = "ipg";
4727 + status = "disabled";
4728 + };
4729 +
4730 + lpuart1: serial@2960000 {
4731 + compatible = "fsl,ls1021a-lpuart";
4732 + reg = <0x0 0x2960000 0x0 0x1000>;
4733 + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4734 + clocks = <&clockgen 4 1>;
4735 + clock-names = "ipg";
4736 + status = "disabled";
4737 + };
4738 +
4739 + lpuart2: serial@2970000 {
4740 + compatible = "fsl,ls1021a-lpuart";
4741 + reg = <0x0 0x2970000 0x0 0x1000>;
4742 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
4743 + clocks = <&clockgen 4 1>;
4744 + clock-names = "ipg";
4745 + status = "disabled";
4746 + };
4747 +
4748 + lpuart3: serial@2980000 {
4749 + compatible = "fsl,ls1021a-lpuart";
4750 + reg = <0x0 0x2980000 0x0 0x1000>;
4751 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4752 + clocks = <&clockgen 4 1>;
4753 + clock-names = "ipg";
4754 + status = "disabled";
4755 + };
4756 +
4757 + lpuart4: serial@2990000 {
4758 + compatible = "fsl,ls1021a-lpuart";
4759 + reg = <0x0 0x2990000 0x0 0x1000>;
4760 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
4761 + clocks = <&clockgen 4 1>;
4762 + clock-names = "ipg";
4763 + status = "disabled";
4764 + };
4765 +
4766 + lpuart5: serial@29a0000 {
4767 + compatible = "fsl,ls1021a-lpuart";
4768 + reg = <0x0 0x29a0000 0x0 0x1000>;
4769 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4770 + clocks = <&clockgen 4 1>;
4771 + clock-names = "ipg";
4772 + status = "disabled";
4773 + };
4774 +
4775 + ftm0: ftm0@29d0000 {
4776 + compatible = "fsl,ls1046a-ftm";
4777 + reg = <0x0 0x29d0000 0x0 0x10000>,
4778 + <0x0 0x1ee2140 0x0 0x4>;
4779 + reg-names = "ftm", "FlexTimer1";
4780 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
4781 + big-endian;
4782 + };
4783 +
4784 + wdog0: watchdog@2ad0000 {
4785 + compatible = "fsl,imx21-wdt";
4786 + reg = <0x0 0x2ad0000 0x0 0x10000>;
4787 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4788 + clocks = <&clockgen 4 1>;
4789 + big-endian;
4790 + };
4791 +
4792 + edma0: edma@2c00000 {
4793 + #dma-cells = <2>;
4794 + compatible = "fsl,vf610-edma";
4795 + reg = <0x0 0x2c00000 0x0 0x10000>,
4796 + <0x0 0x2c10000 0x0 0x10000>,
4797 + <0x0 0x2c20000 0x0 0x10000>;
4798 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4799 + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
4800 + interrupt-names = "edma-tx", "edma-err";
4801 + dma-channels = <32>;
4802 + big-endian;
4803 + clock-names = "dmamux0", "dmamux1";
4804 + clocks = <&clockgen 4 1>,
4805 + <&clockgen 4 1>;
4806 + };
4807 +
4808 + usb0: usb@2f00000 {
4809 + compatible = "snps,dwc3";
4810 + reg = <0x0 0x2f00000 0x0 0x10000>;
4811 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
4812 + dr_mode = "host";
4813 + snps,quirk-frame-length-adjustment = <0x20>;
4814 + snps,dis_rxdet_inp3_quirk;
4815 + };
4816 +
4817 + usb1: usb@3000000 {
4818 + compatible = "snps,dwc3";
4819 + reg = <0x0 0x3000000 0x0 0x10000>;
4820 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
4821 + dr_mode = "host";
4822 + snps,quirk-frame-length-adjustment = <0x20>;
4823 + snps,dis_rxdet_inp3_quirk;
4824 + };
4825 +
4826 + usb2: usb@3100000 {
4827 + compatible = "snps,dwc3";
4828 + reg = <0x0 0x3100000 0x0 0x10000>;
4829 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
4830 + dr_mode = "host";
4831 + snps,quirk-frame-length-adjustment = <0x20>;
4832 + snps,dis_rxdet_inp3_quirk;
4833 + };
4834 +
4835 + sata: sata@3200000 {
4836 + compatible = "fsl,ls1046a-ahci";
4837 + reg = <0x0 0x3200000 0x0 0x10000>,
4838 + <0x0 0x20140520 0x0 0x4>;
4839 + reg-names = "ahci", "sata-ecc";
4840 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
4841 + clocks = <&clockgen 4 1>;
4842 + dma-coherent;
4843 + };
4844 +
4845 + qdma: qdma@8380000 {
4846 + compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
4847 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
4848 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
4849 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
4850 + interrupts = <0 153 0x4>,
4851 + <0 39 0x4>;
4852 + interrupt-names = "qdma-error", "qdma-queue";
4853 + channels = <8>;
4854 + queues = <2>;
4855 + status-sizes = <64>;
4856 + queue-sizes = <64 64>;
4857 + big-endian;
4858 + };
4859 +
4860 + msi1: msi-controller@1580000 {
4861 + compatible = "fsl,ls1046a-msi";
4862 + msi-controller;
4863 + reg = <0x0 0x1580000 0x0 0x10000>;
4864 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4865 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4866 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4867 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
4868 + };
4869 +
4870 + msi2: msi-controller@1590000 {
4871 + compatible = "fsl,ls1046a-msi";
4872 + msi-controller;
4873 + reg = <0x0 0x1590000 0x0 0x10000>;
4874 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
4875 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
4876 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
4877 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
4878 + };
4879 +
4880 + msi3: msi-controller@15a0000 {
4881 + compatible = "fsl,ls1046a-msi";
4882 + msi-controller;
4883 + reg = <0x0 0x15a0000 0x0 0x10000>;
4884 + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4885 + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
4886 + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
4887 + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
4888 + };
4889 +
4890 + pcie@3400000 {
4891 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4892 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
4893 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
4894 + reg-names = "regs", "config";
4895 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
4896 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
4897 + interrupt-names = "pme", "aer";
4898 + #address-cells = <3>;
4899 + #size-cells = <2>;
4900 + device_type = "pci";
4901 + dma-coherent;
4902 + num-lanes = <4>;
4903 + bus-range = <0x0 0xff>;
4904 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
4905 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4906 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4907 + #interrupt-cells = <1>;
4908 + interrupt-map-mask = <0 0 0 7>;
4909 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4910 + <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4911 + <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4912 + <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
4913 + };
4914 +
4915 + pcie@3500000 {
4916 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4917 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
4918 + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
4919 + reg-names = "regs", "config";
4920 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
4921 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
4922 + interrupt-names = "pme", "aer";
4923 + #address-cells = <3>;
4924 + #size-cells = <2>;
4925 + device_type = "pci";
4926 + dma-coherent;
4927 + num-lanes = <2>;
4928 + bus-range = <0x0 0xff>;
4929 + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
4930 + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4931 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4932 + #interrupt-cells = <1>;
4933 + interrupt-map-mask = <0 0 0 7>;
4934 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4935 + <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4936 + <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4937 + <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
4938 + };
4939 +
4940 + pcie@3600000 {
4941 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4942 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
4943 + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
4944 + reg-names = "regs", "config";
4945 + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
4946 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
4947 + interrupt-names = "pme", "aer";
4948 + #address-cells = <3>;
4949 + #size-cells = <2>;
4950 + device_type = "pci";
4951 + dma-coherent;
4952 + num-lanes = <2>;
4953 + bus-range = <0x0 0xff>;
4954 + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
4955 + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4956 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4957 + #interrupt-cells = <1>;
4958 + interrupt-map-mask = <0 0 0 7>;
4959 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4960 + <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4961 + <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4962 + <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
4963 + };
4964 +
4965 + };
4966 +
4967 + reserved-memory {
4968 + #address-cells = <2>;
4969 + #size-cells = <2>;
4970 + ranges;
4971 +
4972 + bman_fbpr: bman-fbpr {
4973 + compatible = "shared-dma-pool";
4974 + size = <0 0x1000000>;
4975 + alignment = <0 0x1000000>;
4976 + no-map;
4977 + };
4978 + qman_fqd: qman-fqd {
4979 + compatible = "shared-dma-pool";
4980 + size = <0 0x800000>;
4981 + alignment = <0 0x800000>;
4982 + no-map;
4983 + };
4984 + qman_pfdr: qman-pfdr {
4985 + compatible = "shared-dma-pool";
4986 + size = <0 0x2000000>;
4987 + alignment = <0 0x2000000>;
4988 + no-map;
4989 + };
4990 + };
4991 +
4992 + firmware {
4993 + optee {
4994 + compatible = "linaro,optee-tz";
4995 + method = "smc";
4996 + };
4997 + };
4998 +};
4999 +
5000 +#include "qoriq-qman1-portals.dtsi"
5001 +#include "qoriq-bman1-portals.dtsi"
5002 --- /dev/null
5003 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
5004 @@ -0,0 +1,173 @@
5005 +/*
5006 + * Device Tree file for NXP LS1088A QDS Board.
5007 + *
5008 + * Copyright 2017 NXP
5009 + *
5010 + * Harninder Rai <harninder.rai@nxp.com>
5011 + *
5012 + * This file is dual-licensed: you can use it either under the terms
5013 + * of the GPLv2 or the X11 license, at your option. Note that this dual
5014 + * licensing only applies to this file, and not this project as a
5015 + * whole.
5016 + *
5017 + * a) This library is free software; you can redistribute it and/or
5018 + * modify it under the terms of the GNU General Public License as
5019 + * published by the Free Software Foundation; either version 2 of the
5020 + * License, or (at your option) any later version.
5021 + *
5022 + * This library is distributed in the hope that it will be useful,
5023 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5024 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5025 + * GNU General Public License for more details.
5026 + *
5027 + * Or, alternatively,
5028 + *
5029 + * b) Permission is hereby granted, free of charge, to any person
5030 + * obtaining a copy of this software and associated documentation
5031 + * files (the "Software"), to deal in the Software without
5032 + * restriction, including without limitation the rights to use,
5033 + * copy, modify, merge, publish, distribute, sublicense, and/or
5034 + * sell copies of the Software, and to permit persons to whom the
5035 + * Software is furnished to do so, subject to the following
5036 + * conditions:
5037 + *
5038 + * The above copyright notice and this permission notice shall be
5039 + * included in all copies or substantial portions of the Software.
5040 + *
5041 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5042 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5043 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5044 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5045 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5046 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5047 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5048 + * OTHER DEALINGS IN THE SOFTWARE.
5049 + */
5050 +
5051 +/dts-v1/;
5052 +
5053 +#include "fsl-ls1088a.dtsi"
5054 +
5055 +/ {
5056 + model = "LS1088A QDS Board";
5057 + compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
5058 +};
5059 +
5060 +&i2c0 {
5061 + status = "okay";
5062 +
5063 + i2c-switch@77 {
5064 + compatible = "nxp,pca9547";
5065 + reg = <0x77>;
5066 + #address-cells = <1>;
5067 + #size-cells = <0>;
5068 +
5069 + i2c@2 {
5070 + #address-cells = <1>;
5071 + #size-cells = <0>;
5072 + reg = <0x2>;
5073 +
5074 + ina220@40 {
5075 + compatible = "ti,ina220";
5076 + reg = <0x40>;
5077 + shunt-resistor = <1000>;
5078 + };
5079 +
5080 + ina220@41 {
5081 + compatible = "ti,ina220";
5082 + reg = <0x41>;
5083 + shunt-resistor = <1000>;
5084 + };
5085 + };
5086 +
5087 + i2c@3 {
5088 + #address-cells = <1>;
5089 + #size-cells = <0>;
5090 + reg = <0x3>;
5091 +
5092 + temp-sensor@4c {
5093 + compatible = "adi,adt7461a";
5094 + reg = <0x4c>;
5095 + };
5096 +
5097 + rtc@51 {
5098 + compatible = "nxp,pcf2129";
5099 + reg = <0x51>;
5100 + /* IRQ10_B */
5101 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
5102 + };
5103 +
5104 + eeprom@56 {
5105 + compatible = "atmel,24c512";
5106 + reg = <0x56>;
5107 + };
5108 +
5109 + eeprom@57 {
5110 + compatible = "atmel,24c512";
5111 + reg = <0x57>;
5112 + };
5113 + };
5114 + };
5115 +};
5116 +
5117 +&qspi {
5118 + status = "okay";
5119 + qflash0: s25fs512s@0 {
5120 + compatible = "spansion,m25p80";
5121 + #address-cells = <1>;
5122 + #size-cells = <1>;
5123 + spi-max-frequency = <20000000>;
5124 + m25p,fast-read;
5125 + reg = <0>;
5126 + };
5127 +
5128 + qflash1: s25fs512s@1 {
5129 + compatible = "spansion,m25p80";
5130 + #address-cells = <1>;
5131 + #size-cells = <1>;
5132 + spi-max-frequency = <20000000>;
5133 + m25p,fast-read;
5134 + reg = <1>;
5135 + };
5136 +};
5137 +
5138 +&ifc {
5139 + status = "okay";
5140 +
5141 + ranges = <0 0 0x5 0x80000000 0x08000000
5142 + 2 0 0x5 0x30000000 0x00010000
5143 + 3 0 0x5 0x20000000 0x00010000>;
5144 +
5145 + nor@0,0 {
5146 + compatible = "cfi-flash";
5147 + reg = <0x0 0x0 0x8000000>;
5148 + bank-width = <2>;
5149 + device-width = <1>;
5150 + };
5151 +
5152 + nand@2,0 {
5153 + compatible = "fsl,ifc-nand";
5154 + reg = <0x2 0x0 0x10000>;
5155 + };
5156 +
5157 + fpga: board-control@3,0 {
5158 + compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
5159 + reg = <0x3 0x0 0x0000100>;
5160 + };
5161 +};
5162 +
5163 +&duart0 {
5164 + status = "okay";
5165 +};
5166 +
5167 +&duart1 {
5168 + status = "okay";
5169 +};
5170 +
5171 +&esdhc {
5172 + status = "okay";
5173 +};
5174 +
5175 +&sata {
5176 + status = "okay";
5177 +};
5178 --- /dev/null
5179 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
5180 @@ -0,0 +1,236 @@
5181 +/*
5182 + * Device Tree file for NXP LS1088A RDB Board.
5183 + *
5184 + * Copyright 2017 NXP
5185 + *
5186 + * Harninder Rai <harninder.rai@nxp.com>
5187 + *
5188 + * This file is dual-licensed: you can use it either under the terms
5189 + * of the GPLv2 or the X11 license, at your option. Note that this dual
5190 + * licensing only applies to this file, and not this project as a
5191 + * whole.
5192 + *
5193 + * a) This library is free software; you can redistribute it and/or
5194 + * modify it under the terms of the GNU General Public License as
5195 + * published by the Free Software Foundation; either version 2 of the
5196 + * License, or (at your option) any later version.
5197 + *
5198 + * This library is distributed in the hope that it will be useful,
5199 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5200 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5201 + * GNU General Public License for more details.
5202 + *
5203 + * Or, alternatively,
5204 + *
5205 + * b) Permission is hereby granted, free of charge, to any person
5206 + * obtaining a copy of this software and associated documentation
5207 + * files (the "Software"), to deal in the Software without
5208 + * restriction, including without limitation the rights to use,
5209 + * copy, modify, merge, publish, distribute, sublicense, and/or
5210 + * sell copies of the Software, and to permit persons to whom the
5211 + * Software is furnished to do so, subject to the following
5212 + * conditions:
5213 + *
5214 + * The above copyright notice and this permission notice shall be
5215 + * included in all copies or substantial portions of the Software.
5216 + *
5217 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5218 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5219 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5220 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5221 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5222 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5223 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5224 + * OTHER DEALINGS IN THE SOFTWARE.
5225 + */
5226 +
5227 +/dts-v1/;
5228 +
5229 +#include "fsl-ls1088a.dtsi"
5230 +
5231 +/ {
5232 + model = "L1088A RDB Board";
5233 + compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
5234 +};
5235 +
5236 +&i2c0 {
5237 + status = "okay";
5238 +
5239 + i2c-switch@77 {
5240 + compatible = "nxp,pca9547";
5241 + reg = <0x77>;
5242 + #address-cells = <1>;
5243 + #size-cells = <0>;
5244 +
5245 + i2c@2 {
5246 + #address-cells = <1>;
5247 + #size-cells = <0>;
5248 + reg = <0x2>;
5249 +
5250 + ina220@40 {
5251 + compatible = "ti,ina220";
5252 + reg = <0x40>;
5253 + shunt-resistor = <1000>;
5254 + };
5255 + };
5256 +
5257 + i2c@3 {
5258 + #address-cells = <1>;
5259 + #size-cells = <0>;
5260 + reg = <0x3>;
5261 +
5262 + temp-sensor@4c {
5263 + compatible = "adi,adt7461a";
5264 + reg = <0x4c>;
5265 + };
5266 +
5267 + rtc@51 {
5268 + compatible = "nxp,pcf2129";
5269 + reg = <0x51>;
5270 + /* IRQ10_B */
5271 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
5272 + };
5273 + };
5274 + };
5275 +};
5276 +
5277 +&qspi {
5278 + status = "okay";
5279 + qflash0: s25fs512s@0 {
5280 + compatible = "spansion,m25p80";
5281 + #address-cells = <1>;
5282 + #size-cells = <1>;
5283 + m25p,fast-read;
5284 + spi-max-frequency = <20000000>;
5285 + reg = <0>;
5286 + };
5287 +
5288 + qflash1: s25fs512s@1 {
5289 + compatible = "spansion,m25p80";
5290 + #address-cells = <1>;
5291 + #size-cells = <1>;
5292 + m25p,fast-read;
5293 + spi-max-frequency = <20000000>;
5294 + reg = <1>;
5295 + };
5296 +};
5297 +
5298 +&ifc {
5299 + status = "okay";
5300 +
5301 + ranges = <0 0 0x5 0x30000000 0x00010000
5302 + 2 0 0x5 0x20000000 0x00010000>;
5303 +
5304 + nand@0,0 {
5305 + compatible = "fsl,ifc-nand";
5306 + reg = <0x0 0x0 0x10000>;
5307 + };
5308 +
5309 + fpga: board-control@2,0 {
5310 + compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
5311 + reg = <0x2 0x0 0x0000100>;
5312 + };
5313 +};
5314 +
5315 +&duart0 {
5316 + status = "okay";
5317 +};
5318 +
5319 +&duart1 {
5320 + status = "okay";
5321 +};
5322 +
5323 +&usb0 {
5324 + status = "okay";
5325 +};
5326 +
5327 +&usb1 {
5328 + status = "okay";
5329 +};
5330 +
5331 +&esdhc {
5332 + status = "okay";
5333 +};
5334 +
5335 +&sata {
5336 + status = "okay";
5337 +};
5338 +
5339 +&emdio1 {
5340 + /* Freescale F104 PHY1 */
5341 + mdio1_phy1: emdio1_phy@1 {
5342 + reg = <0x1c>;
5343 + phy-connection-type = "qsgmii";
5344 + };
5345 + mdio1_phy2: emdio1_phy@2 {
5346 + reg = <0x1d>;
5347 + phy-connection-type = "qsgmii";
5348 + };
5349 + mdio1_phy3: emdio1_phy@3 {
5350 + reg = <0x1e>;
5351 + phy-connection-type = "qsgmii";
5352 + };
5353 + mdio1_phy4: emdio1_phy@4 {
5354 + reg = <0x1f>;
5355 + phy-connection-type = "qsgmii";
5356 + };
5357 + /* F104 PHY2 */
5358 + mdio1_phy5: emdio1_phy@5 {
5359 + reg = <0x0c>;
5360 + phy-connection-type = "qsgmii";
5361 + };
5362 + mdio1_phy6: emdio1_phy@6 {
5363 + reg = <0x0d>;
5364 + phy-connection-type = "qsgmii";
5365 + };
5366 + mdio1_phy7: emdio1_phy@7 {
5367 + reg = <0x0e>;
5368 + phy-connection-type = "qsgmii";
5369 + };
5370 + mdio1_phy8: emdio1_phy@8 {
5371 + reg = <0x0f>;
5372 + phy-connection-type = "qsgmii";
5373 + };
5374 +};
5375 +
5376 +&emdio2 {
5377 + /* Aquantia AQR105 10G PHY */
5378 + mdio2_phy1: emdio2_phy@1 {
5379 + compatible = "ethernet-phy-ieee802.3-c45";
5380 + interrupts = <0 2 0x4>;
5381 + reg = <0x0>;
5382 + phy-connection-type = "xfi";
5383 + };
5384 +};
5385 +
5386 +/* DPMAC connections to external PHYs
5387 + * based on LS1088A RM RevC - $24.1.2 SerDes Options
5388 + */
5389 +/* DPMAC1 is 10G SFP+, fixed link */
5390 +&dpmac2 {
5391 + phy-handle = <&mdio2_phy1>;
5392 +};
5393 +&dpmac3 {
5394 + phy-handle = <&mdio1_phy5>;
5395 +};
5396 +&dpmac4 {
5397 + phy-handle = <&mdio1_phy6>;
5398 +};
5399 +&dpmac5 {
5400 + phy-handle = <&mdio1_phy7>;
5401 +};
5402 +&dpmac6 {
5403 + phy-handle = <&mdio1_phy8>;
5404 +};
5405 +&dpmac7 {
5406 + phy-handle = <&mdio1_phy1>;
5407 +};
5408 +&dpmac8 {
5409 + phy-handle = <&mdio1_phy2>;
5410 +};
5411 +&dpmac9 {
5412 + phy-handle = <&mdio1_phy3>;
5413 +};
5414 +&dpmac10 {
5415 + phy-handle = <&mdio1_phy4>;
5416 +};
5417 --- /dev/null
5418 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
5419 @@ -0,0 +1,825 @@
5420 +/*
5421 + * Device Tree Include file for NXP Layerscape-1088A family SoC.
5422 + *
5423 + * Copyright 2017 NXP
5424 + *
5425 + * Harninder Rai <harninder.rai@nxp.com>
5426 + *
5427 + * This file is dual-licensed: you can use it either under the terms
5428 + * of the GPLv2 or the X11 license, at your option. Note that this dual
5429 + * licensing only applies to this file, and not this project as a
5430 + * whole.
5431 + *
5432 + * a) This library is free software; you can redistribute it and/or
5433 + * modify it under the terms of the GNU General Public License as
5434 + * published by the Free Software Foundation; either version 2 of the
5435 + * License, or (at your option) any later version.
5436 + *
5437 + * This library is distributed in the hope that it will be useful,
5438 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5439 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5440 + * GNU General Public License for more details.
5441 + *
5442 + * Or, alternatively,
5443 + *
5444 + * b) Permission is hereby granted, free of charge, to any person
5445 + * obtaining a copy of this software and associated documentation
5446 + * files (the "Software"), to deal in the Software without
5447 + * restriction, including without limitation the rights to use,
5448 + * copy, modify, merge, publish, distribute, sublicense, and/or
5449 + * sell copies of the Software, and to permit persons to whom the
5450 + * Software is furnished to do so, subject to the following
5451 + * conditions:
5452 + *
5453 + * The above copyright notice and this permission notice shall be
5454 + * included in all copies or substantial portions of the Software.
5455 + *
5456 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5457 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5458 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5459 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5460 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5461 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5462 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5463 + * OTHER DEALINGS IN THE SOFTWARE.
5464 + */
5465 +#include <dt-bindings/interrupt-controller/arm-gic.h>
5466 +#include <dt-bindings/thermal/thermal.h>
5467 +
5468 +/ {
5469 + compatible = "fsl,ls1088a";
5470 + interrupt-parent = <&gic>;
5471 + #address-cells = <2>;
5472 + #size-cells = <2>;
5473 +
5474 + aliases {
5475 + crypto = &crypto;
5476 + };
5477 +
5478 + cpus {
5479 + #address-cells = <1>;
5480 + #size-cells = <0>;
5481 +
5482 + /* We have 2 clusters having 4 Cortex-A53 cores each */
5483 + cpu0: cpu@0 {
5484 + device_type = "cpu";
5485 + compatible = "arm,cortex-a53";
5486 + reg = <0x0>;
5487 + clocks = <&clockgen 1 0>;
5488 + #cooling-cells = <2>;
5489 + cpu-idle-states = <&CPU_PH20>;
5490 + };
5491 +
5492 + cpu1: cpu@1 {
5493 + device_type = "cpu";
5494 + compatible = "arm,cortex-a53";
5495 + reg = <0x1>;
5496 + clocks = <&clockgen 1 0>;
5497 + cpu-idle-states = <&CPU_PH20>;
5498 + };
5499 +
5500 + cpu2: cpu@2 {
5501 + device_type = "cpu";
5502 + compatible = "arm,cortex-a53";
5503 + reg = <0x2>;
5504 + clocks = <&clockgen 1 0>;
5505 + cpu-idle-states = <&CPU_PH20>;
5506 + };
5507 +
5508 + cpu3: cpu@3 {
5509 + device_type = "cpu";
5510 + compatible = "arm,cortex-a53";
5511 + reg = <0x3>;
5512 + clocks = <&clockgen 1 0>;
5513 + cpu-idle-states = <&CPU_PH20>;
5514 + };
5515 +
5516 + cpu4: cpu@100 {
5517 + device_type = "cpu";
5518 + compatible = "arm,cortex-a53";
5519 + reg = <0x100>;
5520 + clocks = <&clockgen 1 1>;
5521 + #cooling-cells = <2>;
5522 + cpu-idle-states = <&CPU_PH20>;
5523 + };
5524 +
5525 + cpu5: cpu@101 {
5526 + device_type = "cpu";
5527 + compatible = "arm,cortex-a53";
5528 + reg = <0x101>;
5529 + clocks = <&clockgen 1 1>;
5530 + cpu-idle-states = <&CPU_PH20>;
5531 + };
5532 +
5533 + cpu6: cpu@102 {
5534 + device_type = "cpu";
5535 + compatible = "arm,cortex-a53";
5536 + reg = <0x102>;
5537 + clocks = <&clockgen 1 1>;
5538 + cpu-idle-states = <&CPU_PH20>;
5539 + };
5540 +
5541 + cpu7: cpu@103 {
5542 + device_type = "cpu";
5543 + compatible = "arm,cortex-a53";
5544 + reg = <0x103>;
5545 + clocks = <&clockgen 1 1>;
5546 + cpu-idle-states = <&CPU_PH20>;
5547 + };
5548 + };
5549 +
5550 + idle-states {
5551 + /*
5552 + * PSCI node is not added default, U-boot will add missing
5553 + * parts if it determines to use PSCI.
5554 + */
5555 + entry-method = "arm,psci";
5556 +
5557 + CPU_PH20: cpu-ph20 {
5558 + compatible = "arm,idle-state";
5559 + idle-state-name = "PH20";
5560 + arm,psci-suspend-param = <0x0>;
5561 + entry-latency-us = <1000>;
5562 + exit-latency-us = <1000>;
5563 + min-residency-us = <3000>;
5564 + };
5565 + };
5566 +
5567 + gic: interrupt-controller@6000000 {
5568 + compatible = "arm,gic-v3";
5569 + #interrupt-cells = <3>;
5570 + #address-cells = <2>;
5571 + #size-cells = <2>;
5572 + ranges;
5573 + interrupt-controller;
5574 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
5575 + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
5576 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
5577 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
5578 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
5579 + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
5580 +
5581 + its: gic-its@6020000 {
5582 + compatible = "arm,gic-v3-its";
5583 + msi-controller;
5584 + reg = <0x0 0x6020000 0 0x20000>;
5585 + };
5586 + };
5587 +
5588 + timer {
5589 + compatible = "arm,armv8-timer";
5590 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
5591 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
5592 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
5593 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
5594 + };
5595 +
5596 + fsl_mc: fsl-mc@80c000000 {
5597 + compatible = "fsl,qoriq-mc";
5598 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
5599 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
5600 + msi-parent = <&its>;
5601 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
5602 + #address-cells = <3>;
5603 + #size-cells = <1>;
5604 +
5605 + /*
5606 + * Region type 0x0 - MC portals
5607 + * Region type 0x1 - QBMAN portals
5608 + */
5609 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
5610 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
5611 +
5612 + dpmacs {
5613 + #address-cells = <1>;
5614 + #size-cells = <0>;
5615 +
5616 + dpmac1: dpmac@1 {
5617 + compatible = "fsl,qoriq-mc-dpmac";
5618 + reg = <1>;
5619 + };
5620 + dpmac2: dpmac@2 {
5621 + compatible = "fsl,qoriq-mc-dpmac";
5622 + reg = <2>;
5623 + };
5624 + dpmac3: dpmac@3 {
5625 + compatible = "fsl,qoriq-mc-dpmac";
5626 + reg = <3>;
5627 + };
5628 + dpmac4: dpmac@4 {
5629 + compatible = "fsl,qoriq-mc-dpmac";
5630 + reg = <4>;
5631 + };
5632 + dpmac5: dpmac@5 {
5633 + compatible = "fsl,qoriq-mc-dpmac";
5634 + reg = <5>;
5635 + };
5636 + dpmac6: dpmac@6 {
5637 + compatible = "fsl,qoriq-mc-dpmac";
5638 + reg = <6>;
5639 + };
5640 + dpmac7: dpmac@7 {
5641 + compatible = "fsl,qoriq-mc-dpmac";
5642 + reg = <7>;
5643 + };
5644 + dpmac8: dpmac@8 {
5645 + compatible = "fsl,qoriq-mc-dpmac";
5646 + reg = <8>;
5647 + };
5648 + dpmac9: dpmac@9 {
5649 + compatible = "fsl,qoriq-mc-dpmac";
5650 + reg = <9>;
5651 + };
5652 + dpmac10: dpmac@10 {
5653 + compatible = "fsl,qoriq-mc-dpmac";
5654 + reg = <0xa>;
5655 + };
5656 + };
5657 +
5658 + };
5659 +
5660 + sysclk: sysclk {
5661 + compatible = "fixed-clock";
5662 + #clock-cells = <0>;
5663 + clock-frequency = <100000000>;
5664 + clock-output-names = "sysclk";
5665 + };
5666 +
5667 + dcfg: dcfg@1e00000 {
5668 + compatible = "fsl,ls1088a-dcfg", "syscon";
5669 + reg = <0x0 0x1e00000 0x0 0x10000>;
5670 + little-endian;
5671 + };
5672 +
5673 + rstcr: syscon@1e60000 {
5674 + compatible = "fsl,ls1088a-rstcr", "syscon";
5675 + reg = <0x0 0x1e60000 0x0 0x4>;
5676 + };
5677 +
5678 + reboot {
5679 + compatible = "syscon-reboot";
5680 + regmap = <&rstcr>;
5681 + offset = <0x0>;
5682 + mask = <0x02>;
5683 + };
5684 +
5685 +
5686 + soc {
5687 + compatible = "simple-bus";
5688 + #address-cells = <2>;
5689 + #size-cells = <2>;
5690 + ranges;
5691 +
5692 + clockgen: clocking@1300000 {
5693 + compatible = "fsl,ls1088a-clockgen";
5694 + reg = <0 0x1300000 0 0xa0000>;
5695 + #clock-cells = <2>;
5696 + clocks = <&sysclk>;
5697 + };
5698 +
5699 + tmu: tmu@1f80000 {
5700 + compatible = "fsl,qoriq-tmu";
5701 + reg = <0x0 0x1f80000 0x0 0x10000>;
5702 + interrupts = <0 23 0x4>;
5703 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
5704 + fsl,tmu-calibration =
5705 + /* Calibration data group 1 */
5706 + <0x00000000 0x00000026
5707 + 0x00000001 0x0000002d
5708 + 0x00000002 0x00000032
5709 + 0x00000003 0x00000039
5710 + 0x00000004 0x0000003f
5711 + 0x00000005 0x00000046
5712 + 0x00000006 0x0000004d
5713 + 0x00000007 0x00000054
5714 + 0x00000008 0x0000005a
5715 + 0x00000009 0x00000061
5716 + 0x0000000a 0x0000006a
5717 + 0x0000000b 0x00000071
5718 + /* Calibration data group 2 */
5719 + 0x00010000 0x00000025
5720 + 0x00010001 0x0000002c
5721 + 0x00010002 0x00000035
5722 + 0x00010003 0x0000003d
5723 + 0x00010004 0x00000045
5724 + 0x00010005 0x0000004e
5725 + 0x00010006 0x00000057
5726 + 0x00010007 0x00000061
5727 + 0x00010008 0x0000006b
5728 + 0x00010009 0x00000076
5729 + /* Calibration data group 3 */
5730 + 0x00020000 0x00000029
5731 + 0x00020001 0x00000033
5732 + 0x00020002 0x0000003d
5733 + 0x00020003 0x00000049
5734 + 0x00020004 0x00000056
5735 + 0x00020005 0x00000061
5736 + 0x00020006 0x0000006d
5737 + /* Calibration data group 4 */
5738 + 0x00030000 0x00000021
5739 + 0x00030001 0x0000002a
5740 + 0x00030002 0x0000003c
5741 + 0x00030003 0x0000004e>;
5742 + little-endian;
5743 + #thermal-sensor-cells = <1>;
5744 + };
5745 +
5746 + thermal-zones {
5747 + cpu_thermal: cpu-thermal {
5748 + polling-delay-passive = <1000>;
5749 + polling-delay = <5000>;
5750 + thermal-sensors = <&tmu 0>;
5751 +
5752 + trips {
5753 + cpu_alert: cpu-alert {
5754 + temperature = <85000>;
5755 + hysteresis = <2000>;
5756 + type = "passive";
5757 + };
5758 +
5759 + cpu_crit: cpu-crit {
5760 + temperature = <95000>;
5761 + hysteresis = <2000>;
5762 + type = "critical";
5763 + };
5764 + };
5765 +
5766 + cooling-maps {
5767 + map0 {
5768 + trip = <&cpu_alert>;
5769 + cooling-device =
5770 + <&cpu0 THERMAL_NO_LIMIT
5771 + THERMAL_NO_LIMIT>;
5772 + };
5773 + map1 {
5774 + trip = <&cpu_alert>;
5775 + cooling-device =
5776 + <&cpu4 THERMAL_NO_LIMIT
5777 + THERMAL_NO_LIMIT>;
5778 + };
5779 + };
5780 + };
5781 + };
5782 +
5783 + duart0: serial@21c0500 {
5784 + compatible = "fsl,ns16550", "ns16550a";
5785 + reg = <0x0 0x21c0500 0x0 0x100>;
5786 + clocks = <&clockgen 4 3>;
5787 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5788 + status = "disabled";
5789 + };
5790 +
5791 + duart1: serial@21c0600 {
5792 + compatible = "fsl,ns16550", "ns16550a";
5793 + reg = <0x0 0x21c0600 0x0 0x100>;
5794 + clocks = <&clockgen 4 3>;
5795 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5796 + status = "disabled";
5797 + };
5798 +
5799 + cluster1_core0_watchdog: wdt@c000000 {
5800 + compatible = "arm,sp805-wdt", "arm,primecell";
5801 + reg = <0x0 0xc000000 0x0 0x1000>;
5802 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5803 + clock-names = "apb_pclk", "wdog_clk";
5804 + };
5805 +
5806 + cluster1_core1_watchdog: wdt@c010000 {
5807 + compatible = "arm,sp805-wdt", "arm,primecell";
5808 + reg = <0x0 0xc010000 0x0 0x1000>;
5809 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5810 + clock-names = "apb_pclk", "wdog_clk";
5811 + };
5812 +
5813 + cluster1_core2_watchdog: wdt@c020000 {
5814 + compatible = "arm,sp805-wdt", "arm,primecell";
5815 + reg = <0x0 0xc020000 0x0 0x1000>;
5816 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5817 + clock-names = "apb_pclk", "wdog_clk";
5818 + };
5819 +
5820 + cluster1_core3_watchdog: wdt@c030000 {
5821 + compatible = "arm,sp805-wdt", "arm,primecell";
5822 + reg = <0x0 0xc030000 0x0 0x1000>;
5823 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5824 + clock-names = "apb_pclk", "wdog_clk";
5825 + };
5826 +
5827 + cluster2_core0_watchdog: wdt@c100000 {
5828 + compatible = "arm,sp805-wdt", "arm,primecell";
5829 + reg = <0x0 0xc100000 0x0 0x1000>;
5830 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5831 + clock-names = "apb_pclk", "wdog_clk";
5832 + };
5833 +
5834 + cluster2_core1_watchdog: wdt@c110000 {
5835 + compatible = "arm,sp805-wdt", "arm,primecell";
5836 + reg = <0x0 0xc110000 0x0 0x1000>;
5837 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5838 + clock-names = "apb_pclk", "wdog_clk";
5839 + };
5840 +
5841 + cluster2_core2_watchdog: wdt@c120000 {
5842 + compatible = "arm,sp805-wdt", "arm,primecell";
5843 + reg = <0x0 0xc120000 0x0 0x1000>;
5844 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5845 + clock-names = "apb_pclk", "wdog_clk";
5846 + };
5847 +
5848 + cluster2_core3_watchdog: wdt@c130000 {
5849 + compatible = "arm,sp805-wdt", "arm,primecell";
5850 + reg = <0x0 0xc130000 0x0 0x1000>;
5851 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5852 + clock-names = "apb_pclk", "wdog_clk";
5853 + };
5854 +
5855 + gpio0: gpio@2300000 {
5856 + compatible = "fsl,qoriq-gpio";
5857 + reg = <0x0 0x2300000 0x0 0x10000>;
5858 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5859 + gpio-controller;
5860 + #gpio-cells = <2>;
5861 + interrupt-controller;
5862 + #interrupt-cells = <2>;
5863 + };
5864 +
5865 + gpio1: gpio@2310000 {
5866 + compatible = "fsl,qoriq-gpio";
5867 + reg = <0x0 0x2310000 0x0 0x10000>;
5868 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5869 + gpio-controller;
5870 + #gpio-cells = <2>;
5871 + interrupt-controller;
5872 + #interrupt-cells = <2>;
5873 + };
5874 +
5875 + gpio2: gpio@2320000 {
5876 + compatible = "fsl,qoriq-gpio";
5877 + reg = <0x0 0x2320000 0x0 0x10000>;
5878 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5879 + gpio-controller;
5880 + #gpio-cells = <2>;
5881 + interrupt-controller;
5882 + #interrupt-cells = <2>;
5883 + };
5884 +
5885 + gpio3: gpio@2330000 {
5886 + compatible = "fsl,qoriq-gpio";
5887 + reg = <0x0 0x2330000 0x0 0x10000>;
5888 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5889 + gpio-controller;
5890 + #gpio-cells = <2>;
5891 + interrupt-controller;
5892 + #interrupt-cells = <2>;
5893 + };
5894 +
5895 + /* TODO: WRIOP (CCSR?) */
5896 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
5897 + * E-MDIO1: 0x1_6000
5898 + */
5899 + compatible = "fsl,fman-memac-mdio";
5900 + reg = <0x0 0x8B96000 0x0 0x1000>;
5901 + device_type = "mdio";
5902 + little-endian; /* force the driver in LE mode */
5903 +
5904 + /* Not necessary on the QDS, but needed on the RDB */
5905 + #address-cells = <1>;
5906 + #size-cells = <0>;
5907 + };
5908 +
5909 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
5910 + * E-MDIO2: 0x1_7000
5911 + */
5912 + compatible = "fsl,fman-memac-mdio";
5913 + reg = <0x0 0x8B97000 0x0 0x1000>;
5914 + device_type = "mdio";
5915 + little-endian; /* force the driver in LE mode */
5916 +
5917 + #address-cells = <1>;
5918 + #size-cells = <0>;
5919 + };
5920 +
5921 + ifc: ifc@2240000 {
5922 + compatible = "fsl,ifc", "simple-bus";
5923 + reg = <0x0 0x2240000 0x0 0x20000>;
5924 + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
5925 + little-endian;
5926 + #address-cells = <2>;
5927 + #size-cells = <1>;
5928 +
5929 + };
5930 +
5931 + ftm0: ftm0@2800000 {
5932 + compatible = "fsl,ls1088a-ftm";
5933 + reg = <0x0 0x2800000 0x0 0x10000>,
5934 + <0x0 0x1e34050 0x0 0x4>;
5935 + interrupts = <0 44 4>;
5936 + reg-names = "ftm", "FlexTimer1";
5937 + };
5938 +
5939 + i2c0: i2c@2000000 {
5940 + compatible = "fsl,vf610-i2c";
5941 + #address-cells = <1>;
5942 + #size-cells = <0>;
5943 + reg = <0x0 0x2000000 0x0 0x10000>;
5944 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5945 + clocks = <&clockgen 4 7>;
5946 + status = "disabled";
5947 + };
5948 +
5949 + i2c1: i2c@2010000 {
5950 + compatible = "fsl,vf610-i2c";
5951 + #address-cells = <1>;
5952 + #size-cells = <0>;
5953 + reg = <0x0 0x2010000 0x0 0x10000>;
5954 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5955 + clocks = <&clockgen 4 7>;
5956 + status = "disabled";
5957 + };
5958 +
5959 + i2c2: i2c@2020000 {
5960 + compatible = "fsl,vf610-i2c";
5961 + #address-cells = <1>;
5962 + #size-cells = <0>;
5963 + reg = <0x0 0x2020000 0x0 0x10000>;
5964 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5965 + clocks = <&clockgen 4 7>;
5966 + status = "disabled";
5967 + };
5968 +
5969 + i2c3: i2c@2030000 {
5970 + compatible = "fsl,vf610-i2c";
5971 + #address-cells = <1>;
5972 + #size-cells = <0>;
5973 + reg = <0x0 0x2030000 0x0 0x10000>;
5974 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5975 + clocks = <&clockgen 4 7>;
5976 + status = "disabled";
5977 + };
5978 +
5979 + qspi: quadspi@20c0000 {
5980 + compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
5981 + #address-cells = <1>;
5982 + #size-cells = <0>;
5983 + reg = <0x0 0x20c0000 0x0 0x10000>,
5984 + <0x0 0x20000000 0x0 0x10000000>;
5985 + reg-names = "QuadSPI", "QuadSPI-memory";
5986 + interrupts = <0 25 0x4>; /* Level high type */
5987 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5988 + clock-names = "qspi_en", "qspi";
5989 + fsl,qspi-has-second-chip;
5990 + };
5991 +
5992 + esdhc: esdhc@2140000 {
5993 + compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
5994 + reg = <0x0 0x2140000 0x0 0x10000>;
5995 + interrupts = <0 28 0x4>; /* Level high type */
5996 + clock-frequency = <0>;
5997 + voltage-ranges = <1800 1800 3300 3300>;
5998 + sdhci,auto-cmd12;
5999 + little-endian;
6000 + bus-width = <4>;
6001 + status = "disabled";
6002 + };
6003 +
6004 + usb0: usb3@3100000 {
6005 + compatible = "snps,dwc3";
6006 + reg = <0x0 0x3100000 0x0 0x10000>;
6007 + interrupts = <0 80 0x4>; /* Level high type */
6008 + dr_mode = "host";
6009 + configure-gfladj;
6010 + snps,dis_rxdet_inp3_quirk;
6011 + };
6012 +
6013 + usb1: usb3@3110000 {
6014 + compatible = "snps,dwc3";
6015 + reg = <0x0 0x3110000 0x0 0x10000>;
6016 + interrupts = <0 81 0x4>; /* Level high type */
6017 + dr_mode = "host";
6018 + configure-gfladj;
6019 + snps,dis_rxdet_inp3_quirk;
6020 + };
6021 +
6022 + sata: sata@3200000 {
6023 + compatible = "fsl,ls1088a-ahci";
6024 + reg = <0x0 0x3200000 0x0 0x10000>,
6025 + <0x7 0x100520 0x0 0x4>;
6026 + reg-names = "ahci", "sata-ecc";
6027 + interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
6028 + clocks = <&clockgen 4 3>;
6029 + dma-coherent;
6030 + status = "disabled";
6031 + };
6032 +
6033 + pcie@3400000 {
6034 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
6035 + "snps,dw-pcie";
6036 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
6037 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
6038 + reg-names = "regs", "config";
6039 + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
6040 + interrupt-names = "aer";
6041 + #address-cells = <3>;
6042 + #size-cells = <2>;
6043 + device_type = "pci";
6044 + dma-coherent;
6045 + num-lanes = <4>;
6046 + bus-range = <0x0 0xff>;
6047 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
6048 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6049 + msi-parent = <&its>;
6050 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
6051 + #interrupt-cells = <1>;
6052 + interrupt-map-mask = <0 0 0 7>;
6053 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
6054 + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
6055 + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
6056 + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
6057 + };
6058 +
6059 + pcie@3500000 {
6060 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
6061 + "snps,dw-pcie";
6062 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
6063 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
6064 + reg-names = "regs", "config";
6065 + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
6066 + interrupt-names = "aer";
6067 + #address-cells = <3>;
6068 + #size-cells = <2>;
6069 + device_type = "pci";
6070 + dma-coherent;
6071 + num-lanes = <4>;
6072 + bus-range = <0x0 0xff>;
6073 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
6074 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6075 + msi-parent = <&its>;
6076 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
6077 + #interrupt-cells = <1>;
6078 + interrupt-map-mask = <0 0 0 7>;
6079 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
6080 + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
6081 + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
6082 + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
6083 + };
6084 +
6085 + pcie@3600000 {
6086 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
6087 + "snps,dw-pcie";
6088 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
6089 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
6090 + reg-names = "regs", "config";
6091 + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
6092 + interrupt-names = "aer";
6093 + #address-cells = <3>;
6094 + #size-cells = <2>;
6095 + device_type = "pci";
6096 + dma-coherent;
6097 + num-lanes = <8>;
6098 + bus-range = <0x0 0xff>;
6099 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
6100 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6101 + msi-parent = <&its>;
6102 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
6103 + #interrupt-cells = <1>;
6104 + interrupt-map-mask = <0 0 0 7>;
6105 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
6106 + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
6107 + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
6108 + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
6109 + };
6110 +
6111 + smmu: iommu@5000000 {
6112 + compatible = "arm,mmu-500";
6113 + reg = <0 0x5000000 0 0x800000>;
6114 + #global-interrupts = <12>;
6115 + #iommu-cells = <1>;
6116 + stream-match-mask = <0x7C00>;
6117 + interrupts = <0 13 4>, /* global secure fault */
6118 + <0 14 4>, /* combined secure interrupt */
6119 + <0 15 4>, /* global non-secure fault */
6120 + <0 16 4>, /* combined non-secure interrupt */
6121 + /* performance counter interrupts 0-7 */
6122 + <0 211 4>,
6123 + <0 212 4>,
6124 + <0 213 4>,
6125 + <0 214 4>,
6126 + <0 215 4>,
6127 + <0 216 4>,
6128 + <0 217 4>,
6129 + <0 218 4>,
6130 + /* per context interrupt, 64 interrupts */
6131 + <0 146 4>,
6132 + <0 147 4>,
6133 + <0 148 4>,
6134 + <0 149 4>,
6135 + <0 150 4>,
6136 + <0 151 4>,
6137 + <0 152 4>,
6138 + <0 153 4>,
6139 + <0 154 4>,
6140 + <0 155 4>,
6141 + <0 156 4>,
6142 + <0 157 4>,
6143 + <0 158 4>,
6144 + <0 159 4>,
6145 + <0 160 4>,
6146 + <0 161 4>,
6147 + <0 162 4>,
6148 + <0 163 4>,
6149 + <0 164 4>,
6150 + <0 165 4>,
6151 + <0 166 4>,
6152 + <0 167 4>,
6153 + <0 168 4>,
6154 + <0 169 4>,
6155 + <0 170 4>,
6156 + <0 171 4>,
6157 + <0 172 4>,
6158 + <0 173 4>,
6159 + <0 174 4>,
6160 + <0 175 4>,
6161 + <0 176 4>,
6162 + <0 177 4>,
6163 + <0 178 4>,
6164 + <0 179 4>,
6165 + <0 180 4>,
6166 + <0 181 4>,
6167 + <0 182 4>,
6168 + <0 183 4>,
6169 + <0 184 4>,
6170 + <0 185 4>,
6171 + <0 186 4>,
6172 + <0 187 4>,
6173 + <0 188 4>,
6174 + <0 189 4>,
6175 + <0 190 4>,
6176 + <0 191 4>,
6177 + <0 192 4>,
6178 + <0 193 4>,
6179 + <0 194 4>,
6180 + <0 195 4>,
6181 + <0 196 4>,
6182 + <0 197 4>,
6183 + <0 198 4>,
6184 + <0 199 4>,
6185 + <0 200 4>,
6186 + <0 201 4>,
6187 + <0 202 4>,
6188 + <0 203 4>,
6189 + <0 204 4>,
6190 + <0 205 4>,
6191 + <0 206 4>,
6192 + <0 207 4>,
6193 + <0 208 4>,
6194 + <0 209 4>;
6195 + };
6196 +
6197 + crypto: crypto@8000000 {
6198 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
6199 + fsl,sec-era = <8>;
6200 + #address-cells = <1>;
6201 + #size-cells = <1>;
6202 + ranges = <0x0 0x00 0x8000000 0x100000>;
6203 + reg = <0x00 0x8000000 0x0 0x100000>;
6204 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
6205 + dma-coherent;
6206 +
6207 + sec_jr0: jr@10000 {
6208 + compatible = "fsl,sec-v5.0-job-ring",
6209 + "fsl,sec-v4.0-job-ring";
6210 + reg = <0x10000 0x10000>;
6211 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
6212 + };
6213 +
6214 + sec_jr1: jr@20000 {
6215 + compatible = "fsl,sec-v5.0-job-ring",
6216 + "fsl,sec-v4.0-job-ring";
6217 + reg = <0x20000 0x10000>;
6218 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
6219 + };
6220 +
6221 + sec_jr2: jr@30000 {
6222 + compatible = "fsl,sec-v5.0-job-ring",
6223 + "fsl,sec-v4.0-job-ring";
6224 + reg = <0x30000 0x10000>;
6225 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
6226 + };
6227 +
6228 + sec_jr3: jr@40000 {
6229 + compatible = "fsl,sec-v5.0-job-ring",
6230 + "fsl,sec-v4.0-job-ring";
6231 + reg = <0x40000 0x10000>;
6232 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
6233 + };
6234 + };
6235 + };
6236 +
6237 + firmware {
6238 + optee {
6239 + compatible = "linaro,optee-tz";
6240 + method = "smc";
6241 + };
6242 + };
6243 +
6244 +};
6245 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
6246 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
6247 @@ -1,8 +1,10 @@
6248 /*
6249 * Device Tree file for Freescale LS2080a QDS Board.
6250 *
6251 - * Copyright (C) 2015, Freescale Semiconductor
6252 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
6253 + * Copyright 2017 NXP
6254 *
6255 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6256 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6257 *
6258 * This file is dual-licensed: you can use it either under the terms
6259 @@ -46,169 +48,76 @@
6260  
6261 /dts-v1/;
6262  
6263 -/include/ "fsl-ls2080a.dtsi"
6264 +#include "fsl-ls2080a.dtsi"
6265 +#include "fsl-ls208xa-qds.dtsi"
6266  
6267 / {
6268 model = "Freescale Layerscape 2080a QDS Board";
6269 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
6270  
6271 - aliases {
6272 - serial0 = &serial0;
6273 - serial1 = &serial1;
6274 - };
6275 -
6276 chosen {
6277 stdout-path = "serial0:115200n8";
6278 };
6279 };
6280  
6281 -&esdhc {
6282 - status = "okay";
6283 -};
6284 -
6285 &ifc {
6286 - status = "okay";
6287 - #address-cells = <2>;
6288 - #size-cells = <1>;
6289 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6290 - 0x2 0x0 0x5 0x30000000 0x00010000
6291 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6292 -
6293 - nor@0,0 {
6294 + boardctrl: board-control@3,0 {
6295 #address-cells = <1>;
6296 #size-cells = <1>;
6297 - compatible = "cfi-flash";
6298 - reg = <0x0 0x0 0x8000000>;
6299 - bank-width = <2>;
6300 - device-width = <1>;
6301 - };
6302 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
6303 + reg = <3 0 0x300>; /* TODO check address */
6304 + ranges = <0 3 0 0x300>;
6305  
6306 - nand@2,0 {
6307 - compatible = "fsl,ifc-nand";
6308 - reg = <0x2 0x0 0x10000>;
6309 - };
6310 + mdio_mux_emi1 {
6311 + compatible = "mdio-mux-mmioreg", "mdio-mux";
6312 + mdio-parent-bus = <&emdio1>;
6313 + reg = <0x54 1>; /* BRDCFG4 */
6314 + mux-mask = <0xe0>; /* EMI1_MDIO */
6315  
6316 - cpld@3,0 {
6317 - reg = <0x3 0x0 0x10000>;
6318 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6319 - };
6320 -};
6321 -
6322 -&i2c0 {
6323 - status = "okay";
6324 - pca9547@77 {
6325 - compatible = "nxp,pca9547";
6326 - reg = <0x77>;
6327 - #address-cells = <1>;
6328 - #size-cells = <0>;
6329 - i2c@0 {
6330 - #address-cells = <1>;
6331 + #address-cells=<1>;
6332 #size-cells = <0>;
6333 - reg = <0x00>;
6334 - rtc@68 {
6335 - compatible = "dallas,ds3232";
6336 - reg = <0x68>;
6337 - };
6338 - };
6339  
6340 - i2c@2 {
6341 - #address-cells = <1>;
6342 - #size-cells = <0>;
6343 - reg = <0x02>;
6344 -
6345 - ina220@40 {
6346 - compatible = "ti,ina220";
6347 - reg = <0x40>;
6348 - shunt-resistor = <500>;
6349 - };
6350 -
6351 - ina220@41 {
6352 - compatible = "ti,ina220";
6353 - reg = <0x41>;
6354 - shunt-resistor = <1000>;
6355 - };
6356 - };
6357 -
6358 - i2c@3 {
6359 - #address-cells = <1>;
6360 - #size-cells = <0>;
6361 - reg = <0x3>;
6362 -
6363 - adt7481@4c {
6364 - compatible = "adi,adt7461";
6365 - reg = <0x4c>;
6366 + /* Child MDIO buses, one for each riser card:
6367 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
6368 + * VSC8234 PHYs on the riser cards.
6369 + */
6370 +
6371 + mdio_mux3: mdio@60 {
6372 + reg = <0x60>;
6373 + #address-cells = <1>;
6374 + #size-cells = <0>;
6375 +
6376 + mdio0_phy12: mdio_phy0@1c {
6377 + reg = <0x1c>;
6378 + phy-connection-type = "sgmii";
6379 + };
6380 + mdio0_phy13: mdio_phy1@1d {
6381 + reg = <0x1d>;
6382 + phy-connection-type = "sgmii";
6383 + };
6384 + mdio0_phy14: mdio_phy2@1e {
6385 + reg = <0x1e>;
6386 + phy-connection-type = "sgmii";
6387 + };
6388 + mdio0_phy15: mdio_phy3@1f {
6389 + reg = <0x1f>;
6390 + phy-connection-type = "sgmii";
6391 + };
6392 };
6393 };
6394 };
6395 };
6396  
6397 -&i2c1 {
6398 - status = "disabled";
6399 -};
6400 -
6401 -&i2c2 {
6402 - status = "disabled";
6403 -};
6404 -
6405 -&i2c3 {
6406 - status = "disabled";
6407 -};
6408 -
6409 -&dspi {
6410 - status = "okay";
6411 - dflash0: n25q128a {
6412 - #address-cells = <1>;
6413 - #size-cells = <1>;
6414 - compatible = "st,m25p80";
6415 - spi-max-frequency = <3000000>;
6416 - reg = <0>;
6417 - };
6418 - dflash1: sst25wf040b {
6419 - #address-cells = <1>;
6420 - #size-cells = <1>;
6421 - compatible = "st,m25p80";
6422 - spi-max-frequency = <3000000>;
6423 - reg = <1>;
6424 - };
6425 - dflash2: en25s64 {
6426 - #address-cells = <1>;
6427 - #size-cells = <1>;
6428 - compatible = "st,m25p80";
6429 - spi-max-frequency = <3000000>;
6430 - reg = <2>;
6431 - };
6432 -};
6433 -
6434 -&qspi {
6435 - status = "okay";
6436 - flash0: s25fl256s1@0 {
6437 - #address-cells = <1>;
6438 - #size-cells = <1>;
6439 - compatible = "st,m25p80";
6440 - spi-max-frequency = <20000000>;
6441 - reg = <0>;
6442 - };
6443 - flash2: s25fl256s1@2 {
6444 - #address-cells = <1>;
6445 - #size-cells = <1>;
6446 - compatible = "st,m25p80";
6447 - spi-max-frequency = <20000000>;
6448 - reg = <0>;
6449 - };
6450 -};
6451 -
6452 -&sata0 {
6453 - status = "okay";
6454 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
6455 +&dpmac9 {
6456 + phy-handle = <&mdio0_phy12>;
6457 };
6458 -
6459 -&sata1 {
6460 - status = "okay";
6461 +&dpmac10 {
6462 + phy-handle = <&mdio0_phy13>;
6463 };
6464 -
6465 -&usb0 {
6466 - status = "okay";
6467 +&dpmac11 {
6468 + phy-handle = <&mdio0_phy14>;
6469 };
6470 -
6471 -&usb1 {
6472 - status = "okay";
6473 +&dpmac12 {
6474 + phy-handle = <&mdio0_phy15>;
6475 };
6476 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6477 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6478 @@ -1,8 +1,10 @@
6479 /*
6480 * Device Tree file for Freescale LS2080a RDB Board.
6481 *
6482 - * Copyright (C) 2015, Freescale Semiconductor
6483 + * Copyright 2016 Freescale Semiconductor, Inc.
6484 + * Copyright 2017 NXP
6485 *
6486 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6487 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6488 *
6489 * This file is dual-licensed: you can use it either under the terms
6490 @@ -46,125 +48,94 @@
6491  
6492 /dts-v1/;
6493  
6494 -/include/ "fsl-ls2080a.dtsi"
6495 +#include "fsl-ls2080a.dtsi"
6496 +#include "fsl-ls208xa-rdb.dtsi"
6497  
6498 / {
6499 model = "Freescale Layerscape 2080a RDB Board";
6500 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
6501  
6502 - aliases {
6503 - serial0 = &serial0;
6504 - serial1 = &serial1;
6505 - };
6506 -
6507 chosen {
6508 stdout-path = "serial1:115200n8";
6509 };
6510 };
6511  
6512 -&esdhc {
6513 - status = "okay";
6514 -};
6515 -
6516 -&ifc {
6517 - status = "okay";
6518 - #address-cells = <2>;
6519 - #size-cells = <1>;
6520 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6521 - 0x2 0x0 0x5 0x30000000 0x00010000
6522 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6523 -
6524 - nor@0,0 {
6525 - #address-cells = <1>;
6526 - #size-cells = <1>;
6527 - compatible = "cfi-flash";
6528 - reg = <0x0 0x0 0x8000000>;
6529 - bank-width = <2>;
6530 - device-width = <1>;
6531 - };
6532 -
6533 - nand@2,0 {
6534 - compatible = "fsl,ifc-nand";
6535 - reg = <0x2 0x0 0x10000>;
6536 - };
6537 -
6538 - cpld@3,0 {
6539 - reg = <0x3 0x0 0x10000>;
6540 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6541 - };
6542 -
6543 -};
6544 -
6545 -&i2c0 {
6546 - status = "okay";
6547 - pca9547@75 {
6548 - compatible = "nxp,pca9547";
6549 - reg = <0x75>;
6550 - #address-cells = <1>;
6551 - #size-cells = <0>;
6552 - status = "disabled";
6553 - i2c@1 {
6554 - #address-cells = <1>;
6555 - #size-cells = <0>;
6556 - reg = <0x01>;
6557 - rtc@68 {
6558 - compatible = "dallas,ds3232";
6559 - reg = <0x68>;
6560 - };
6561 - };
6562 -
6563 - i2c@3 {
6564 - #address-cells = <1>;
6565 - #size-cells = <0>;
6566 - reg = <0x3>;
6567 -
6568 - adt7481@4c {
6569 - compatible = "adi,adt7461";
6570 - reg = <0x4c>;
6571 - };
6572 - };
6573 - };
6574 -};
6575 -
6576 -&i2c1 {
6577 - status = "disabled";
6578 -};
6579 -
6580 -&i2c2 {
6581 - status = "disabled";
6582 -};
6583 -
6584 -&i2c3 {
6585 +&emdio1 {
6586 status = "disabled";
6587 + /* CS4340 PHYs */
6588 + mdio1_phy1: emdio1_phy@1 {
6589 + reg = <0x10>;
6590 + phy-connection-type = "xfi";
6591 + };
6592 + mdio1_phy2: emdio1_phy@2 {
6593 + reg = <0x11>;
6594 + phy-connection-type = "xfi";
6595 + };
6596 + mdio1_phy3: emdio1_phy@3 {
6597 + reg = <0x12>;
6598 + phy-connection-type = "xfi";
6599 + };
6600 + mdio1_phy4: emdio1_phy@4 {
6601 + reg = <0x13>;
6602 + phy-connection-type = "xfi";
6603 + };
6604 };
6605  
6606 -&dspi {
6607 - status = "okay";
6608 - dflash0: n25q512a {
6609 - #address-cells = <1>;
6610 - #size-cells = <1>;
6611 - compatible = "st,m25p80";
6612 - spi-max-frequency = <3000000>;
6613 - reg = <0>;
6614 +&emdio2 {
6615 + /* AQR405 PHYs */
6616 + mdio2_phy1: emdio2_phy@1 {
6617 + compatible = "ethernet-phy-ieee802.3-c45";
6618 + interrupts = <0 1 0x4>; /* Level high type */
6619 + reg = <0x0>;
6620 + phy-connection-type = "xfi";
6621 + };
6622 + mdio2_phy2: emdio2_phy@2 {
6623 + compatible = "ethernet-phy-ieee802.3-c45";
6624 + interrupts = <0 2 0x4>; /* Level high type */
6625 + reg = <0x1>;
6626 + phy-connection-type = "xfi";
6627 + };
6628 + mdio2_phy3: emdio2_phy@3 {
6629 + compatible = "ethernet-phy-ieee802.3-c45";
6630 + interrupts = <0 4 0x4>; /* Level high type */
6631 + reg = <0x2>;
6632 + phy-connection-type = "xfi";
6633 + };
6634 + mdio2_phy4: emdio2_phy@4 {
6635 + compatible = "ethernet-phy-ieee802.3-c45";
6636 + interrupts = <0 5 0x4>; /* Level high type */
6637 + reg = <0x3>;
6638 + phy-connection-type = "xfi";
6639 };
6640 };
6641  
6642 -&qspi {
6643 - status = "disabled";
6644 -};
6645 +/* Update DPMAC connections to external PHYs, under the assumption of
6646 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
6647 + */
6648 +/* Leave Cortina nodes commented out until driver is integrated
6649 + *&dpmac1 {
6650 + * phy-handle = <&mdio1_phy1>;
6651 + *};
6652 + *&dpmac2 {
6653 + * phy-handle = <&mdio1_phy2>;
6654 + *};
6655 + *&dpmac3 {
6656 + * phy-handle = <&mdio1_phy3>;
6657 + *};
6658 + *&dpmac4 {
6659 + * phy-handle = <&mdio1_phy4>;
6660 + *};
6661 + */
6662  
6663 -&sata0 {
6664 - status = "okay";
6665 +&dpmac5 {
6666 + phy-handle = <&mdio2_phy1>;
6667 };
6668 -
6669 -&sata1 {
6670 - status = "okay";
6671 +&dpmac6 {
6672 + phy-handle = <&mdio2_phy2>;
6673 };
6674 -
6675 -&usb0 {
6676 - status = "okay";
6677 +&dpmac7 {
6678 + phy-handle = <&mdio2_phy3>;
6679 };
6680 -
6681 -&usb1 {
6682 - status = "okay";
6683 +&dpmac8 {
6684 + phy-handle = <&mdio2_phy4>;
6685 };
6686 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6687 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6688 @@ -1,7 +1,7 @@
6689 /*
6690 * Device Tree file for Freescale LS2080a software Simulator model
6691 *
6692 - * Copyright (C) 2014-2015, Freescale Semiconductor
6693 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
6694 *
6695 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6696 *
6697 @@ -46,17 +46,12 @@
6698  
6699 /dts-v1/;
6700  
6701 -/include/ "fsl-ls2080a.dtsi"
6702 +#include "fsl-ls2080a.dtsi"
6703  
6704 / {
6705 model = "Freescale Layerscape 2080a software Simulator model";
6706 compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
6707  
6708 - aliases {
6709 - serial0 = &serial0;
6710 - serial1 = &serial1;
6711 - };
6712 -
6713 ethernet@2210000 {
6714 compatible = "smsc,lan91c111";
6715 reg = <0x0 0x2210000 0x0 0x100>;
6716 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6717 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6718 @@ -1,8 +1,9 @@
6719 /*
6720 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6721 *
6722 - * Copyright (C) 2014-2015, Freescale Semiconductor
6723 + * Copyright 2014-2016 Freescale Semiconductor, Inc.
6724 *
6725 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6726 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6727 *
6728 * This file is dual-licensed: you can use it either under the terms
6729 @@ -44,696 +45,132 @@
6730 * OTHER DEALINGS IN THE SOFTWARE.
6731 */
6732  
6733 -/ {
6734 - compatible = "fsl,ls2080a";
6735 - interrupt-parent = <&gic>;
6736 - #address-cells = <2>;
6737 - #size-cells = <2>;
6738 -
6739 - cpus {
6740 - #address-cells = <1>;
6741 - #size-cells = <0>;
6742 -
6743 - /*
6744 - * We expect the enable-method for cpu's to be "psci", but this
6745 - * is dependent on the SoC FW, which will fill this in.
6746 - *
6747 - * Currently supported enable-method is psci v0.2
6748 - */
6749 -
6750 - /* We have 4 clusters having 2 Cortex-A57 cores each */
6751 - cpu@0 {
6752 - device_type = "cpu";
6753 - compatible = "arm,cortex-a57";
6754 - reg = <0x0>;
6755 - clocks = <&clockgen 1 0>;
6756 - next-level-cache = <&cluster0_l2>;
6757 - };
6758 -
6759 - cpu@1 {
6760 - device_type = "cpu";
6761 - compatible = "arm,cortex-a57";
6762 - reg = <0x1>;
6763 - clocks = <&clockgen 1 0>;
6764 - next-level-cache = <&cluster0_l2>;
6765 - };
6766 -
6767 - cpu@100 {
6768 - device_type = "cpu";
6769 - compatible = "arm,cortex-a57";
6770 - reg = <0x100>;
6771 - clocks = <&clockgen 1 1>;
6772 - next-level-cache = <&cluster1_l2>;
6773 - };
6774 -
6775 - cpu@101 {
6776 - device_type = "cpu";
6777 - compatible = "arm,cortex-a57";
6778 - reg = <0x101>;
6779 - clocks = <&clockgen 1 1>;
6780 - next-level-cache = <&cluster1_l2>;
6781 - };
6782 -
6783 - cpu@200 {
6784 - device_type = "cpu";
6785 - compatible = "arm,cortex-a57";
6786 - reg = <0x200>;
6787 - clocks = <&clockgen 1 2>;
6788 - next-level-cache = <&cluster2_l2>;
6789 - };
6790 -
6791 - cpu@201 {
6792 - device_type = "cpu";
6793 - compatible = "arm,cortex-a57";
6794 - reg = <0x201>;
6795 - clocks = <&clockgen 1 2>;
6796 - next-level-cache = <&cluster2_l2>;
6797 - };
6798 -
6799 - cpu@300 {
6800 - device_type = "cpu";
6801 - compatible = "arm,cortex-a57";
6802 - reg = <0x300>;
6803 - clocks = <&clockgen 1 3>;
6804 - next-level-cache = <&cluster3_l2>;
6805 - };
6806 -
6807 - cpu@301 {
6808 - device_type = "cpu";
6809 - compatible = "arm,cortex-a57";
6810 - reg = <0x301>;
6811 - clocks = <&clockgen 1 3>;
6812 - next-level-cache = <&cluster3_l2>;
6813 - };
6814 -
6815 - cluster0_l2: l2-cache0 {
6816 - compatible = "cache";
6817 - };
6818 -
6819 - cluster1_l2: l2-cache1 {
6820 - compatible = "cache";
6821 - };
6822 -
6823 - cluster2_l2: l2-cache2 {
6824 - compatible = "cache";
6825 - };
6826 -
6827 - cluster3_l2: l2-cache3 {
6828 - compatible = "cache";
6829 - };
6830 - };
6831 -
6832 - memory@80000000 {
6833 - device_type = "memory";
6834 - reg = <0x00000000 0x80000000 0 0x80000000>;
6835 - /* DRAM space - 1, size : 2 GB DRAM */
6836 - };
6837 -
6838 - sysclk: sysclk {
6839 - compatible = "fixed-clock";
6840 - #clock-cells = <0>;
6841 - clock-frequency = <100000000>;
6842 - clock-output-names = "sysclk";
6843 - };
6844 -
6845 - gic: interrupt-controller@6000000 {
6846 - compatible = "arm,gic-v3";
6847 - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
6848 - <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
6849 - <0x0 0x0c0c0000 0 0x2000>, /* GICC */
6850 - <0x0 0x0c0d0000 0 0x1000>, /* GICH */
6851 - <0x0 0x0c0e0000 0 0x20000>; /* GICV */
6852 - #interrupt-cells = <3>;
6853 - #address-cells = <2>;
6854 - #size-cells = <2>;
6855 - ranges;
6856 - interrupt-controller;
6857 - interrupts = <1 9 0x4>;
6858 -
6859 - its: gic-its@6020000 {
6860 - compatible = "arm,gic-v3-its";
6861 - msi-controller;
6862 - reg = <0x0 0x6020000 0 0x20000>;
6863 - };
6864 - };
6865 -
6866 - rstcr: syscon@1e60000 {
6867 - compatible = "fsl,ls2080a-rstcr", "syscon";
6868 - reg = <0x0 0x1e60000 0x0 0x4>;
6869 - };
6870 -
6871 - reboot {
6872 - compatible ="syscon-reboot";
6873 - regmap = <&rstcr>;
6874 - offset = <0x0>;
6875 - mask = <0x2>;
6876 - };
6877 -
6878 - timer {
6879 - compatible = "arm,armv8-timer";
6880 - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
6881 - <1 14 4>, /* Physical Non-Secure PPI, active-low */
6882 - <1 11 4>, /* Virtual PPI, active-low */
6883 - <1 10 4>; /* Hypervisor PPI, active-low */
6884 - fsl,erratum-a008585;
6885 - };
6886 -
6887 - pmu {
6888 - compatible = "arm,armv8-pmuv3";
6889 - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
6890 - };
6891 -
6892 - soc {
6893 - compatible = "simple-bus";
6894 - #address-cells = <2>;
6895 - #size-cells = <2>;
6896 - ranges;
6897 -
6898 - clockgen: clocking@1300000 {
6899 - compatible = "fsl,ls2080a-clockgen";
6900 - reg = <0 0x1300000 0 0xa0000>;
6901 - #clock-cells = <2>;
6902 - clocks = <&sysclk>;
6903 - };
6904 -
6905 - serial0: serial@21c0500 {
6906 - compatible = "fsl,ns16550", "ns16550a";
6907 - reg = <0x0 0x21c0500 0x0 0x100>;
6908 - clocks = <&clockgen 4 3>;
6909 - interrupts = <0 32 0x4>; /* Level high type */
6910 - };
6911 -
6912 - serial1: serial@21c0600 {
6913 - compatible = "fsl,ns16550", "ns16550a";
6914 - reg = <0x0 0x21c0600 0x0 0x100>;
6915 - clocks = <&clockgen 4 3>;
6916 - interrupts = <0 32 0x4>; /* Level high type */
6917 - };
6918 -
6919 - cluster1_core0_watchdog: wdt@c000000 {
6920 - compatible = "arm,sp805-wdt", "arm,primecell";
6921 - reg = <0x0 0xc000000 0x0 0x1000>;
6922 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6923 - clock-names = "apb_pclk", "wdog_clk";
6924 - };
6925 -
6926 - cluster1_core1_watchdog: wdt@c010000 {
6927 - compatible = "arm,sp805-wdt", "arm,primecell";
6928 - reg = <0x0 0xc010000 0x0 0x1000>;
6929 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6930 - clock-names = "apb_pclk", "wdog_clk";
6931 - };
6932 -
6933 - cluster2_core0_watchdog: wdt@c100000 {
6934 - compatible = "arm,sp805-wdt", "arm,primecell";
6935 - reg = <0x0 0xc100000 0x0 0x1000>;
6936 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6937 - clock-names = "apb_pclk", "wdog_clk";
6938 - };
6939 -
6940 - cluster2_core1_watchdog: wdt@c110000 {
6941 - compatible = "arm,sp805-wdt", "arm,primecell";
6942 - reg = <0x0 0xc110000 0x0 0x1000>;
6943 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6944 - clock-names = "apb_pclk", "wdog_clk";
6945 - };
6946 -
6947 - cluster3_core0_watchdog: wdt@c200000 {
6948 - compatible = "arm,sp805-wdt", "arm,primecell";
6949 - reg = <0x0 0xc200000 0x0 0x1000>;
6950 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6951 - clock-names = "apb_pclk", "wdog_clk";
6952 - };
6953 -
6954 - cluster3_core1_watchdog: wdt@c210000 {
6955 - compatible = "arm,sp805-wdt", "arm,primecell";
6956 - reg = <0x0 0xc210000 0x0 0x1000>;
6957 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6958 - clock-names = "apb_pclk", "wdog_clk";
6959 - };
6960 -
6961 - cluster4_core0_watchdog: wdt@c300000 {
6962 - compatible = "arm,sp805-wdt", "arm,primecell";
6963 - reg = <0x0 0xc300000 0x0 0x1000>;
6964 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6965 - clock-names = "apb_pclk", "wdog_clk";
6966 - };
6967 -
6968 - cluster4_core1_watchdog: wdt@c310000 {
6969 - compatible = "arm,sp805-wdt", "arm,primecell";
6970 - reg = <0x0 0xc310000 0x0 0x1000>;
6971 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6972 - clock-names = "apb_pclk", "wdog_clk";
6973 - };
6974 -
6975 - fsl_mc: fsl-mc@80c000000 {
6976 - compatible = "fsl,qoriq-mc";
6977 - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
6978 - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
6979 - msi-parent = <&its>;
6980 - #address-cells = <3>;
6981 - #size-cells = <1>;
6982 -
6983 - /*
6984 - * Region type 0x0 - MC portals
6985 - * Region type 0x1 - QBMAN portals
6986 - */
6987 - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
6988 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
6989 -
6990 - /*
6991 - * Define the maximum number of MACs present on the SoC.
6992 - */
6993 - dpmacs {
6994 - #address-cells = <1>;
6995 - #size-cells = <0>;
6996 -
6997 - dpmac1: dpmac@1 {
6998 - compatible = "fsl,qoriq-mc-dpmac";
6999 - reg = <0x1>;
7000 - };
7001 -
7002 - dpmac2: dpmac@2 {
7003 - compatible = "fsl,qoriq-mc-dpmac";
7004 - reg = <0x2>;
7005 - };
7006 -
7007 - dpmac3: dpmac@3 {
7008 - compatible = "fsl,qoriq-mc-dpmac";
7009 - reg = <0x3>;
7010 - };
7011 -
7012 - dpmac4: dpmac@4 {
7013 - compatible = "fsl,qoriq-mc-dpmac";
7014 - reg = <0x4>;
7015 - };
7016 -
7017 - dpmac5: dpmac@5 {
7018 - compatible = "fsl,qoriq-mc-dpmac";
7019 - reg = <0x5>;
7020 - };
7021 -
7022 - dpmac6: dpmac@6 {
7023 - compatible = "fsl,qoriq-mc-dpmac";
7024 - reg = <0x6>;
7025 - };
7026 -
7027 - dpmac7: dpmac@7 {
7028 - compatible = "fsl,qoriq-mc-dpmac";
7029 - reg = <0x7>;
7030 - };
7031 -
7032 - dpmac8: dpmac@8 {
7033 - compatible = "fsl,qoriq-mc-dpmac";
7034 - reg = <0x8>;
7035 - };
7036 -
7037 - dpmac9: dpmac@9 {
7038 - compatible = "fsl,qoriq-mc-dpmac";
7039 - reg = <0x9>;
7040 - };
7041 -
7042 - dpmac10: dpmac@a {
7043 - compatible = "fsl,qoriq-mc-dpmac";
7044 - reg = <0xa>;
7045 - };
7046 -
7047 - dpmac11: dpmac@b {
7048 - compatible = "fsl,qoriq-mc-dpmac";
7049 - reg = <0xb>;
7050 - };
7051 -
7052 - dpmac12: dpmac@c {
7053 - compatible = "fsl,qoriq-mc-dpmac";
7054 - reg = <0xc>;
7055 - };
7056 -
7057 - dpmac13: dpmac@d {
7058 - compatible = "fsl,qoriq-mc-dpmac";
7059 - reg = <0xd>;
7060 - };
7061 -
7062 - dpmac14: dpmac@e {
7063 - compatible = "fsl,qoriq-mc-dpmac";
7064 - reg = <0xe>;
7065 - };
7066 -
7067 - dpmac15: dpmac@f {
7068 - compatible = "fsl,qoriq-mc-dpmac";
7069 - reg = <0xf>;
7070 - };
7071 -
7072 - dpmac16: dpmac@10 {
7073 - compatible = "fsl,qoriq-mc-dpmac";
7074 - reg = <0x10>;
7075 - };
7076 - };
7077 - };
7078 -
7079 - smmu: iommu@5000000 {
7080 - compatible = "arm,mmu-500";
7081 - reg = <0 0x5000000 0 0x800000>;
7082 - #global-interrupts = <12>;
7083 - interrupts = <0 13 4>, /* global secure fault */
7084 - <0 14 4>, /* combined secure interrupt */
7085 - <0 15 4>, /* global non-secure fault */
7086 - <0 16 4>, /* combined non-secure interrupt */
7087 - /* performance counter interrupts 0-7 */
7088 - <0 211 4>, <0 212 4>,
7089 - <0 213 4>, <0 214 4>,
7090 - <0 215 4>, <0 216 4>,
7091 - <0 217 4>, <0 218 4>,
7092 - /* per context interrupt, 64 interrupts */
7093 - <0 146 4>, <0 147 4>,
7094 - <0 148 4>, <0 149 4>,
7095 - <0 150 4>, <0 151 4>,
7096 - <0 152 4>, <0 153 4>,
7097 - <0 154 4>, <0 155 4>,
7098 - <0 156 4>, <0 157 4>,
7099 - <0 158 4>, <0 159 4>,
7100 - <0 160 4>, <0 161 4>,
7101 - <0 162 4>, <0 163 4>,
7102 - <0 164 4>, <0 165 4>,
7103 - <0 166 4>, <0 167 4>,
7104 - <0 168 4>, <0 169 4>,
7105 - <0 170 4>, <0 171 4>,
7106 - <0 172 4>, <0 173 4>,
7107 - <0 174 4>, <0 175 4>,
7108 - <0 176 4>, <0 177 4>,
7109 - <0 178 4>, <0 179 4>,
7110 - <0 180 4>, <0 181 4>,
7111 - <0 182 4>, <0 183 4>,
7112 - <0 184 4>, <0 185 4>,
7113 - <0 186 4>, <0 187 4>,
7114 - <0 188 4>, <0 189 4>,
7115 - <0 190 4>, <0 191 4>,
7116 - <0 192 4>, <0 193 4>,
7117 - <0 194 4>, <0 195 4>,
7118 - <0 196 4>, <0 197 4>,
7119 - <0 198 4>, <0 199 4>,
7120 - <0 200 4>, <0 201 4>,
7121 - <0 202 4>, <0 203 4>,
7122 - <0 204 4>, <0 205 4>,
7123 - <0 206 4>, <0 207 4>,
7124 - <0 208 4>, <0 209 4>;
7125 - mmu-masters = <&fsl_mc 0x300 0>;
7126 - };
7127 -
7128 - dspi: dspi@2100000 {
7129 - status = "disabled";
7130 - compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
7131 - #address-cells = <1>;
7132 - #size-cells = <0>;
7133 - reg = <0x0 0x2100000 0x0 0x10000>;
7134 - interrupts = <0 26 0x4>; /* Level high type */
7135 - clocks = <&clockgen 4 3>;
7136 - clock-names = "dspi";
7137 - spi-num-chipselects = <5>;
7138 - bus-num = <0>;
7139 - };
7140 -
7141 - esdhc: esdhc@2140000 {
7142 - status = "disabled";
7143 - compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
7144 - reg = <0x0 0x2140000 0x0 0x10000>;
7145 - interrupts = <0 28 0x4>; /* Level high type */
7146 - clock-frequency = <0>; /* Updated by bootloader */
7147 - voltage-ranges = <1800 1800 3300 3300>;
7148 - sdhci,auto-cmd12;
7149 - little-endian;
7150 - bus-width = <4>;
7151 - };
7152 -
7153 - gpio0: gpio@2300000 {
7154 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7155 - reg = <0x0 0x2300000 0x0 0x10000>;
7156 - interrupts = <0 36 0x4>; /* Level high type */
7157 - gpio-controller;
7158 - little-endian;
7159 - #gpio-cells = <2>;
7160 - interrupt-controller;
7161 - #interrupt-cells = <2>;
7162 - };
7163 -
7164 - gpio1: gpio@2310000 {
7165 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7166 - reg = <0x0 0x2310000 0x0 0x10000>;
7167 - interrupts = <0 36 0x4>; /* Level high type */
7168 - gpio-controller;
7169 - little-endian;
7170 - #gpio-cells = <2>;
7171 - interrupt-controller;
7172 - #interrupt-cells = <2>;
7173 - };
7174 -
7175 - gpio2: gpio@2320000 {
7176 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7177 - reg = <0x0 0x2320000 0x0 0x10000>;
7178 - interrupts = <0 37 0x4>; /* Level high type */
7179 - gpio-controller;
7180 - little-endian;
7181 - #gpio-cells = <2>;
7182 - interrupt-controller;
7183 - #interrupt-cells = <2>;
7184 - };
7185 -
7186 - gpio3: gpio@2330000 {
7187 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7188 - reg = <0x0 0x2330000 0x0 0x10000>;
7189 - interrupts = <0 37 0x4>; /* Level high type */
7190 - gpio-controller;
7191 - little-endian;
7192 - #gpio-cells = <2>;
7193 - interrupt-controller;
7194 - #interrupt-cells = <2>;
7195 - };
7196 -
7197 - i2c0: i2c@2000000 {
7198 - status = "disabled";
7199 - compatible = "fsl,vf610-i2c";
7200 - #address-cells = <1>;
7201 - #size-cells = <0>;
7202 - reg = <0x0 0x2000000 0x0 0x10000>;
7203 - interrupts = <0 34 0x4>; /* Level high type */
7204 - clock-names = "i2c";
7205 - clocks = <&clockgen 4 3>;
7206 - };
7207 -
7208 - i2c1: i2c@2010000 {
7209 - status = "disabled";
7210 - compatible = "fsl,vf610-i2c";
7211 - #address-cells = <1>;
7212 - #size-cells = <0>;
7213 - reg = <0x0 0x2010000 0x0 0x10000>;
7214 - interrupts = <0 34 0x4>; /* Level high type */
7215 - clock-names = "i2c";
7216 - clocks = <&clockgen 4 3>;
7217 - };
7218 -
7219 - i2c2: i2c@2020000 {
7220 - status = "disabled";
7221 - compatible = "fsl,vf610-i2c";
7222 - #address-cells = <1>;
7223 - #size-cells = <0>;
7224 - reg = <0x0 0x2020000 0x0 0x10000>;
7225 - interrupts = <0 35 0x4>; /* Level high type */
7226 - clock-names = "i2c";
7227 - clocks = <&clockgen 4 3>;
7228 - };
7229 -
7230 - i2c3: i2c@2030000 {
7231 - status = "disabled";
7232 - compatible = "fsl,vf610-i2c";
7233 - #address-cells = <1>;
7234 - #size-cells = <0>;
7235 - reg = <0x0 0x2030000 0x0 0x10000>;
7236 - interrupts = <0 35 0x4>; /* Level high type */
7237 - clock-names = "i2c";
7238 - clocks = <&clockgen 4 3>;
7239 - };
7240 -
7241 - ifc: ifc@2240000 {
7242 - compatible = "fsl,ifc", "simple-bus";
7243 - reg = <0x0 0x2240000 0x0 0x20000>;
7244 - interrupts = <0 21 0x4>; /* Level high type */
7245 - little-endian;
7246 - #address-cells = <2>;
7247 - #size-cells = <1>;
7248 -
7249 - ranges = <0 0 0x5 0x80000000 0x08000000
7250 - 2 0 0x5 0x30000000 0x00010000
7251 - 3 0 0x5 0x20000000 0x00010000>;
7252 - };
7253 -
7254 - qspi: quadspi@20c0000 {
7255 - status = "disabled";
7256 - compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
7257 - #address-cells = <1>;
7258 - #size-cells = <0>;
7259 - reg = <0x0 0x20c0000 0x0 0x10000>,
7260 - <0x0 0x20000000 0x0 0x10000000>;
7261 - reg-names = "QuadSPI", "QuadSPI-memory";
7262 - interrupts = <0 25 0x4>; /* Level high type */
7263 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7264 - clock-names = "qspi_en", "qspi";
7265 - };
7266 -
7267 - pcie@3400000 {
7268 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7269 - "snps,dw-pcie";
7270 - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7271 - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7272 - reg-names = "regs", "config";
7273 - interrupts = <0 108 0x4>; /* Level high type */
7274 - interrupt-names = "intr";
7275 - #address-cells = <3>;
7276 - #size-cells = <2>;
7277 - device_type = "pci";
7278 - dma-coherent;
7279 - num-lanes = <4>;
7280 - bus-range = <0x0 0xff>;
7281 - ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7282 - 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7283 - msi-parent = <&its>;
7284 - #interrupt-cells = <1>;
7285 - interrupt-map-mask = <0 0 0 7>;
7286 - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
7287 - <0000 0 0 2 &gic 0 0 0 110 4>,
7288 - <0000 0 0 3 &gic 0 0 0 111 4>,
7289 - <0000 0 0 4 &gic 0 0 0 112 4>;
7290 - };
7291 -
7292 - pcie@3500000 {
7293 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7294 - "snps,dw-pcie";
7295 - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7296 - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7297 - reg-names = "regs", "config";
7298 - interrupts = <0 113 0x4>; /* Level high type */
7299 - interrupt-names = "intr";
7300 - #address-cells = <3>;
7301 - #size-cells = <2>;
7302 - device_type = "pci";
7303 - dma-coherent;
7304 - num-lanes = <4>;
7305 - bus-range = <0x0 0xff>;
7306 - ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7307 - 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7308 - msi-parent = <&its>;
7309 - #interrupt-cells = <1>;
7310 - interrupt-map-mask = <0 0 0 7>;
7311 - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
7312 - <0000 0 0 2 &gic 0 0 0 115 4>,
7313 - <0000 0 0 3 &gic 0 0 0 116 4>,
7314 - <0000 0 0 4 &gic 0 0 0 117 4>;
7315 - };
7316 -
7317 - pcie@3600000 {
7318 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7319 - "snps,dw-pcie";
7320 - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7321 - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7322 - reg-names = "regs", "config";
7323 - interrupts = <0 118 0x4>; /* Level high type */
7324 - interrupt-names = "intr";
7325 - #address-cells = <3>;
7326 - #size-cells = <2>;
7327 - device_type = "pci";
7328 - dma-coherent;
7329 - num-lanes = <8>;
7330 - bus-range = <0x0 0xff>;
7331 - ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7332 - 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7333 - msi-parent = <&its>;
7334 - #interrupt-cells = <1>;
7335 - interrupt-map-mask = <0 0 0 7>;
7336 - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
7337 - <0000 0 0 2 &gic 0 0 0 120 4>,
7338 - <0000 0 0 3 &gic 0 0 0 121 4>,
7339 - <0000 0 0 4 &gic 0 0 0 122 4>;
7340 - };
7341 -
7342 - pcie@3700000 {
7343 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7344 - "snps,dw-pcie";
7345 - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7346 - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7347 - reg-names = "regs", "config";
7348 - interrupts = <0 123 0x4>; /* Level high type */
7349 - interrupt-names = "intr";
7350 - #address-cells = <3>;
7351 - #size-cells = <2>;
7352 - device_type = "pci";
7353 - dma-coherent;
7354 - num-lanes = <4>;
7355 - bus-range = <0x0 0xff>;
7356 - ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7357 - 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7358 - msi-parent = <&its>;
7359 - #interrupt-cells = <1>;
7360 - interrupt-map-mask = <0 0 0 7>;
7361 - interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
7362 - <0000 0 0 2 &gic 0 0 0 125 4>,
7363 - <0000 0 0 3 &gic 0 0 0 126 4>,
7364 - <0000 0 0 4 &gic 0 0 0 127 4>;
7365 - };
7366 -
7367 - sata0: sata@3200000 {
7368 - status = "disabled";
7369 - compatible = "fsl,ls2080a-ahci";
7370 - reg = <0x0 0x3200000 0x0 0x10000>;
7371 - interrupts = <0 133 0x4>; /* Level high type */
7372 - clocks = <&clockgen 4 3>;
7373 - dma-coherent;
7374 - };
7375 -
7376 - sata1: sata@3210000 {
7377 - status = "disabled";
7378 - compatible = "fsl,ls2080a-ahci";
7379 - reg = <0x0 0x3210000 0x0 0x10000>;
7380 - interrupts = <0 136 0x4>; /* Level high type */
7381 - clocks = <&clockgen 4 3>;
7382 - dma-coherent;
7383 - };
7384 -
7385 - usb0: usb3@3100000 {
7386 - status = "disabled";
7387 - compatible = "snps,dwc3";
7388 - reg = <0x0 0x3100000 0x0 0x10000>;
7389 - interrupts = <0 80 0x4>; /* Level high type */
7390 - dr_mode = "host";
7391 - snps,quirk-frame-length-adjustment = <0x20>;
7392 - snps,dis_rxdet_inp3_quirk;
7393 - };
7394 -
7395 - usb1: usb3@3110000 {
7396 - status = "disabled";
7397 - compatible = "snps,dwc3";
7398 - reg = <0x0 0x3110000 0x0 0x10000>;
7399 - interrupts = <0 81 0x4>; /* Level high type */
7400 - dr_mode = "host";
7401 - snps,quirk-frame-length-adjustment = <0x20>;
7402 - snps,dis_rxdet_inp3_quirk;
7403 - };
7404 -
7405 - ccn@4000000 {
7406 - compatible = "arm,ccn-504";
7407 - reg = <0x0 0x04000000 0x0 0x01000000>;
7408 - interrupts = <0 12 4>;
7409 - };
7410 - };
7411 -
7412 - ddr1: memory-controller@1080000 {
7413 - compatible = "fsl,qoriq-memory-controller";
7414 - reg = <0x0 0x1080000 0x0 0x1000>;
7415 - interrupts = <0 17 0x4>;
7416 - little-endian;
7417 - };
7418 -
7419 - ddr2: memory-controller@1090000 {
7420 - compatible = "fsl,qoriq-memory-controller";
7421 - reg = <0x0 0x1090000 0x0 0x1000>;
7422 - interrupts = <0 18 0x4>;
7423 - little-endian;
7424 +#include "fsl-ls208xa.dtsi"
7425 +
7426 +&cpu {
7427 + cpu0: cpu@0 {
7428 + device_type = "cpu";
7429 + compatible = "arm,cortex-a57";
7430 + reg = <0x0>;
7431 + clocks = <&clockgen 1 0>;
7432 + next-level-cache = <&cluster0_l2>;
7433 + #cooling-cells = <2>;
7434 + };
7435 +
7436 + cpu1: cpu@1 {
7437 + device_type = "cpu";
7438 + compatible = "arm,cortex-a57";
7439 + reg = <0x1>;
7440 + clocks = <&clockgen 1 0>;
7441 + next-level-cache = <&cluster0_l2>;
7442 + };
7443 +
7444 + cpu2: cpu@100 {
7445 + device_type = "cpu";
7446 + compatible = "arm,cortex-a57";
7447 + reg = <0x100>;
7448 + clocks = <&clockgen 1 1>;
7449 + next-level-cache = <&cluster1_l2>;
7450 + #cooling-cells = <2>;
7451 + };
7452 +
7453 + cpu3: cpu@101 {
7454 + device_type = "cpu";
7455 + compatible = "arm,cortex-a57";
7456 + reg = <0x101>;
7457 + clocks = <&clockgen 1 1>;
7458 + next-level-cache = <&cluster1_l2>;
7459 + };
7460 +
7461 + cpu4: cpu@200 {
7462 + device_type = "cpu";
7463 + compatible = "arm,cortex-a57";
7464 + reg = <0x200>;
7465 + clocks = <&clockgen 1 2>;
7466 + next-level-cache = <&cluster2_l2>;
7467 + #cooling-cells = <2>;
7468 + };
7469 +
7470 + cpu5: cpu@201 {
7471 + device_type = "cpu";
7472 + compatible = "arm,cortex-a57";
7473 + reg = <0x201>;
7474 + clocks = <&clockgen 1 2>;
7475 + next-level-cache = <&cluster2_l2>;
7476 + };
7477 +
7478 + cpu6: cpu@300 {
7479 + device_type = "cpu";
7480 + compatible = "arm,cortex-a57";
7481 + reg = <0x300>;
7482 + clocks = <&clockgen 1 3>;
7483 + next-level-cache = <&cluster3_l2>;
7484 + #cooling-cells = <2>;
7485 + };
7486 +
7487 + cpu7: cpu@301 {
7488 + device_type = "cpu";
7489 + compatible = "arm,cortex-a57";
7490 + reg = <0x301>;
7491 + clocks = <&clockgen 1 3>;
7492 + next-level-cache = <&cluster3_l2>;
7493 };
7494 +
7495 + cluster0_l2: l2-cache0 {
7496 + compatible = "cache";
7497 + };
7498 +
7499 + cluster1_l2: l2-cache1 {
7500 + compatible = "cache";
7501 + };
7502 +
7503 + cluster2_l2: l2-cache2 {
7504 + compatible = "cache";
7505 + };
7506 +
7507 + cluster3_l2: l2-cache3 {
7508 + compatible = "cache";
7509 + };
7510 +};
7511 +
7512 +&usb0 {
7513 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7514 + snps,dma-snooping;
7515 +};
7516 +
7517 +&usb1 {
7518 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7519 + snps,dma-snooping;
7520 +};
7521 +
7522 +&pcie1 {
7523 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7524 + 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7525 +
7526 + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7527 + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7528 +};
7529 +
7530 +&pcie2 {
7531 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7532 + 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7533 +
7534 + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7535 + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7536 +};
7537 +
7538 +&pcie3 {
7539 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7540 + 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7541 +
7542 + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7543 + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7544 +};
7545 +
7546 +&pcie4 {
7547 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7548 + 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7549 +
7550 + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7551 + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7552 };
7553 --- /dev/null
7554 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
7555 @@ -0,0 +1,161 @@
7556 +/*
7557 + * Device Tree file for NXP LS2081A RDB Board.
7558 + *
7559 + * Copyright 2017 NXP
7560 + *
7561 + * Priyanka Jain <priyanka.jain@nxp.com>
7562 + *
7563 + * This file is dual-licensed: you can use it either under the terms
7564 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7565 + * licensing only applies to this file, and not this project as a
7566 + * whole.
7567 + *
7568 + * a) This library is free software; you can redistribute it and/or
7569 + * modify it under the terms of the GNU General Public License as
7570 + * published by the Free Software Foundation; either version 2 of the
7571 + * License, or (at your option) any later version.
7572 + *
7573 + * This library is distributed in the hope that it will be useful,
7574 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7575 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7576 + * GNU General Public License for more details.
7577 + *
7578 + * Or, alternatively,
7579 + *
7580 + * b) Permission is hereby granted, free of charge, to any person
7581 + * obtaining a copy of this software and associated documentation
7582 + * files (the "Software"), to deal in the Software without
7583 + * restriction, including without limitation the rights to use,
7584 + * copy, modify, merge, publish, distribute, sublicense, and/or
7585 + * sell copies of the Software, and to permit persons to whom the
7586 + * Software is furnished to do so, subject to the following
7587 + * conditions:
7588 + *
7589 + * The above copyright notice and this permission notice shall be
7590 + * included in all copies or substantial portions of the Software.
7591 + *
7592 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7593 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7594 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7595 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7596 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7597 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7598 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7599 + * OTHER DEALINGS IN THE SOFTWARE.
7600 + */
7601 +
7602 +/dts-v1/;
7603 +
7604 +#include "fsl-ls2088a.dtsi"
7605 +
7606 +/ {
7607 + model = "NXP Layerscape 2081A RDB Board";
7608 + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
7609 +
7610 + aliases {
7611 + serial0 = &serial0;
7612 + serial1 = &serial1;
7613 + };
7614 +
7615 + chosen {
7616 + stdout-path = "serial1:115200n8";
7617 + };
7618 +};
7619 +
7620 +&esdhc {
7621 + status = "okay";
7622 +};
7623 +
7624 +&ifc {
7625 + status = "disabled";
7626 +};
7627 +
7628 +&i2c0 {
7629 + status = "okay";
7630 + pca9547@75 {
7631 + compatible = "nxp,pca9547";
7632 + reg = <0x75>;
7633 + #address-cells = <1>;
7634 + #size-cells = <0>;
7635 + i2c@1 {
7636 + #address-cells = <1>;
7637 + #size-cells = <0>;
7638 + reg = <0x01>;
7639 + rtc@51 {
7640 + compatible = "nxp,pcf2129";
7641 + reg = <0x51>;
7642 + };
7643 + };
7644 +
7645 + i2c@2 {
7646 + #address-cells = <1>;
7647 + #size-cells = <0>;
7648 + reg = <0x02>;
7649 +
7650 + ina220@40 {
7651 + compatible = "ti,ina220";
7652 + reg = <0x40>;
7653 + shunt-resistor = <500>;
7654 + };
7655 + };
7656 +
7657 + i2c@3 {
7658 + #address-cells = <1>;
7659 + #size-cells = <0>;
7660 + reg = <0x3>;
7661 +
7662 + adt7481@4c {
7663 + compatible = "adi,adt7461";
7664 + reg = <0x4c>;
7665 + };
7666 + };
7667 + };
7668 +};
7669 +
7670 +&dspi {
7671 + status = "okay";
7672 + dflash0: n25q512a {
7673 + #address-cells = <1>;
7674 + #size-cells = <1>;
7675 + compatible = "st,m25p80";
7676 + spi-max-frequency = <3000000>;
7677 + reg = <0>;
7678 + };
7679 +};
7680 +
7681 +&qspi {
7682 + status = "okay";
7683 + fsl,qspi-has-second-chip;
7684 + flash0: s25fs512s@0 {
7685 + #address-cells = <1>;
7686 + #size-cells = <1>;
7687 + compatible = "spansion,m25p80";
7688 + m25p,fast-read;
7689 + spi-max-frequency = <20000000>;
7690 + reg = <0>;
7691 + };
7692 + flash1: s25fs512s@1 {
7693 + #address-cells = <1>;
7694 + #size-cells = <1>;
7695 + compatible = "spansion,m25p80";
7696 + m25p,fast-read;
7697 + spi-max-frequency = <20000000>;
7698 + reg = <1>;
7699 + };
7700 +};
7701 +
7702 +&sata0 {
7703 + status = "okay";
7704 +};
7705 +
7706 +&sata1 {
7707 + status = "okay";
7708 +};
7709 +
7710 +&usb0 {
7711 + status = "okay";
7712 +};
7713 +
7714 +&usb1 {
7715 + status = "okay";
7716 +};
7717 --- /dev/null
7718 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
7719 @@ -0,0 +1,162 @@
7720 +/*
7721 + * Device Tree file for Freescale LS2088A QDS Board.
7722 + *
7723 + * Copyright 2016 Freescale Semiconductor, Inc.
7724 + * Copyright 2017 NXP
7725 + *
7726 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7727 + *
7728 + * This file is dual-licensed: you can use it either under the terms
7729 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7730 + * licensing only applies to this file, and not this project as a
7731 + * whole.
7732 + *
7733 + * a) This library is free software; you can redistribute it and/or
7734 + * modify it under the terms of the GNU General Public License as
7735 + * published by the Free Software Foundation; either version 2 of the
7736 + * License, or (at your option) any later version.
7737 + *
7738 + * This library is distributed in the hope that it will be useful,
7739 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7740 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7741 + * GNU General Public License for more details.
7742 + *
7743 + * Or, alternatively,
7744 + *
7745 + * b) Permission is hereby granted, free of charge, to any person
7746 + * obtaining a copy of this software and associated documentation
7747 + * files (the "Software"), to deal in the Software without
7748 + * restriction, including without limitation the rights to use,
7749 + * copy, modify, merge, publish, distribute, sublicense, and/or
7750 + * sell copies of the Software, and to permit persons to whom the
7751 + * Software is furnished to do so, subject to the following
7752 + * conditions:
7753 + *
7754 + * The above copyright notice and this permission notice shall be
7755 + * included in all copies or substantial portions of the Software.
7756 + *
7757 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7758 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7759 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7760 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7761 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7762 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7763 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7764 + * OTHER DEALINGS IN THE SOFTWARE.
7765 + */
7766 +
7767 +/dts-v1/;
7768 +
7769 +#include "fsl-ls2088a.dtsi"
7770 +#include "fsl-ls208xa-qds.dtsi"
7771 +
7772 +/ {
7773 + model = "Freescale Layerscape 2088A QDS Board";
7774 + compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
7775 +
7776 + chosen {
7777 + stdout-path = "serial0:115200n8";
7778 + };
7779 +};
7780 +
7781 +&ifc {
7782 + boardctrl: board-control@3,0 {
7783 + #address-cells = <1>;
7784 + #size-cells = <1>;
7785 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
7786 + reg = <3 0 0x300>; /* TODO check address */
7787 + ranges = <0 3 0 0x300>;
7788 +
7789 + mdio_mux_emi1 {
7790 + compatible = "mdio-mux-mmioreg", "mdio-mux";
7791 + mdio-parent-bus = <&emdio1>;
7792 + reg = <0x54 1>; /* BRDCFG4 */
7793 + mux-mask = <0xe0>; /* EMI1_MDIO */
7794 +
7795 + #address-cells=<1>;
7796 + #size-cells = <0>;
7797 +
7798 + /* Child MDIO buses, one for each riser card:
7799 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
7800 + * VSC8234 PHYs on the riser cards.
7801 + */
7802 +
7803 + mdio_mux3: mdio@60 {
7804 + reg = <0x60>;
7805 + #address-cells = <1>;
7806 + #size-cells = <0>;
7807 +
7808 + mdio0_phy12: mdio_phy0@1c {
7809 + reg = <0x1c>;
7810 + phy-connection-type = "sgmii";
7811 + };
7812 + mdio0_phy13: mdio_phy1@1d {
7813 + reg = <0x1d>;
7814 + phy-connection-type = "sgmii";
7815 + };
7816 + mdio0_phy14: mdio_phy2@1e {
7817 + reg = <0x1e>;
7818 + phy-connection-type = "sgmii";
7819 + };
7820 + mdio0_phy15: mdio_phy3@1f {
7821 + reg = <0x1f>;
7822 + phy-connection-type = "sgmii";
7823 + };
7824 + };
7825 + };
7826 + };
7827 +};
7828 +
7829 +&pcs_mdio1 {
7830 + pcs_phy1: ethernet-phy@0 {
7831 + backplane-mode = "10gbase-kr";
7832 + compatible = "ethernet-phy-ieee802.3-c45";
7833 + reg = <0x0>;
7834 + fsl,lane-handle = <&serdes1>;
7835 + fsl,lane-reg = <0x9C0 0x40>;/* lane H */
7836 + };
7837 +};
7838 +
7839 +&pcs_mdio2 {
7840 + pcs_phy2: ethernet-phy@0 {
7841 + backplane-mode = "10gbase-kr";
7842 + compatible = "ethernet-phy-ieee802.3-c45";
7843 + reg = <0x0>;
7844 + fsl,lane-handle = <&serdes1>;
7845 + fsl,lane-reg = <0x980 0x40>;/* lane G */
7846 + };
7847 +};
7848 +
7849 +&pcs_mdio3 {
7850 + pcs_phy3: ethernet-phy@0 {
7851 + backplane-mode = "10gbase-kr";
7852 + compatible = "ethernet-phy-ieee802.3-c45";
7853 + reg = <0x0>;
7854 + fsl,lane-handle = <&serdes1>;
7855 + fsl,lane-reg = <0x940 0x40>;/* lane F */
7856 + };
7857 +};
7858 +
7859 +&pcs_mdio4 {
7860 + pcs_phy4: ethernet-phy@0 {
7861 + backplane-mode = "10gbase-kr";
7862 + compatible = "ethernet-phy-ieee802.3-c45";
7863 + reg = <0x0>;
7864 + fsl,lane-handle = <&serdes1>;
7865 + fsl,lane-reg = <0x900 0x40>;/* lane E */
7866 + };
7867 +};
7868 +
7869 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
7870 +&dpmac9 {
7871 + phy-handle = <&mdio0_phy12>;
7872 +};
7873 +&dpmac10 {
7874 + phy-handle = <&mdio0_phy13>;
7875 +};
7876 +&dpmac11 {
7877 + phy-handle = <&mdio0_phy14>;
7878 +};
7879 +&dpmac12 {
7880 + phy-handle = <&mdio0_phy15>;
7881 +};
7882 --- /dev/null
7883 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
7884 @@ -0,0 +1,140 @@
7885 +/*
7886 + * Device Tree file for Freescale LS2088A RDB Board.
7887 + *
7888 + * Copyright 2016 Freescale Semiconductor, Inc.
7889 + * Copyright 2017 NXP
7890 + *
7891 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7892 + *
7893 + * This file is dual-licensed: you can use it either under the terms
7894 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7895 + * licensing only applies to this file, and not this project as a
7896 + * whole.
7897 + *
7898 + * a) This library is free software; you can redistribute it and/or
7899 + * modify it under the terms of the GNU General Public License as
7900 + * published by the Free Software Foundation; either version 2 of the
7901 + * License, or (at your option) any later version.
7902 + *
7903 + * This library is distributed in the hope that it will be useful,
7904 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7905 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7906 + * GNU General Public License for more details.
7907 + *
7908 + * Or, alternatively,
7909 + *
7910 + * b) Permission is hereby granted, free of charge, to any person
7911 + * obtaining a copy of this software and associated documentation
7912 + * files (the "Software"), to deal in the Software without
7913 + * restriction, including without limitation the rights to use,
7914 + * copy, modify, merge, publish, distribute, sublicense, and/or
7915 + * sell copies of the Software, and to permit persons to whom the
7916 + * Software is furnished to do so, subject to the following
7917 + * conditions:
7918 + *
7919 + * The above copyright notice and this permission notice shall be
7920 + * included in all copies or substantial portions of the Software.
7921 + *
7922 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7923 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7924 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7925 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7926 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7927 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7928 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7929 + * OTHER DEALINGS IN THE SOFTWARE.
7930 + */
7931 +
7932 +/dts-v1/;
7933 +
7934 +#include "fsl-ls2088a.dtsi"
7935 +#include "fsl-ls208xa-rdb.dtsi"
7936 +
7937 +/ {
7938 + model = "Freescale Layerscape 2088A RDB Board";
7939 + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
7940 +
7941 + chosen {
7942 + stdout-path = "serial1:115200n8";
7943 + };
7944 +};
7945 +
7946 +&emdio1 {
7947 + status = "disabled";
7948 + /* CS4340 PHYs */
7949 + mdio1_phy1: emdio1_phy@1 {
7950 + reg = <0x10>;
7951 + phy-connection-type = "xfi";
7952 + };
7953 + mdio1_phy2: emdio1_phy@2 {
7954 + reg = <0x11>;
7955 + phy-connection-type = "xfi";
7956 + };
7957 + mdio1_phy3: emdio1_phy@3 {
7958 + reg = <0x12>;
7959 + phy-connection-type = "xfi";
7960 + };
7961 + mdio1_phy4: emdio1_phy@4 {
7962 + reg = <0x13>;
7963 + phy-connection-type = "xfi";
7964 + };
7965 +};
7966 +
7967 +&emdio2 {
7968 + /* AQR405 PHYs */
7969 + mdio2_phy1: emdio2_phy@1 {
7970 + compatible = "ethernet-phy-ieee802.3-c45";
7971 + interrupts = <0 1 0x4>; /* Level high type */
7972 + reg = <0x0>;
7973 + phy-connection-type = "xfi";
7974 + };
7975 + mdio2_phy2: emdio2_phy@2 {
7976 + compatible = "ethernet-phy-ieee802.3-c45";
7977 + interrupts = <0 2 0x4>; /* Level high type */
7978 + reg = <0x1>;
7979 + phy-connection-type = "xfi";
7980 + };
7981 + mdio2_phy3: emdio2_phy@3 {
7982 + compatible = "ethernet-phy-ieee802.3-c45";
7983 + interrupts = <0 4 0x4>; /* Level high type */
7984 + reg = <0x2>;
7985 + phy-connection-type = "xfi";
7986 + };
7987 + mdio2_phy4: emdio2_phy@4 {
7988 + compatible = "ethernet-phy-ieee802.3-c45";
7989 + interrupts = <0 5 0x4>; /* Level high type */
7990 + reg = <0x3>;
7991 + phy-connection-type = "xfi";
7992 + };
7993 +};
7994 +
7995 +/* Update DPMAC connections to external PHYs, under the assumption of
7996 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
7997 + */
7998 +/* Leave Cortina PHYs commented out until proper driver is integrated
7999 + *&dpmac1 {
8000 + * phy-handle = <&mdio1_phy1>;
8001 + *};
8002 + *&dpmac2 {
8003 + * phy-handle = <&mdio1_phy2>;
8004 + *};
8005 + *&dpmac3 {
8006 + * phy-handle = <&mdio1_phy3>;
8007 + *};
8008 + *&dpmac4 {
8009 + * phy-handle = <&mdio1_phy4>;
8010 + *};
8011 + */
8012 +
8013 +&dpmac5 {
8014 + phy-handle = <&mdio2_phy1>;
8015 +};
8016 +&dpmac6 {
8017 + phy-handle = <&mdio2_phy2>;
8018 +};
8019 +&dpmac7 {
8020 + phy-handle = <&mdio2_phy3>;
8021 +};
8022 +&dpmac8 {
8023 + phy-handle = <&mdio2_phy4>;
8024 +};
8025 --- /dev/null
8026 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
8027 @@ -0,0 +1,195 @@
8028 +/*
8029 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
8030 + *
8031 + * Copyright 2016 Freescale Semiconductor, Inc.
8032 + * Copyright 2017 NXP
8033 + *
8034 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8035 + *
8036 + * This file is dual-licensed: you can use it either under the terms
8037 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8038 + * licensing only applies to this file, and not this project as a
8039 + * whole.
8040 + *
8041 + * a) This library is free software; you can redistribute it and/or
8042 + * modify it under the terms of the GNU General Public License as
8043 + * published by the Free Software Foundation; either version 2 of the
8044 + * License, or (at your option) any later version.
8045 + *
8046 + * This library is distributed in the hope that it will be useful,
8047 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8048 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8049 + * GNU General Public License for more details.
8050 + *
8051 + * Or, alternatively,
8052 + *
8053 + * b) Permission is hereby granted, free of charge, to any person
8054 + * obtaining a copy of this software and associated documentation
8055 + * files (the "Software"), to deal in the Software without
8056 + * restriction, including without limitation the rights to use,
8057 + * copy, modify, merge, publish, distribute, sublicense, and/or
8058 + * sell copies of the Software, and to permit persons to whom the
8059 + * Software is furnished to do so, subject to the following
8060 + * conditions:
8061 + *
8062 + * The above copyright notice and this permission notice shall be
8063 + * included in all copies or substantial portions of the Software.
8064 + *
8065 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8066 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8067 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8068 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8069 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8070 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8071 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8072 + * OTHER DEALINGS IN THE SOFTWARE.
8073 + */
8074 +
8075 +#include "fsl-ls208xa.dtsi"
8076 +
8077 +&cpu {
8078 + cpu0: cpu@0 {
8079 + device_type = "cpu";
8080 + compatible = "arm,cortex-a72";
8081 + reg = <0x0>;
8082 + clocks = <&clockgen 1 0>;
8083 + next-level-cache = <&cluster0_l2>;
8084 + #cooling-cells = <2>;
8085 + cpu-idle-states = <&CPU_PH20>;
8086 + };
8087 +
8088 + cpu1: cpu@1 {
8089 + device_type = "cpu";
8090 + compatible = "arm,cortex-a72";
8091 + reg = <0x1>;
8092 + clocks = <&clockgen 1 0>;
8093 + next-level-cache = <&cluster0_l2>;
8094 + cpu-idle-states = <&CPU_PH20>;
8095 + };
8096 +
8097 + cpu2: cpu@100 {
8098 + device_type = "cpu";
8099 + compatible = "arm,cortex-a72";
8100 + reg = <0x100>;
8101 + clocks = <&clockgen 1 1>;
8102 + next-level-cache = <&cluster1_l2>;
8103 + #cooling-cells = <2>;
8104 + cpu-idle-states = <&CPU_PH20>;
8105 + };
8106 +
8107 + cpu3: cpu@101 {
8108 + device_type = "cpu";
8109 + compatible = "arm,cortex-a72";
8110 + reg = <0x101>;
8111 + clocks = <&clockgen 1 1>;
8112 + next-level-cache = <&cluster1_l2>;
8113 + cpu-idle-states = <&CPU_PH20>;
8114 + };
8115 +
8116 + cpu4: cpu@200 {
8117 + device_type = "cpu";
8118 + compatible = "arm,cortex-a72";
8119 + reg = <0x200>;
8120 + clocks = <&clockgen 1 2>;
8121 + next-level-cache = <&cluster2_l2>;
8122 + #cooling-cells = <2>;
8123 + cpu-idle-states = <&CPU_PH20>;
8124 + };
8125 +
8126 + cpu5: cpu@201 {
8127 + device_type = "cpu";
8128 + compatible = "arm,cortex-a72";
8129 + reg = <0x201>;
8130 + clocks = <&clockgen 1 2>;
8131 + next-level-cache = <&cluster2_l2>;
8132 + cpu-idle-states = <&CPU_PH20>;
8133 + };
8134 +
8135 + cpu6: cpu@300 {
8136 + device_type = "cpu";
8137 + compatible = "arm,cortex-a72";
8138 + reg = <0x300>;
8139 + clocks = <&clockgen 1 3>;
8140 + next-level-cache = <&cluster3_l2>;
8141 + #cooling-cells = <2>;
8142 + cpu-idle-states = <&CPU_PH20>;
8143 + };
8144 +
8145 + cpu7: cpu@301 {
8146 + device_type = "cpu";
8147 + compatible = "arm,cortex-a72";
8148 + reg = <0x301>;
8149 + clocks = <&clockgen 1 3>;
8150 + next-level-cache = <&cluster3_l2>;
8151 + cpu-idle-states = <&CPU_PH20>;
8152 + };
8153 +
8154 + idle-states {
8155 + /*
8156 + * PSCI node is not added default, U-boot will add missing
8157 + * parts if it determines to use PSCI.
8158 + */
8159 + entry-method = "arm,psci";
8160 +
8161 + CPU_PH20: cpu-ph20 {
8162 + compatible = "arm,idle-state";
8163 + idle-state-name = "PH20";
8164 + arm,psci-suspend-param = <0x0>;
8165 + entry-latency-us = <1000>;
8166 + exit-latency-us = <1000>;
8167 + min-residency-us = <3000>;
8168 + };
8169 + };
8170 +
8171 + cluster0_l2: l2-cache0 {
8172 + compatible = "cache";
8173 + };
8174 +
8175 + cluster1_l2: l2-cache1 {
8176 + compatible = "cache";
8177 + };
8178 +
8179 + cluster2_l2: l2-cache2 {
8180 + compatible = "cache";
8181 + };
8182 +
8183 + cluster3_l2: l2-cache3 {
8184 + compatible = "cache";
8185 + };
8186 +};
8187 +
8188 +&pcie1 {
8189 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8190 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
8191 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
8192 +
8193 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
8194 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
8195 +};
8196 +
8197 +&pcie2 {
8198 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8199 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
8200 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
8201 +
8202 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
8203 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
8204 +};
8205 +
8206 +&pcie3 {
8207 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8208 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
8209 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
8210 +
8211 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
8212 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
8213 +};
8214 +
8215 +&pcie4 {
8216 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8217 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
8218 + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
8219 +
8220 + ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
8221 + 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
8222 +};
8223 --- /dev/null
8224 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
8225 @@ -0,0 +1,198 @@
8226 +/*
8227 + * Device Tree file for Freescale LS2080A QDS Board.
8228 + *
8229 + * Copyright 2016 Freescale Semiconductor, Inc.
8230 + * Copyright 2017 NXP
8231 + *
8232 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8233 + *
8234 + * This file is dual-licensed: you can use it either under the terms
8235 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8236 + * licensing only applies to this file, and not this project as a
8237 + * whole.
8238 + *
8239 + * a) This library is free software; you can redistribute it and/or
8240 + * modify it under the terms of the GNU General Public License as
8241 + * published by the Free Software Foundation; either version 2 of the
8242 + * License, or (at your option) any later version.
8243 + *
8244 + * This library is distributed in the hope that it will be useful,
8245 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8246 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8247 + * GNU General Public License for more details.
8248 + *
8249 + * Or, alternatively,
8250 + *
8251 + * b) Permission is hereby granted, free of charge, to any person
8252 + * obtaining a copy of this software and associated documentation
8253 + * files (the "Software"), to deal in the Software without
8254 + * restriction, including without limitation the rights to use,
8255 + * copy, modify, merge, publish, distribute, sublicense, and/or
8256 + * sell copies of the Software, and to permit persons to whom the
8257 + * Software is furnished to do so, subject to the following
8258 + * conditions:
8259 + *
8260 + * The above copyright notice and this permission notice shall be
8261 + * included in all copies or substantial portions of the Software.
8262 + *
8263 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8264 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8265 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8266 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8267 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8268 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8269 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8270 + * OTHER DEALINGS IN THE SOFTWARE.
8271 + */
8272 +
8273 +&esdhc {
8274 + mmc-hs200-1_8v;
8275 + status = "okay";
8276 +};
8277 +
8278 +&ifc {
8279 + status = "okay";
8280 + #address-cells = <2>;
8281 + #size-cells = <1>;
8282 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8283 + 0x2 0x0 0x5 0x30000000 0x00010000
8284 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8285 +
8286 + nor@0,0 {
8287 + #address-cells = <1>;
8288 + #size-cells = <1>;
8289 + compatible = "cfi-flash";
8290 + reg = <0x0 0x0 0x8000000>;
8291 + bank-width = <2>;
8292 + device-width = <1>;
8293 + };
8294 +
8295 + nand@2,0 {
8296 + compatible = "fsl,ifc-nand";
8297 + reg = <0x2 0x0 0x10000>;
8298 + };
8299 +
8300 + cpld@3,0 {
8301 + reg = <0x3 0x0 0x10000>;
8302 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8303 + };
8304 +};
8305 +
8306 +&i2c0 {
8307 + status = "okay";
8308 + pca9547@77 {
8309 + compatible = "nxp,pca9547";
8310 + reg = <0x77>;
8311 + #address-cells = <1>;
8312 + #size-cells = <0>;
8313 + i2c@0 {
8314 + #address-cells = <1>;
8315 + #size-cells = <0>;
8316 + reg = <0x00>;
8317 + rtc@68 {
8318 + compatible = "dallas,ds3232";
8319 + reg = <0x68>;
8320 + };
8321 + };
8322 +
8323 + i2c@2 {
8324 + #address-cells = <1>;
8325 + #size-cells = <0>;
8326 + reg = <0x02>;
8327 +
8328 + ina220@40 {
8329 + compatible = "ti,ina220";
8330 + reg = <0x40>;
8331 + shunt-resistor = <500>;
8332 + };
8333 +
8334 + ina220@41 {
8335 + compatible = "ti,ina220";
8336 + reg = <0x41>;
8337 + shunt-resistor = <1000>;
8338 + };
8339 + };
8340 +
8341 + i2c@3 {
8342 + #address-cells = <1>;
8343 + #size-cells = <0>;
8344 + reg = <0x3>;
8345 +
8346 + adt7481@4c {
8347 + compatible = "adi,adt7461";
8348 + reg = <0x4c>;
8349 + };
8350 + };
8351 + };
8352 +};
8353 +
8354 +&i2c1 {
8355 + status = "disabled";
8356 +};
8357 +
8358 +&i2c2 {
8359 + status = "disabled";
8360 +};
8361 +
8362 +&i2c3 {
8363 + status = "disabled";
8364 +};
8365 +
8366 +&dspi {
8367 + status = "okay";
8368 + dflash0: n25q128a {
8369 + #address-cells = <1>;
8370 + #size-cells = <1>;
8371 + compatible = "st,m25p80";
8372 + spi-max-frequency = <3000000>;
8373 + reg = <0>;
8374 + };
8375 + dflash1: sst25wf040b {
8376 + #address-cells = <1>;
8377 + #size-cells = <1>;
8378 + compatible = "st,m25p80";
8379 + spi-max-frequency = <3000000>;
8380 + reg = <1>;
8381 + };
8382 + dflash2: en25s64 {
8383 + #address-cells = <1>;
8384 + #size-cells = <1>;
8385 + compatible = "st,m25p80";
8386 + spi-max-frequency = <3000000>;
8387 + reg = <2>;
8388 + };
8389 +};
8390 +
8391 +&qspi {
8392 + status = "okay";
8393 + flash0: s25fl256s1@0 {
8394 + #address-cells = <1>;
8395 + #size-cells = <1>;
8396 + compatible = "st,m25p80";
8397 + spi-max-frequency = <20000000>;
8398 + reg = <0>;
8399 + };
8400 + flash2: s25fl256s1@2 {
8401 + #address-cells = <1>;
8402 + #size-cells = <1>;
8403 + compatible = "st,m25p80";
8404 + spi-max-frequency = <20000000>;
8405 + reg = <0>;
8406 + };
8407 +};
8408 +
8409 +&sata0 {
8410 + status = "okay";
8411 +};
8412 +
8413 +&sata1 {
8414 + status = "okay";
8415 +};
8416 +
8417 +&usb0 {
8418 + status = "okay";
8419 +};
8420 +
8421 +&usb1 {
8422 + status = "okay";
8423 +};
8424 --- /dev/null
8425 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
8426 @@ -0,0 +1,161 @@
8427 +/*
8428 + * Device Tree file for Freescale LS2080A RDB Board.
8429 + *
8430 + * Copyright 2016 Freescale Semiconductor, Inc.
8431 + * Copyright 2017 NXP
8432 + *
8433 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8434 + *
8435 + * This file is dual-licensed: you can use it either under the terms
8436 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8437 + * licensing only applies to this file, and not this project as a
8438 + * whole.
8439 + *
8440 + * a) This library is free software; you can redistribute it and/or
8441 + * modify it under the terms of the GNU General Public License as
8442 + * published by the Free Software Foundation; either version 2 of the
8443 + * License, or (at your option) any later version.
8444 + *
8445 + * This library is distributed in the hope that it will be useful,
8446 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8447 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8448 + * GNU General Public License for more details.
8449 + *
8450 + * Or, alternatively,
8451 + *
8452 + * b) Permission is hereby granted, free of charge, to any person
8453 + * obtaining a copy of this software and associated documentation
8454 + * files (the "Software"), to deal in the Software without
8455 + * restriction, including without limitation the rights to use,
8456 + * copy, modify, merge, publish, distribute, sublicense, and/or
8457 + * sell copies of the Software, and to permit persons to whom the
8458 + * Software is furnished to do so, subject to the following
8459 + * conditions:
8460 + *
8461 + * The above copyright notice and this permission notice shall be
8462 + * included in all copies or substantial portions of the Software.
8463 + *
8464 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8465 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8466 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8467 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8468 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8469 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8470 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8471 + * OTHER DEALINGS IN THE SOFTWARE.
8472 + */
8473 +
8474 +&esdhc {
8475 + status = "okay";
8476 +};
8477 +
8478 +&ifc {
8479 + status = "okay";
8480 + #address-cells = <2>;
8481 + #size-cells = <1>;
8482 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8483 + 0x2 0x0 0x5 0x30000000 0x00010000
8484 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8485 +
8486 + nor@0,0 {
8487 + #address-cells = <1>;
8488 + #size-cells = <1>;
8489 + compatible = "cfi-flash";
8490 + reg = <0x0 0x0 0x8000000>;
8491 + bank-width = <2>;
8492 + device-width = <1>;
8493 + };
8494 +
8495 + nand@2,0 {
8496 + compatible = "fsl,ifc-nand";
8497 + reg = <0x2 0x0 0x10000>;
8498 + };
8499 +
8500 + cpld@3,0 {
8501 + reg = <0x3 0x0 0x10000>;
8502 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8503 + };
8504 +
8505 +};
8506 +
8507 +&i2c0 {
8508 + status = "okay";
8509 + pca9547@75 {
8510 + compatible = "nxp,pca9547";
8511 + reg = <0x75>;
8512 + #address-cells = <1>;
8513 + #size-cells = <0>;
8514 + i2c-mux-never-disable;
8515 + i2c@1 {
8516 + #address-cells = <1>;
8517 + #size-cells = <0>;
8518 + reg = <0x01>;
8519 + rtc@68 {
8520 + compatible = "dallas,ds3232";
8521 + reg = <0x68>;
8522 + };
8523 + };
8524 +
8525 + i2c@3 {
8526 + #address-cells = <1>;
8527 + #size-cells = <0>;
8528 + reg = <0x3>;
8529 +
8530 + adt7481@4c {
8531 + compatible = "adi,adt7461";
8532 + reg = <0x4c>;
8533 + };
8534 + };
8535 + };
8536 +};
8537 +
8538 +&i2c1 {
8539 + status = "disabled";
8540 +};
8541 +
8542 +&i2c2 {
8543 + status = "disabled";
8544 +};
8545 +
8546 +&i2c3 {
8547 + status = "disabled";
8548 +};
8549 +
8550 +&dspi {
8551 + status = "okay";
8552 + dflash0: n25q512a {
8553 + #address-cells = <1>;
8554 + #size-cells = <1>;
8555 + compatible = "st,m25p80";
8556 + spi-max-frequency = <3000000>;
8557 + reg = <0>;
8558 + };
8559 +};
8560 +
8561 +&qspi {
8562 + status = "okay";
8563 + flash0: s25fs512s@0 {
8564 + #address-cells = <1>;
8565 + #size-cells = <1>;
8566 + compatible = "spansion,m25p80";
8567 + m25p,fast-read;
8568 + spi-max-frequency = <20000000>;
8569 + reg = <0>;
8570 + };
8571 +};
8572 +
8573 +&sata0 {
8574 + status = "okay";
8575 +};
8576 +
8577 +&sata1 {
8578 + status = "okay";
8579 +};
8580 +
8581 +&usb0 {
8582 + status = "okay";
8583 +};
8584 +
8585 +&usb1 {
8586 + status = "okay";
8587 +};
8588 --- /dev/null
8589 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
8590 @@ -0,0 +1,919 @@
8591 +/*
8592 + * Device Tree Include file for Freescale Layerscape-2080A family SoC.
8593 + *
8594 + * Copyright 2016 Freescale Semiconductor, Inc.
8595 + * Copyright 2017 NXP
8596 + *
8597 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8598 + *
8599 + * This file is dual-licensed: you can use it either under the terms
8600 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8601 + * licensing only applies to this file, and not this project as a
8602 + * whole.
8603 + *
8604 + * a) This library is free software; you can redistribute it and/or
8605 + * modify it under the terms of the GNU General Public License as
8606 + * published by the Free Software Foundation; either version 2 of the
8607 + * License, or (at your option) any later version.
8608 + *
8609 + * This library is distributed in the hope that it will be useful,
8610 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8611 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8612 + * GNU General Public License for more details.
8613 + *
8614 + * Or, alternatively,
8615 + *
8616 + * b) Permission is hereby granted, free of charge, to any person
8617 + * obtaining a copy of this software and associated documentation
8618 + * files (the "Software"), to deal in the Software without
8619 + * restriction, including without limitation the rights to use,
8620 + * copy, modify, merge, publish, distribute, sublicense, and/or
8621 + * sell copies of the Software, and to permit persons to whom the
8622 + * Software is furnished to do so, subject to the following
8623 + * conditions:
8624 + *
8625 + * The above copyright notice and this permission notice shall be
8626 + * included in all copies or substantial portions of the Software.
8627 + *
8628 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8629 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8630 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8631 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8632 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8633 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8634 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8635 + * OTHER DEALINGS IN THE SOFTWARE.
8636 + */
8637 +
8638 +#include <dt-bindings/thermal/thermal.h>
8639 +#include <dt-bindings/interrupt-controller/arm-gic.h>
8640 +
8641 +/ {
8642 + compatible = "fsl,ls2080a";
8643 + interrupt-parent = <&gic>;
8644 + #address-cells = <2>;
8645 + #size-cells = <2>;
8646 +
8647 + aliases {
8648 + crypto = &crypto;
8649 + serial0 = &serial0;
8650 + serial1 = &serial1;
8651 + };
8652 +
8653 + cpu: cpus {
8654 + #address-cells = <1>;
8655 + #size-cells = <0>;
8656 + };
8657 +
8658 + memory@80000000 {
8659 + device_type = "memory";
8660 + reg = <0x00000000 0x80000000 0 0x80000000>;
8661 + /* DRAM space - 1, size : 2 GB DRAM */
8662 + };
8663 +
8664 + sysclk: sysclk {
8665 + compatible = "fixed-clock";
8666 + #clock-cells = <0>;
8667 + clock-frequency = <100000000>;
8668 + clock-output-names = "sysclk";
8669 + };
8670 +
8671 + gic: interrupt-controller@6000000 {
8672 + compatible = "arm,gic-v3";
8673 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
8674 + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
8675 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
8676 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
8677 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
8678 + #interrupt-cells = <3>;
8679 + #address-cells = <2>;
8680 + #size-cells = <2>;
8681 + ranges;
8682 + interrupt-controller;
8683 + interrupts = <1 9 0x4>;
8684 +
8685 + its: gic-its@6020000 {
8686 + compatible = "arm,gic-v3-its";
8687 + msi-controller;
8688 + reg = <0x0 0x6020000 0 0x20000>;
8689 + };
8690 + };
8691 +
8692 + rstcr: syscon@1e60000 {
8693 + compatible = "fsl,ls2080a-rstcr", "syscon";
8694 + reg = <0x0 0x1e60000 0x0 0x4>;
8695 + };
8696 +
8697 + reboot {
8698 + compatible ="syscon-reboot";
8699 + regmap = <&rstcr>;
8700 + offset = <0x0>;
8701 + mask = <0x2>;
8702 + };
8703 +
8704 + timer {
8705 + compatible = "arm,armv8-timer";
8706 + interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
8707 + <1 14 4>, /* Physical Non-Secure PPI, active-low */
8708 + <1 11 4>, /* Virtual PPI, active-low */
8709 + <1 10 4>; /* Hypervisor PPI, active-low */
8710 + fsl,erratum-a008585;
8711 + };
8712 +
8713 + pmu {
8714 + compatible = "arm,armv8-pmuv3";
8715 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
8716 + };
8717 +
8718 + soc {
8719 + compatible = "simple-bus";
8720 + #address-cells = <2>;
8721 + #size-cells = <2>;
8722 + ranges;
8723 +
8724 + clockgen: clocking@1300000 {
8725 + compatible = "fsl,ls2080a-clockgen";
8726 + reg = <0 0x1300000 0 0xa0000>;
8727 + #clock-cells = <2>;
8728 + clocks = <&sysclk>;
8729 + };
8730 +
8731 + dcfg: dcfg@1e00000 {
8732 + compatible = "fsl,ls2080a-dcfg", "syscon";
8733 + reg = <0x0 0x1e00000 0x0 0x10000>;
8734 + little-endian;
8735 + };
8736 +
8737 + tmu: tmu@1f80000 {
8738 + compatible = "fsl,qoriq-tmu";
8739 + reg = <0x0 0x1f80000 0x0 0x10000>;
8740 + interrupts = <0 23 0x4>;
8741 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
8742 + fsl,tmu-calibration = <0x00000000 0x00000026
8743 + 0x00000001 0x0000002d
8744 + 0x00000002 0x00000032
8745 + 0x00000003 0x00000039
8746 + 0x00000004 0x0000003f
8747 + 0x00000005 0x00000046
8748 + 0x00000006 0x0000004d
8749 + 0x00000007 0x00000054
8750 + 0x00000008 0x0000005a
8751 + 0x00000009 0x00000061
8752 + 0x0000000a 0x0000006a
8753 + 0x0000000b 0x00000071
8754 +
8755 + 0x00010000 0x00000025
8756 + 0x00010001 0x0000002c
8757 + 0x00010002 0x00000035
8758 + 0x00010003 0x0000003d
8759 + 0x00010004 0x00000045
8760 + 0x00010005 0x0000004e
8761 + 0x00010006 0x00000057
8762 + 0x00010007 0x00000061
8763 + 0x00010008 0x0000006b
8764 + 0x00010009 0x00000076
8765 +
8766 + 0x00020000 0x00000029
8767 + 0x00020001 0x00000033
8768 + 0x00020002 0x0000003d
8769 + 0x00020003 0x00000049
8770 + 0x00020004 0x00000056
8771 + 0x00020005 0x00000061
8772 + 0x00020006 0x0000006d
8773 +
8774 + 0x00030000 0x00000021
8775 + 0x00030001 0x0000002a
8776 + 0x00030002 0x0000003c
8777 + 0x00030003 0x0000004e>;
8778 + little-endian;
8779 + #thermal-sensor-cells = <1>;
8780 + };
8781 +
8782 + thermal-zones {
8783 + cpu_thermal: cpu-thermal {
8784 + polling-delay-passive = <1000>;
8785 + polling-delay = <5000>;
8786 +
8787 + thermal-sensors = <&tmu 4>;
8788 +
8789 + trips {
8790 + cpu_alert: cpu-alert {
8791 + temperature = <75000>;
8792 + hysteresis = <2000>;
8793 + type = "passive";
8794 + };
8795 + cpu_crit: cpu-crit {
8796 + temperature = <85000>;
8797 + hysteresis = <2000>;
8798 + type = "critical";
8799 + };
8800 + };
8801 +
8802 + cooling-maps {
8803 + map0 {
8804 + trip = <&cpu_alert>;
8805 + cooling-device =
8806 + <&cpu0 THERMAL_NO_LIMIT
8807 + THERMAL_NO_LIMIT>;
8808 + };
8809 + map1 {
8810 + trip = <&cpu_alert>;
8811 + cooling-device =
8812 + <&cpu2 THERMAL_NO_LIMIT
8813 + THERMAL_NO_LIMIT>;
8814 + };
8815 + map2 {
8816 + trip = <&cpu_alert>;
8817 + cooling-device =
8818 + <&cpu4 THERMAL_NO_LIMIT
8819 + THERMAL_NO_LIMIT>;
8820 + };
8821 + map3 {
8822 + trip = <&cpu_alert>;
8823 + cooling-device =
8824 + <&cpu6 THERMAL_NO_LIMIT
8825 + THERMAL_NO_LIMIT>;
8826 + };
8827 + };
8828 + };
8829 + };
8830 +
8831 + serial0: serial@21c0500 {
8832 + compatible = "fsl,ns16550", "ns16550a";
8833 + reg = <0x0 0x21c0500 0x0 0x100>;
8834 + clocks = <&clockgen 4 3>;
8835 + interrupts = <0 32 0x4>; /* Level high type */
8836 + };
8837 +
8838 + serial1: serial@21c0600 {
8839 + compatible = "fsl,ns16550", "ns16550a";
8840 + reg = <0x0 0x21c0600 0x0 0x100>;
8841 + clocks = <&clockgen 4 3>;
8842 + interrupts = <0 32 0x4>; /* Level high type */
8843 + };
8844 +
8845 + cluster1_core0_watchdog: wdt@c000000 {
8846 + compatible = "arm,sp805-wdt", "arm,primecell";
8847 + reg = <0x0 0xc000000 0x0 0x1000>;
8848 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8849 + clock-names = "apb_pclk", "wdog_clk";
8850 + };
8851 +
8852 + cluster1_core1_watchdog: wdt@c010000 {
8853 + compatible = "arm,sp805-wdt", "arm,primecell";
8854 + reg = <0x0 0xc010000 0x0 0x1000>;
8855 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8856 + clock-names = "apb_pclk", "wdog_clk";
8857 + };
8858 +
8859 + cluster2_core0_watchdog: wdt@c100000 {
8860 + compatible = "arm,sp805-wdt", "arm,primecell";
8861 + reg = <0x0 0xc100000 0x0 0x1000>;
8862 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8863 + clock-names = "apb_pclk", "wdog_clk";
8864 + };
8865 +
8866 + cluster2_core1_watchdog: wdt@c110000 {
8867 + compatible = "arm,sp805-wdt", "arm,primecell";
8868 + reg = <0x0 0xc110000 0x0 0x1000>;
8869 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8870 + clock-names = "apb_pclk", "wdog_clk";
8871 + };
8872 +
8873 + cluster3_core0_watchdog: wdt@c200000 {
8874 + compatible = "arm,sp805-wdt", "arm,primecell";
8875 + reg = <0x0 0xc200000 0x0 0x1000>;
8876 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8877 + clock-names = "apb_pclk", "wdog_clk";
8878 + };
8879 +
8880 + cluster3_core1_watchdog: wdt@c210000 {
8881 + compatible = "arm,sp805-wdt", "arm,primecell";
8882 + reg = <0x0 0xc210000 0x0 0x1000>;
8883 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8884 + clock-names = "apb_pclk", "wdog_clk";
8885 + };
8886 +
8887 + cluster4_core0_watchdog: wdt@c300000 {
8888 + compatible = "arm,sp805-wdt", "arm,primecell";
8889 + reg = <0x0 0xc300000 0x0 0x1000>;
8890 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8891 + clock-names = "apb_pclk", "wdog_clk";
8892 + };
8893 +
8894 + cluster4_core1_watchdog: wdt@c310000 {
8895 + compatible = "arm,sp805-wdt", "arm,primecell";
8896 + reg = <0x0 0xc310000 0x0 0x1000>;
8897 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8898 + clock-names = "apb_pclk", "wdog_clk";
8899 + };
8900 +
8901 + crypto: crypto@8000000 {
8902 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
8903 + fsl,sec-era = <8>;
8904 + #address-cells = <1>;
8905 + #size-cells = <1>;
8906 + ranges = <0x0 0x00 0x8000000 0x100000>;
8907 + reg = <0x00 0x8000000 0x0 0x100000>;
8908 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
8909 + dma-coherent;
8910 +
8911 + sec_jr0: jr@10000 {
8912 + compatible = "fsl,sec-v5.0-job-ring",
8913 + "fsl,sec-v4.0-job-ring";
8914 + reg = <0x10000 0x10000>;
8915 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
8916 + };
8917 +
8918 + sec_jr1: jr@20000 {
8919 + compatible = "fsl,sec-v5.0-job-ring",
8920 + "fsl,sec-v4.0-job-ring";
8921 + reg = <0x20000 0x10000>;
8922 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
8923 + };
8924 +
8925 + sec_jr2: jr@30000 {
8926 + compatible = "fsl,sec-v5.0-job-ring",
8927 + "fsl,sec-v4.0-job-ring";
8928 + reg = <0x30000 0x10000>;
8929 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
8930 + };
8931 +
8932 + sec_jr3: jr@40000 {
8933 + compatible = "fsl,sec-v5.0-job-ring",
8934 + "fsl,sec-v4.0-job-ring";
8935 + reg = <0x40000 0x10000>;
8936 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
8937 + };
8938 + };
8939 +
8940 + fsl_mc: fsl-mc@80c000000 {
8941 + compatible = "fsl,qoriq-mc";
8942 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
8943 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
8944 + msi-parent = <&its>;
8945 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
8946 + #address-cells = <3>;
8947 + #size-cells = <1>;
8948 +
8949 + /*
8950 + * Region type 0x0 - MC portals
8951 + * Region type 0x1 - QBMAN portals
8952 + */
8953 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
8954 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
8955 +
8956 + /*
8957 + * Define the maximum number of MACs present on the SoC.
8958 + */
8959 + dpmacs {
8960 + #address-cells = <1>;
8961 + #size-cells = <0>;
8962 +
8963 + dpmac1: dpmac@1 {
8964 + compatible = "fsl,qoriq-mc-dpmac";
8965 + reg = <0x1>;
8966 + };
8967 +
8968 + dpmac2: dpmac@2 {
8969 + compatible = "fsl,qoriq-mc-dpmac";
8970 + reg = <0x2>;
8971 + };
8972 +
8973 + dpmac3: dpmac@3 {
8974 + compatible = "fsl,qoriq-mc-dpmac";
8975 + reg = <0x3>;
8976 + };
8977 +
8978 + dpmac4: dpmac@4 {
8979 + compatible = "fsl,qoriq-mc-dpmac";
8980 + reg = <0x4>;
8981 + };
8982 +
8983 + dpmac5: dpmac@5 {
8984 + compatible = "fsl,qoriq-mc-dpmac";
8985 + reg = <0x5>;
8986 + };
8987 +
8988 + dpmac6: dpmac@6 {
8989 + compatible = "fsl,qoriq-mc-dpmac";
8990 + reg = <0x6>;
8991 + };
8992 +
8993 + dpmac7: dpmac@7 {
8994 + compatible = "fsl,qoriq-mc-dpmac";
8995 + reg = <0x7>;
8996 + };
8997 +
8998 + dpmac8: dpmac@8 {
8999 + compatible = "fsl,qoriq-mc-dpmac";
9000 + reg = <0x8>;
9001 + };
9002 +
9003 + dpmac9: dpmac@9 {
9004 + compatible = "fsl,qoriq-mc-dpmac";
9005 + reg = <0x9>;
9006 + };
9007 +
9008 + dpmac10: dpmac@a {
9009 + compatible = "fsl,qoriq-mc-dpmac";
9010 + reg = <0xa>;
9011 + };
9012 +
9013 + dpmac11: dpmac@b {
9014 + compatible = "fsl,qoriq-mc-dpmac";
9015 + reg = <0xb>;
9016 + };
9017 +
9018 + dpmac12: dpmac@c {
9019 + compatible = "fsl,qoriq-mc-dpmac";
9020 + reg = <0xc>;
9021 + };
9022 +
9023 + dpmac13: dpmac@d {
9024 + compatible = "fsl,qoriq-mc-dpmac";
9025 + reg = <0xd>;
9026 + };
9027 +
9028 + dpmac14: dpmac@e {
9029 + compatible = "fsl,qoriq-mc-dpmac";
9030 + reg = <0xe>;
9031 + };
9032 +
9033 + dpmac15: dpmac@f {
9034 + compatible = "fsl,qoriq-mc-dpmac";
9035 + reg = <0xf>;
9036 + };
9037 +
9038 + dpmac16: dpmac@10 {
9039 + compatible = "fsl,qoriq-mc-dpmac";
9040 + reg = <0x10>;
9041 + };
9042 + };
9043 + };
9044 +
9045 + smmu: iommu@5000000 {
9046 + compatible = "arm,mmu-500";
9047 + reg = <0 0x5000000 0 0x800000>;
9048 + #global-interrupts = <12>;
9049 + #iommu-cells = <1>;
9050 + stream-match-mask = <0x7C00>;
9051 + interrupts = <0 13 4>, /* global secure fault */
9052 + <0 14 4>, /* combined secure interrupt */
9053 + <0 15 4>, /* global non-secure fault */
9054 + <0 16 4>, /* combined non-secure interrupt */
9055 + /* performance counter interrupts 0-7 */
9056 + <0 211 4>, <0 212 4>,
9057 + <0 213 4>, <0 214 4>,
9058 + <0 215 4>, <0 216 4>,
9059 + <0 217 4>, <0 218 4>,
9060 + /* per context interrupt, 64 interrupts */
9061 + <0 146 4>, <0 147 4>,
9062 + <0 148 4>, <0 149 4>,
9063 + <0 150 4>, <0 151 4>,
9064 + <0 152 4>, <0 153 4>,
9065 + <0 154 4>, <0 155 4>,
9066 + <0 156 4>, <0 157 4>,
9067 + <0 158 4>, <0 159 4>,
9068 + <0 160 4>, <0 161 4>,
9069 + <0 162 4>, <0 163 4>,
9070 + <0 164 4>, <0 165 4>,
9071 + <0 166 4>, <0 167 4>,
9072 + <0 168 4>, <0 169 4>,
9073 + <0 170 4>, <0 171 4>,
9074 + <0 172 4>, <0 173 4>,
9075 + <0 174 4>, <0 175 4>,
9076 + <0 176 4>, <0 177 4>,
9077 + <0 178 4>, <0 179 4>,
9078 + <0 180 4>, <0 181 4>,
9079 + <0 182 4>, <0 183 4>,
9080 + <0 184 4>, <0 185 4>,
9081 + <0 186 4>, <0 187 4>,
9082 + <0 188 4>, <0 189 4>,
9083 + <0 190 4>, <0 191 4>,
9084 + <0 192 4>, <0 193 4>,
9085 + <0 194 4>, <0 195 4>,
9086 + <0 196 4>, <0 197 4>,
9087 + <0 198 4>, <0 199 4>,
9088 + <0 200 4>, <0 201 4>,
9089 + <0 202 4>, <0 203 4>,
9090 + <0 204 4>, <0 205 4>,
9091 + <0 206 4>, <0 207 4>,
9092 + <0 208 4>, <0 209 4>;
9093 + };
9094 +
9095 + dspi: dspi@2100000 {
9096 + status = "disabled";
9097 + compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
9098 + #address-cells = <1>;
9099 + #size-cells = <0>;
9100 + reg = <0x0 0x2100000 0x0 0x10000>;
9101 + interrupts = <0 26 0x4>; /* Level high type */
9102 + clocks = <&clockgen 4 3>;
9103 + clock-names = "dspi";
9104 + spi-num-chipselects = <5>;
9105 + bus-num = <0>;
9106 + };
9107 +
9108 + esdhc: esdhc@2140000 {
9109 + status = "disabled";
9110 + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
9111 + reg = <0x0 0x2140000 0x0 0x10000>;
9112 + interrupts = <0 28 0x4>; /* Level high type */
9113 + clocks = <&clockgen 4 1>;
9114 + voltage-ranges = <1800 1800 3300 3300>;
9115 + sdhci,auto-cmd12;
9116 + little-endian;
9117 + bus-width = <4>;
9118 + };
9119 +
9120 + gpio0: gpio@2300000 {
9121 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9122 + reg = <0x0 0x2300000 0x0 0x10000>;
9123 + interrupts = <0 36 0x4>; /* Level high type */
9124 + gpio-controller;
9125 + little-endian;
9126 + #gpio-cells = <2>;
9127 + interrupt-controller;
9128 + #interrupt-cells = <2>;
9129 + };
9130 +
9131 + gpio1: gpio@2310000 {
9132 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9133 + reg = <0x0 0x2310000 0x0 0x10000>;
9134 + interrupts = <0 36 0x4>; /* Level high type */
9135 + gpio-controller;
9136 + little-endian;
9137 + #gpio-cells = <2>;
9138 + interrupt-controller;
9139 + #interrupt-cells = <2>;
9140 + };
9141 +
9142 + gpio2: gpio@2320000 {
9143 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9144 + reg = <0x0 0x2320000 0x0 0x10000>;
9145 + interrupts = <0 37 0x4>; /* Level high type */
9146 + gpio-controller;
9147 + little-endian;
9148 + #gpio-cells = <2>;
9149 + interrupt-controller;
9150 + #interrupt-cells = <2>;
9151 + };
9152 +
9153 + gpio3: gpio@2330000 {
9154 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9155 + reg = <0x0 0x2330000 0x0 0x10000>;
9156 + interrupts = <0 37 0x4>; /* Level high type */
9157 + gpio-controller;
9158 + little-endian;
9159 + #gpio-cells = <2>;
9160 + interrupt-controller;
9161 + #interrupt-cells = <2>;
9162 + };
9163 +
9164 + /* TODO: WRIOP (CCSR?) */
9165 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
9166 + * E-MDIO1: 0x1_6000
9167 + */
9168 + compatible = "fsl,fman-memac-mdio";
9169 + reg = <0x0 0x8B96000 0x0 0x1000>;
9170 + device_type = "mdio"; /* TODO: is this necessary? */
9171 + little-endian; /* force the driver in LE mode */
9172 +
9173 + /* Not necessary on the QDS, but needed on the RDB */
9174 + #address-cells = <1>;
9175 + #size-cells = <0>;
9176 + };
9177 +
9178 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
9179 + * E-MDIO2: 0x1_7000
9180 + */
9181 + compatible = "fsl,fman-memac-mdio";
9182 + reg = <0x0 0x8B97000 0x0 0x1000>;
9183 + device_type = "mdio"; /* TODO: is this necessary? */
9184 + little-endian; /* force the driver in LE mode */
9185 +
9186 + #address-cells = <1>;
9187 + #size-cells = <0>;
9188 + };
9189 +
9190 + pcs_mdio1: mdio@0x8c07000 {
9191 + compatible = "fsl,fman-memac-mdio";
9192 + reg = <0x0 0x8c07000 0x0 0x1000>;
9193 + device_type = "mdio";
9194 + little-endian;
9195 +
9196 + #address-cells = <1>;
9197 + #size-cells = <0>;
9198 + };
9199 +
9200 + pcs_mdio2: mdio@0x8c0b000 {
9201 + compatible = "fsl,fman-memac-mdio";
9202 + reg = <0x0 0x8c0b000 0x0 0x1000>;
9203 + device_type = "mdio";
9204 + little-endian;
9205 +
9206 + #address-cells = <1>;
9207 + #size-cells = <0>;
9208 + };
9209 +
9210 + pcs_mdio3: mdio@0x8c0f000 {
9211 + compatible = "fsl,fman-memac-mdio";
9212 + reg = <0x0 0x8c0f000 0x0 0x1000>;
9213 + device_type = "mdio";
9214 + little-endian;
9215 +
9216 + #address-cells = <1>;
9217 + #size-cells = <0>;
9218 + };
9219 +
9220 + pcs_mdio4: mdio@0x8c13000 {
9221 + compatible = "fsl,fman-memac-mdio";
9222 + reg = <0x0 0x8c13000 0x0 0x1000>;
9223 + device_type = "mdio";
9224 + little-endian;
9225 +
9226 + #address-cells = <1>;
9227 + #size-cells = <0>;
9228 + };
9229 +
9230 + pcs_mdio5: mdio@0x8c17000 {
9231 + status = "disabled";
9232 + compatible = "fsl,fman-memac-mdio";
9233 + reg = <0x0 0x8c17000 0x0 0x1000>;
9234 + device_type = "mdio";
9235 + little-endian;
9236 +
9237 + #address-cells = <1>;
9238 + #size-cells = <0>;
9239 + };
9240 +
9241 + pcs_mdio6: mdio@0x8c1b000 {
9242 + status = "disabled";
9243 + compatible = "fsl,fman-memac-mdio";
9244 + reg = <0x0 0x8c1b000 0x0 0x1000>;
9245 + device_type = "mdio";
9246 + little-endian;
9247 +
9248 + #address-cells = <1>;
9249 + #size-cells = <0>;
9250 + };
9251 +
9252 + pcs_mdio7: mdio@0x8c1f000 {
9253 + status = "disabled";
9254 + compatible = "fsl,fman-memac-mdio";
9255 + reg = <0x0 0x8c1f000 0x0 0x1000>;
9256 + device_type = "mdio";
9257 + little-endian;
9258 +
9259 + #address-cells = <1>;
9260 + #size-cells = <0>;
9261 + };
9262 +
9263 + pcs_mdio8: mdio@0x8c23000 {
9264 + status = "disabled";
9265 + compatible = "fsl,fman-memac-mdio";
9266 + reg = <0x0 0x8c23000 0x0 0x1000>;
9267 + device_type = "mdio";
9268 + little-endian;
9269 +
9270 + #address-cells = <1>;
9271 + #size-cells = <0>;
9272 + };
9273 +
9274 + i2c0: i2c@2000000 {
9275 + status = "disabled";
9276 + compatible = "fsl,vf610-i2c";
9277 + #address-cells = <1>;
9278 + #size-cells = <0>;
9279 + reg = <0x0 0x2000000 0x0 0x10000>;
9280 + interrupts = <0 34 0x4>; /* Level high type */
9281 + clock-names = "i2c";
9282 + clocks = <&clockgen 4 1>;
9283 + };
9284 +
9285 + i2c1: i2c@2010000 {
9286 + status = "disabled";
9287 + compatible = "fsl,vf610-i2c";
9288 + #address-cells = <1>;
9289 + #size-cells = <0>;
9290 + reg = <0x0 0x2010000 0x0 0x10000>;
9291 + interrupts = <0 34 0x4>; /* Level high type */
9292 + clock-names = "i2c";
9293 + clocks = <&clockgen 4 1>;
9294 + };
9295 +
9296 + i2c2: i2c@2020000 {
9297 + status = "disabled";
9298 + compatible = "fsl,vf610-i2c";
9299 + #address-cells = <1>;
9300 + #size-cells = <0>;
9301 + reg = <0x0 0x2020000 0x0 0x10000>;
9302 + interrupts = <0 35 0x4>; /* Level high type */
9303 + clock-names = "i2c";
9304 + clocks = <&clockgen 4 1>;
9305 + };
9306 +
9307 + i2c3: i2c@2030000 {
9308 + status = "disabled";
9309 + compatible = "fsl,vf610-i2c";
9310 + #address-cells = <1>;
9311 + #size-cells = <0>;
9312 + reg = <0x0 0x2030000 0x0 0x10000>;
9313 + interrupts = <0 35 0x4>; /* Level high type */
9314 + clock-names = "i2c";
9315 + clocks = <&clockgen 4 1>;
9316 + };
9317 +
9318 + ifc: ifc@2240000 {
9319 + compatible = "fsl,ifc", "simple-bus";
9320 + reg = <0x0 0x2240000 0x0 0x20000>;
9321 + interrupts = <0 21 0x4>; /* Level high type */
9322 + little-endian;
9323 + #address-cells = <2>;
9324 + #size-cells = <1>;
9325 +
9326 + ranges = <0 0 0x5 0x80000000 0x08000000
9327 + 2 0 0x5 0x30000000 0x00010000
9328 + 3 0 0x5 0x20000000 0x00010000>;
9329 + };
9330 +
9331 + qspi: quadspi@20c0000 {
9332 + status = "disabled";
9333 + compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
9334 + #address-cells = <1>;
9335 + #size-cells = <0>;
9336 + reg = <0x0 0x20c0000 0x0 0x10000>,
9337 + <0x0 0x20000000 0x0 0x10000000>;
9338 + reg-names = "QuadSPI", "QuadSPI-memory";
9339 + interrupts = <0 25 0x4>; /* Level high type */
9340 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
9341 + clock-names = "qspi_en", "qspi";
9342 + };
9343 +
9344 + pcie1: pcie@3400000 {
9345 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9346 + "snps,dw-pcie";
9347 + reg-names = "regs", "config";
9348 + interrupts = <0 108 0x4>; /* aer interrupt */
9349 + interrupt-names = "aer";
9350 + #address-cells = <3>;
9351 + #size-cells = <2>;
9352 + device_type = "pci";
9353 + dma-coherent;
9354 + num-lanes = <4>;
9355 + bus-range = <0x0 0xff>;
9356 + msi-parent = <&its>;
9357 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9358 + #interrupt-cells = <1>;
9359 + interrupt-map-mask = <0 0 0 7>;
9360 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
9361 + <0000 0 0 2 &gic 0 0 0 110 4>,
9362 + <0000 0 0 3 &gic 0 0 0 111 4>,
9363 + <0000 0 0 4 &gic 0 0 0 112 4>;
9364 + };
9365 +
9366 + pcie2: pcie@3500000 {
9367 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9368 + "snps,dw-pcie";
9369 + reg-names = "regs", "config";
9370 + interrupts = <0 113 0x4>; /* aer interrupt */
9371 + interrupt-names = "aer";
9372 + #address-cells = <3>;
9373 + #size-cells = <2>;
9374 + device_type = "pci";
9375 + dma-coherent;
9376 + num-lanes = <4>;
9377 + bus-range = <0x0 0xff>;
9378 + msi-parent = <&its>;
9379 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9380 + #interrupt-cells = <1>;
9381 + interrupt-map-mask = <0 0 0 7>;
9382 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
9383 + <0000 0 0 2 &gic 0 0 0 115 4>,
9384 + <0000 0 0 3 &gic 0 0 0 116 4>,
9385 + <0000 0 0 4 &gic 0 0 0 117 4>;
9386 + };
9387 +
9388 + pcie3: pcie@3600000 {
9389 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9390 + "snps,dw-pcie";
9391 + reg-names = "regs", "config";
9392 + interrupts = <0 118 0x4>; /* aer interrupt */
9393 + interrupt-names = "aer";
9394 + #address-cells = <3>;
9395 + #size-cells = <2>;
9396 + device_type = "pci";
9397 + dma-coherent;
9398 + num-lanes = <8>;
9399 + bus-range = <0x0 0xff>;
9400 + msi-parent = <&its>;
9401 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9402 + #interrupt-cells = <1>;
9403 + interrupt-map-mask = <0 0 0 7>;
9404 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
9405 + <0000 0 0 2 &gic 0 0 0 120 4>,
9406 + <0000 0 0 3 &gic 0 0 0 121 4>,
9407 + <0000 0 0 4 &gic 0 0 0 122 4>;
9408 + };
9409 +
9410 + pcie4: pcie@3700000 {
9411 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9412 + "snps,dw-pcie";
9413 + reg-names = "regs", "config";
9414 + interrupts = <0 123 0x4>; /* aer interrupt */
9415 + interrupt-names = "aer";
9416 + #address-cells = <3>;
9417 + #size-cells = <2>;
9418 + device_type = "pci";
9419 + dma-coherent;
9420 + num-lanes = <4>;
9421 + bus-range = <0x0 0xff>;
9422 + msi-parent = <&its>;
9423 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9424 + #interrupt-cells = <1>;
9425 + interrupt-map-mask = <0 0 0 7>;
9426 + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
9427 + <0000 0 0 2 &gic 0 0 0 125 4>,
9428 + <0000 0 0 3 &gic 0 0 0 126 4>,
9429 + <0000 0 0 4 &gic 0 0 0 127 4>;
9430 + };
9431 +
9432 + sata0: sata@3200000 {
9433 + status = "disabled";
9434 + compatible = "fsl,ls2080a-ahci";
9435 + reg = <0x0 0x3200000 0x0 0x10000>;
9436 + interrupts = <0 133 0x4>; /* Level high type */
9437 + clocks = <&clockgen 4 3>;
9438 + dma-coherent;
9439 + };
9440 +
9441 + sata1: sata@3210000 {
9442 + status = "disabled";
9443 + compatible = "fsl,ls2080a-ahci";
9444 + reg = <0x0 0x3210000 0x0 0x10000>;
9445 + interrupts = <0 136 0x4>; /* Level high type */
9446 + clocks = <&clockgen 4 3>;
9447 + dma-coherent;
9448 + };
9449 +
9450 + usb0: usb3@3100000 {
9451 + status = "disabled";
9452 + compatible = "snps,dwc3";
9453 + reg = <0x0 0x3100000 0x0 0x10000>;
9454 + interrupts = <0 80 0x4>; /* Level high type */
9455 + dr_mode = "host";
9456 + snps,quirk-frame-length-adjustment = <0x20>;
9457 + snps,dis_rxdet_inp3_quirk;
9458 + };
9459 +
9460 + usb1: usb3@3110000 {
9461 + status = "disabled";
9462 + compatible = "snps,dwc3";
9463 + reg = <0x0 0x3110000 0x0 0x10000>;
9464 + interrupts = <0 81 0x4>; /* Level high type */
9465 + dr_mode = "host";
9466 + snps,quirk-frame-length-adjustment = <0x20>;
9467 + snps,dis_rxdet_inp3_quirk;
9468 + };
9469 +
9470 + serdes1: serdes@1ea0000 {
9471 + reg = <0x0 0x1ea0000 0 0x00002000>;
9472 + };
9473 +
9474 + ccn@4000000 {
9475 + compatible = "arm,ccn-504";
9476 + reg = <0x0 0x04000000 0x0 0x01000000>;
9477 + interrupts = <0 12 4>;
9478 + };
9479 +
9480 + ftm0: ftm0@2800000 {
9481 + compatible = "fsl,ls208xa-ftm";
9482 + reg = <0x0 0x2800000 0x0 0x10000>,
9483 + <0x0 0x1e34050 0x0 0x4>;
9484 + interrupts = <0 44 4>;
9485 + reg-names = "ftm", "FlexTimer1";
9486 + };
9487 + };
9488 +
9489 + ddr1: memory-controller@1080000 {
9490 + compatible = "fsl,qoriq-memory-controller";
9491 + reg = <0x0 0x1080000 0x0 0x1000>;
9492 + interrupts = <0 17 0x4>;
9493 + little-endian;
9494 + };
9495 +
9496 + ddr2: memory-controller@1090000 {
9497 + compatible = "fsl,qoriq-memory-controller";
9498 + reg = <0x0 0x1090000 0x0 0x1000>;
9499 + interrupts = <0 18 0x4>;
9500 + little-endian;
9501 + };
9502 +
9503 + firmware {
9504 + optee {
9505 + compatible = "linaro,optee-tz";
9506 + method = "smc";
9507 + };
9508 + };
9509 +};
9510 --- /dev/null
9511 +++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
9512 @@ -0,0 +1,81 @@
9513 +/*
9514 + * QorIQ BMan Portals device tree
9515 + *
9516 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9517 + *
9518 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9519 + */
9520 +
9521 +&bportals {
9522 + #address-cells = <1>;
9523 + #size-cells = <1>;
9524 + compatible = "simple-bus";
9525 +
9526 + bman-portal@0 {
9527 + cell-index = <0>;
9528 + compatible = "fsl,bman-portal";
9529 + reg = <0x0 0x4000 0x4000000 0x4000>;
9530 + interrupts = <0 173 0x4>;
9531 + };
9532 +
9533 + bman-portal@10000 {
9534 + cell-index = <1>;
9535 + compatible = "fsl,bman-portal";
9536 + reg = <0x10000 0x4000 0x4010000 0x4000>;
9537 + interrupts = <0 175 0x4>;
9538 + };
9539 +
9540 + bman-portal@20000 {
9541 + cell-index = <2>;
9542 + compatible = "fsl,bman-portal";
9543 + reg = <0x20000 0x4000 0x4020000 0x4000>;
9544 + interrupts = <0 177 0x4>;
9545 + };
9546 +
9547 + bman-portal@30000 {
9548 + cell-index = <3>;
9549 + compatible = "fsl,bman-portal";
9550 + reg = <0x30000 0x4000 0x4030000 0x4000>;
9551 + interrupts = <0 179 0x4>;
9552 + };
9553 +
9554 + bman-portal@40000 {
9555 + cell-index = <4>;
9556 + compatible = "fsl,bman-portal";
9557 + reg = <0x40000 0x4000 0x4040000 0x4000>;
9558 + interrupts = <0 181 0x4>;
9559 + };
9560 +
9561 + bman-portal@50000 {
9562 + cell-index = <5>;
9563 + compatible = "fsl,bman-portal";
9564 + reg = <0x50000 0x4000 0x4050000 0x4000>;
9565 + interrupts = <0 183 0x4>;
9566 + };
9567 +
9568 + bman-portal@60000 {
9569 + cell-index = <6>;
9570 + compatible = "fsl,bman-portal";
9571 + reg = <0x60000 0x4000 0x4060000 0x4000>;
9572 + interrupts = <0 185 0x4>;
9573 + };
9574 +
9575 + bman-portal@70000 {
9576 + cell-index = <7>;
9577 + compatible = "fsl,bman-portal";
9578 + reg = <0x70000 0x4000 0x4070000 0x4000>;
9579 + interrupts = <0 187 0x4>;
9580 + };
9581 +
9582 + bman-portal@80000 {
9583 + cell-index = <8>;
9584 + compatible = "fsl,bman-portal";
9585 + reg = <0x80000 0x4000 0x4080000 0x4000>;
9586 + interrupts = <0 189 0x4>;
9587 + };
9588 +
9589 + bman-bpids@0 {
9590 + compatible = "fsl,bpid-range";
9591 + fsl,bpid-range = <32 32>;
9592 + };
9593 +};
9594 --- /dev/null
9595 +++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
9596 @@ -0,0 +1,73 @@
9597 +/*
9598 + * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
9599 + *
9600 + * Copyright 2012 - 2015 Freescale Semiconductor Inc.
9601 + *
9602 + * Redistribution and use in source and binary forms, with or without
9603 + * modification, are permitted provided that the following conditions are met:
9604 + * * Redistributions of source code must retain the above copyright
9605 + * notice, this list of conditions and the following disclaimer.
9606 + * * Redistributions in binary form must reproduce the above copyright
9607 + * notice, this list of conditions and the following disclaimer in the
9608 + * documentation and/or other materials provided with the distribution.
9609 + * * Neither the name of Freescale Semiconductor nor the
9610 + * names of its contributors may be used to endorse or promote products
9611 + * derived from this software without specific prior written permission.
9612 + *
9613 + *
9614 + * ALTERNATIVELY, this software may be distributed under the terms of the
9615 + * GNU General Public License ("GPL") as published by the Free Software
9616 + * Foundation, either version 2 of that License or (at your option) any
9617 + * later version.
9618 + *
9619 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9620 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9621 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9622 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9623 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9624 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9625 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9626 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9627 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9628 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9629 + */
9630 +
9631 +fsldpaa: fsl,dpaa {
9632 + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
9633 + ethernet@0 {
9634 + compatible = "fsl,dpa-ethernet";
9635 + fsl,fman-mac = <&enet0>;
9636 + dma-coherent;
9637 + };
9638 + ethernet@1 {
9639 + compatible = "fsl,dpa-ethernet";
9640 + fsl,fman-mac = <&enet1>;
9641 + dma-coherent;
9642 + };
9643 + ethernet@2 {
9644 + compatible = "fsl,dpa-ethernet";
9645 + fsl,fman-mac = <&enet2>;
9646 + dma-coherent;
9647 + };
9648 + ethernet@3 {
9649 + compatible = "fsl,dpa-ethernet";
9650 + fsl,fman-mac = <&enet3>;
9651 + dma-coherent;
9652 + };
9653 + ethernet@4 {
9654 + compatible = "fsl,dpa-ethernet";
9655 + fsl,fman-mac = <&enet4>;
9656 + dma-coherent;
9657 + };
9658 + ethernet@5 {
9659 + compatible = "fsl,dpa-ethernet";
9660 + fsl,fman-mac = <&enet5>;
9661 + dma-coherent;
9662 + };
9663 + ethernet@8 {
9664 + compatible = "fsl,dpa-ethernet";
9665 + fsl,fman-mac = <&enet6>;
9666 + dma-coherent;
9667 + };
9668 +};
9669 +
9670 --- /dev/null
9671 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
9672 @@ -0,0 +1,43 @@
9673 +/*
9674 + * QorIQ FMan v3 10g port #0 device tree
9675 + *
9676 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9677 + *
9678 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9679 + */
9680 +
9681 +fman@1a00000 {
9682 + fman0_rx_0x10: port@90000 {
9683 + cell-index = <0x10>;
9684 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9685 + reg = <0x90000 0x1000>;
9686 + fsl,fman-10g-port;
9687 + };
9688 +
9689 + fman0_tx_0x30: port@b0000 {
9690 + cell-index = <0x30>;
9691 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9692 + reg = <0xb0000 0x1000>;
9693 + fsl,fman-10g-port;
9694 + fsl,qman-channel-id = <0x800>;
9695 + };
9696 +
9697 + ethernet@f0000 {
9698 + cell-index = <0x8>;
9699 + compatible = "fsl,fman-memac";
9700 + reg = <0xf0000 0x1000>;
9701 + fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
9702 + pcsphy-handle = <&pcsphy6>;
9703 + };
9704 +
9705 + mdio@f1000 {
9706 + #address-cells = <1>;
9707 + #size-cells = <0>;
9708 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9709 + reg = <0xf1000 0x1000>;
9710 +
9711 + pcsphy6: ethernet-phy@0 {
9712 + reg = <0x0>;
9713 + };
9714 + };
9715 +};
9716 --- /dev/null
9717 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
9718 @@ -0,0 +1,43 @@
9719 +/*
9720 + * QorIQ FMan v3 10g port #1 device tree
9721 + *
9722 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9723 + *
9724 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9725 + */
9726 +
9727 +fman@1a00000 {
9728 + fman0_rx_0x11: port@91000 {
9729 + cell-index = <0x11>;
9730 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9731 + reg = <0x91000 0x1000>;
9732 + fsl,fman-10g-port;
9733 + };
9734 +
9735 + fman0_tx_0x31: port@b1000 {
9736 + cell-index = <0x31>;
9737 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9738 + reg = <0xb1000 0x1000>;
9739 + fsl,fman-10g-port;
9740 + fsl,qman-channel-id = <0x801>;
9741 + };
9742 +
9743 + ethernet@f2000 {
9744 + cell-index = <0x9>;
9745 + compatible = "fsl,fman-memac";
9746 + reg = <0xf2000 0x1000>;
9747 + fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
9748 + pcsphy-handle = <&pcsphy7>;
9749 + };
9750 +
9751 + mdio@f3000 {
9752 + #address-cells = <1>;
9753 + #size-cells = <0>;
9754 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9755 + reg = <0xf3000 0x1000>;
9756 +
9757 + pcsphy7: ethernet-phy@0 {
9758 + reg = <0x0>;
9759 + };
9760 + };
9761 +};
9762 --- /dev/null
9763 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
9764 @@ -0,0 +1,42 @@
9765 +/*
9766 + * QorIQ FMan v3 1g port #0 device tree
9767 + *
9768 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9769 + *
9770 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9771 + */
9772 +
9773 +fman@1a00000 {
9774 + fman0_rx_0x08: port@88000 {
9775 + cell-index = <0x8>;
9776 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9777 + reg = <0x88000 0x1000>;
9778 + };
9779 +
9780 + fman0_tx_0x28: port@a8000 {
9781 + cell-index = <0x28>;
9782 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9783 + reg = <0xa8000 0x1000>;
9784 + fsl,qman-channel-id = <0x802>;
9785 + };
9786 +
9787 + ethernet@e0000 {
9788 + cell-index = <0>;
9789 + compatible = "fsl,fman-memac";
9790 + reg = <0xe0000 0x1000>;
9791 + fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
9792 + ptp-timer = <&ptp_timer0>;
9793 + pcsphy-handle = <&pcsphy0>;
9794 + };
9795 +
9796 + mdio@e1000 {
9797 + #address-cells = <1>;
9798 + #size-cells = <0>;
9799 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9800 + reg = <0xe1000 0x1000>;
9801 +
9802 + pcsphy0: ethernet-phy@0 {
9803 + reg = <0x0>;
9804 + };
9805 + };
9806 +};
9807 --- /dev/null
9808 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
9809 @@ -0,0 +1,42 @@
9810 +/*
9811 + * QorIQ FMan v3 1g port #1 device tree
9812 + *
9813 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9814 + *
9815 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9816 + */
9817 +
9818 +fman@1a00000 {
9819 + fman0_rx_0x09: port@89000 {
9820 + cell-index = <0x9>;
9821 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9822 + reg = <0x89000 0x1000>;
9823 + };
9824 +
9825 + fman0_tx_0x29: port@a9000 {
9826 + cell-index = <0x29>;
9827 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9828 + reg = <0xa9000 0x1000>;
9829 + fsl,qman-channel-id = <0x803>;
9830 + };
9831 +
9832 + ethernet@e2000 {
9833 + cell-index = <1>;
9834 + compatible = "fsl,fman-memac";
9835 + reg = <0xe2000 0x1000>;
9836 + fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
9837 + ptp-timer = <&ptp_timer0>;
9838 + pcsphy-handle = <&pcsphy1>;
9839 + };
9840 +
9841 + mdio@e3000 {
9842 + #address-cells = <1>;
9843 + #size-cells = <0>;
9844 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9845 + reg = <0xe3000 0x1000>;
9846 +
9847 + pcsphy1: ethernet-phy@0 {
9848 + reg = <0x0>;
9849 + };
9850 + };
9851 +};
9852 --- /dev/null
9853 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
9854 @@ -0,0 +1,42 @@
9855 +/*
9856 + * QorIQ FMan v3 1g port #2 device tree
9857 + *
9858 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9859 + *
9860 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9861 + */
9862 +
9863 +fman@1a00000 {
9864 + fman0_rx_0x0a: port@8a000 {
9865 + cell-index = <0xa>;
9866 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9867 + reg = <0x8a000 0x1000>;
9868 + };
9869 +
9870 + fman0_tx_0x2a: port@aa000 {
9871 + cell-index = <0x2a>;
9872 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9873 + reg = <0xaa000 0x1000>;
9874 + fsl,qman-channel-id = <0x804>;
9875 + };
9876 +
9877 + ethernet@e4000 {
9878 + cell-index = <2>;
9879 + compatible = "fsl,fman-memac";
9880 + reg = <0xe4000 0x1000>;
9881 + fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
9882 + ptp-timer = <&ptp_timer0>;
9883 + pcsphy-handle = <&pcsphy2>;
9884 + };
9885 +
9886 + mdio@e5000 {
9887 + #address-cells = <1>;
9888 + #size-cells = <0>;
9889 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9890 + reg = <0xe5000 0x1000>;
9891 +
9892 + pcsphy2: ethernet-phy@0 {
9893 + reg = <0x0>;
9894 + };
9895 + };
9896 +};
9897 --- /dev/null
9898 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
9899 @@ -0,0 +1,42 @@
9900 +/*
9901 + * QorIQ FMan v3 1g port #3 device tree
9902 + *
9903 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9904 + *
9905 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9906 + */
9907 +
9908 +fman@1a00000 {
9909 + fman0_rx_0x0b: port@8b000 {
9910 + cell-index = <0xb>;
9911 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9912 + reg = <0x8b000 0x1000>;
9913 + };
9914 +
9915 + fman0_tx_0x2b: port@ab000 {
9916 + cell-index = <0x2b>;
9917 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9918 + reg = <0xab000 0x1000>;
9919 + fsl,qman-channel-id = <0x805>;
9920 + };
9921 +
9922 + ethernet@e6000 {
9923 + cell-index = <3>;
9924 + compatible = "fsl,fman-memac";
9925 + reg = <0xe6000 0x1000>;
9926 + fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
9927 + ptp-timer = <&ptp_timer0>;
9928 + pcsphy-handle = <&pcsphy3>;
9929 + };
9930 +
9931 + mdio@e7000 {
9932 + #address-cells = <1>;
9933 + #size-cells = <0>;
9934 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9935 + reg = <0xe7000 0x1000>;
9936 +
9937 + pcsphy3: ethernet-phy@0 {
9938 + reg = <0x0>;
9939 + };
9940 + };
9941 +};
9942 --- /dev/null
9943 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
9944 @@ -0,0 +1,42 @@
9945 +/*
9946 + * QorIQ FMan v3 1g port #4 device tree
9947 + *
9948 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9949 + *
9950 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9951 + */
9952 +
9953 +fman@1a00000 {
9954 + fman0_rx_0x0c: port@8c000 {
9955 + cell-index = <0xc>;
9956 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9957 + reg = <0x8c000 0x1000>;
9958 + };
9959 +
9960 + fman0_tx_0x2c: port@ac000 {
9961 + cell-index = <0x2c>;
9962 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9963 + reg = <0xac000 0x1000>;
9964 + fsl,qman-channel-id = <0x806>;
9965 + };
9966 +
9967 + ethernet@e8000 {
9968 + cell-index = <4>;
9969 + compatible = "fsl,fman-memac";
9970 + reg = <0xe8000 0x1000>;
9971 + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
9972 + ptp-timer = <&ptp_timer0>;
9973 + pcsphy-handle = <&pcsphy4>;
9974 + };
9975 +
9976 + mdio@e9000 {
9977 + #address-cells = <1>;
9978 + #size-cells = <0>;
9979 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9980 + reg = <0xe9000 0x1000>;
9981 +
9982 + pcsphy4: ethernet-phy@0 {
9983 + reg = <0x0>;
9984 + };
9985 + };
9986 +};
9987 --- /dev/null
9988 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
9989 @@ -0,0 +1,42 @@
9990 +/*
9991 + * QorIQ FMan v3 1g port #5 device tree
9992 + *
9993 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9994 + *
9995 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9996 + */
9997 +
9998 +fman@1a00000 {
9999 + fman0_rx_0x0d: port@8d000 {
10000 + cell-index = <0xd>;
10001 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
10002 + reg = <0x8d000 0x1000>;
10003 + };
10004 +
10005 + fman0_tx_0x2d: port@ad000 {
10006 + cell-index = <0x2d>;
10007 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
10008 + reg = <0xad000 0x1000>;
10009 + fsl,qman-channel-id = <0x807>;
10010 + };
10011 +
10012 + ethernet@ea000 {
10013 + cell-index = <5>;
10014 + compatible = "fsl,fman-memac";
10015 + reg = <0xea000 0x1000>;
10016 + fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
10017 + ptp-timer = <&ptp_timer0>;
10018 + pcsphy-handle = <&pcsphy5>;
10019 + };
10020 +
10021 + mdio@eb000 {
10022 + #address-cells = <1>;
10023 + #size-cells = <0>;
10024 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10025 + reg = <0xeb000 0x1000>;
10026 +
10027 + pcsphy5: ethernet-phy@0 {
10028 + reg = <0x0>;
10029 + };
10030 + };
10031 +};
10032 --- /dev/null
10033 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
10034 @@ -0,0 +1,47 @@
10035 +/*
10036 + * QorIQ FMan v3 OH ports device tree
10037 + *
10038 + * Copyright 2012-2015 Freescale Semiconductor Inc.
10039 + *
10040 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10041 + */
10042 +
10043 +fman@1a00000 {
10044 +
10045 + fman0_oh1: port@82000 {
10046 + cell-index = <0>;
10047 + compatible = "fsl,fman-port-oh";
10048 + reg = <0x82000 0x1000>;
10049 + };
10050 +
10051 + fman0_oh2: port@83000 {
10052 + cell-index = <1>;
10053 + compatible = "fsl,fman-port-oh";
10054 + reg = <0x83000 0x1000>;
10055 + };
10056 +
10057 + fman0_oh3: port@84000 {
10058 + cell-index = <2>;
10059 + compatible = "fsl,fman-port-oh";
10060 + reg = <0x84000 0x1000>;
10061 + };
10062 +
10063 + fman0_oh4: port@85000 {
10064 + cell-index = <3>;
10065 + compatible = "fsl,fman-port-oh";
10066 + reg = <0x85000 0x1000>;
10067 + };
10068 +
10069 + fman0_oh5: port@86000 {
10070 + cell-index = <4>;
10071 + compatible = "fsl,fman-port-oh";
10072 + reg = <0x86000 0x1000>;
10073 + };
10074 +
10075 + fman0_oh6: port@87000 {
10076 + cell-index = <5>;
10077 + compatible = "fsl,fman-port-oh";
10078 + reg = <0x87000 0x1000>;
10079 + };
10080 +
10081 +};
10082 --- /dev/null
10083 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
10084 @@ -0,0 +1,130 @@
10085 +/*
10086 + * QorIQ FMan v3 device tree
10087 + *
10088 + * Copyright 2012-2015 Freescale Semiconductor Inc.
10089 + *
10090 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10091 + */
10092 +
10093 +fman0: fman@1a00000 {
10094 + #address-cells = <1>;
10095 + #size-cells = <1>;
10096 + cell-index = <0>;
10097 + compatible = "fsl,fman";
10098 + ranges = <0x0 0x00 0x1a00000 0x100000>;
10099 + reg = <0x0 0x1a00000 0x0 0x100000>;
10100 + interrupts = <0 44 0x4>, <0 45 0x4>;
10101 + clocks = <&clockgen 3 0>;
10102 + clock-names = "fmanclk";
10103 + fsl,qman-channel-range = <0x800 0x10>;
10104 +
10105 + cc {
10106 + compatible = "fsl,fman-cc";
10107 + };
10108 +
10109 + muram@0 {
10110 + compatible = "fsl,fman-muram";
10111 + reg = <0x0 0x60000>;
10112 + };
10113 +
10114 + bmi@80000 {
10115 + compatible = "fsl,fman-bmi";
10116 + reg = <0x80000 0x400>;
10117 + };
10118 +
10119 + qmi@80400 {
10120 + compatible = "fsl,fman-qmi";
10121 + reg = <0x80400 0x400>;
10122 + };
10123 +
10124 + fman0_oh_0x2: port@82000 {
10125 + cell-index = <0x2>;
10126 + compatible = "fsl,fman-v3-port-oh";
10127 + reg = <0x82000 0x1000>;
10128 + fsl,qman-channel-id = <0x809>;
10129 + };
10130 +
10131 + fman0_oh_0x3: port@83000 {
10132 + cell-index = <0x3>;
10133 + compatible = "fsl,fman-v3-port-oh";
10134 + reg = <0x83000 0x1000>;
10135 + fsl,qman-channel-id = <0x80a>;
10136 + };
10137 +
10138 + fman0_oh_0x4: port@84000 {
10139 + cell-index = <0x4>;
10140 + compatible = "fsl,fman-v3-port-oh";
10141 + reg = <0x84000 0x1000>;
10142 + fsl,qman-channel-id = <0x80b>;
10143 + };
10144 +
10145 + fman0_oh_0x5: port@85000 {
10146 + cell-index = <0x5>;
10147 + compatible = "fsl,fman-v3-port-oh";
10148 + reg = <0x85000 0x1000>;
10149 + fsl,qman-channel-id = <0x80c>;
10150 + };
10151 +
10152 + fman0_oh_0x6: port@86000 {
10153 + cell-index = <0x6>;
10154 + compatible = "fsl,fman-v3-port-oh";
10155 + reg = <0x86000 0x1000>;
10156 + fsl,qman-channel-id = <0x80d>;
10157 + };
10158 +
10159 + fman0_oh_0x7: port@87000 {
10160 + cell-index = <0x7>;
10161 + compatible = "fsl,fman-v3-port-oh";
10162 + reg = <0x87000 0x1000>;
10163 + fsl,qman-channel-id = <0x80e>;
10164 + };
10165 +
10166 + policer@c0000 {
10167 + compatible = "fsl,fman-policer";
10168 + reg = <0xc0000 0x1000>;
10169 + };
10170 +
10171 + keygen@c1000 {
10172 + compatible = "fsl,fman-keygen";
10173 + reg = <0xc1000 0x1000>;
10174 + };
10175 +
10176 + dma@c2000 {
10177 + compatible = "fsl,fman-dma";
10178 + reg = <0xc2000 0x1000>;
10179 + };
10180 +
10181 + fpm@c3000 {
10182 + compatible = "fsl,fman-fpm";
10183 + reg = <0xc3000 0x1000>;
10184 + };
10185 +
10186 + parser@c7000 {
10187 + compatible = "fsl,fman-parser";
10188 + reg = <0xc7000 0x1000>;
10189 + };
10190 +
10191 + vsps@dc000 {
10192 + compatible = "fsl,fman-vsps";
10193 + reg = <0xdc000 0x1000>;
10194 + };
10195 +
10196 + mdio0: mdio@fc000 {
10197 + #address-cells = <1>;
10198 + #size-cells = <0>;
10199 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10200 + reg = <0xfc000 0x1000>;
10201 + };
10202 +
10203 + xmdio0: mdio@fd000 {
10204 + #address-cells = <1>;
10205 + #size-cells = <0>;
10206 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10207 + reg = <0xfd000 0x1000>;
10208 + };
10209 +
10210 + ptp_timer0: ptp-timer@fe000 {
10211 + compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
10212 + reg = <0xfe000 0x1000>;
10213 + };
10214 +};
10215 --- /dev/null
10216 +++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
10217 @@ -0,0 +1,104 @@
10218 +/*
10219 + * QorIQ QMan Portals device tree
10220 + *
10221 + * Copyright 2011-2016 Freescale Semiconductor Inc.
10222 + *
10223 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10224 + */
10225 +
10226 +&qportals {
10227 + #address-cells = <1>;
10228 + #size-cells = <1>;
10229 + compatible = "simple-bus";
10230 +
10231 + qportal0: qman-portal@0 {
10232 + compatible = "fsl,qman-portal";
10233 + reg = <0x0 0x4000 0x4000000 0x4000>;
10234 + interrupts = <0 172 0x4>;
10235 + cell-index = <0>;
10236 + };
10237 +
10238 + qportal1: qman-portal@10000 {
10239 + compatible = "fsl,qman-portal";
10240 + reg = <0x10000 0x4000 0x4010000 0x4000>;
10241 + interrupts = <0 174 0x4>;
10242 + cell-index = <1>;
10243 + };
10244 +
10245 + qportal2: qman-portal@20000 {
10246 + compatible = "fsl,qman-portal";
10247 + reg = <0x20000 0x4000 0x4020000 0x4000>;
10248 + interrupts = <0 176 0x4>;
10249 + cell-index = <2>;
10250 + };
10251 +
10252 + qportal3: qman-portal@30000 {
10253 + compatible = "fsl,qman-portal";
10254 + reg = <0x30000 0x4000 0x4030000 0x4000>;
10255 + interrupts = <0 178 0x4>;
10256 + cell-index = <3>;
10257 + };
10258 +
10259 + qportal4: qman-portal@40000 {
10260 + compatible = "fsl,qman-portal";
10261 + reg = <0x40000 0x4000 0x4040000 0x4000>;
10262 + interrupts = <0 180 0x4>;
10263 + cell-index = <4>;
10264 + };
10265 +
10266 + qportal5: qman-portal@50000 {
10267 + compatible = "fsl,qman-portal";
10268 + reg = <0x50000 0x4000 0x4050000 0x4000>;
10269 + interrupts = <0 182 0x4>;
10270 + cell-index = <5>;
10271 + };
10272 +
10273 + qportal6: qman-portal@60000 {
10274 + compatible = "fsl,qman-portal";
10275 + reg = <0x60000 0x4000 0x4060000 0x4000>;
10276 + interrupts = <0 184 0x4>;
10277 + cell-index = <6>;
10278 + };
10279 +
10280 + qportal7: qman-portal@70000 {
10281 + compatible = "fsl,qman-portal";
10282 + reg = <0x70000 0x4000 0x4070000 0x4000>;
10283 + interrupts = <0 186 0x4>;
10284 + cell-index = <7>;
10285 + };
10286 +
10287 + qportal8: qman-portal@80000 {
10288 + compatible = "fsl,qman-portal";
10289 + reg = <0x80000 0x4000 0x4080000 0x4000>;
10290 + interrupts = <0 188 0x4>;
10291 + cell-index = <8>;
10292 + };
10293 +
10294 + qman-fqids@0 {
10295 + compatible = "fsl,fqid-range";
10296 + fsl,fqid-range = <256 256>;
10297 + };
10298 +
10299 + qman-fqids@1 {
10300 + compatible = "fsl,fqid-range";
10301 + fsl,fqid-range = <32768 32768>;
10302 + };
10303 +
10304 + qman-pools@0 {
10305 + compatible = "fsl,pool-channel-range";
10306 + fsl,pool-channel-range = <0x401 0xf>;
10307 + };
10308 +
10309 + qman-cgrids@0 {
10310 + compatible = "fsl,cgrid-range";
10311 + fsl,cgrid-range = <0 256>;
10312 + };
10313 +
10314 + qman-ceetm@0 {
10315 + compatible = "fsl,qman-ceetm";
10316 + fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
10317 + fsl,ceetm-sp-range = <0 12>;
10318 + fsl,ceetm-lni-range = <0 8>;
10319 + fsl,ceetm-channel-range = <0 32>;
10320 + };
10321 +};
10322 --- a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10323 +++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10324 @@ -38,51 +38,61 @@
10325 compatible = "simple-bus";
10326  
10327 bman-portal@0 {
10328 + cell-index = <0>;
10329 compatible = "fsl,bman-portal";
10330 reg = <0x0 0x4000>, <0x100000 0x1000>;
10331 interrupts = <105 2 0 0>;
10332 };
10333 bman-portal@4000 {
10334 + cell-index = <1>;
10335 compatible = "fsl,bman-portal";
10336 reg = <0x4000 0x4000>, <0x101000 0x1000>;
10337 interrupts = <107 2 0 0>;
10338 };
10339 bman-portal@8000 {
10340 + cell-index = <2>;
10341 compatible = "fsl,bman-portal";
10342 reg = <0x8000 0x4000>, <0x102000 0x1000>;
10343 interrupts = <109 2 0 0>;
10344 };
10345 bman-portal@c000 {
10346 + cell-index = <3>;
10347 compatible = "fsl,bman-portal";
10348 reg = <0xc000 0x4000>, <0x103000 0x1000>;
10349 interrupts = <111 2 0 0>;
10350 };
10351 bman-portal@10000 {
10352 + cell-index = <4>;
10353 compatible = "fsl,bman-portal";
10354 reg = <0x10000 0x4000>, <0x104000 0x1000>;
10355 interrupts = <113 2 0 0>;
10356 };
10357 bman-portal@14000 {
10358 + cell-index = <5>;
10359 compatible = "fsl,bman-portal";
10360 reg = <0x14000 0x4000>, <0x105000 0x1000>;
10361 interrupts = <115 2 0 0>;
10362 };
10363 bman-portal@18000 {
10364 + cell-index = <6>;
10365 compatible = "fsl,bman-portal";
10366 reg = <0x18000 0x4000>, <0x106000 0x1000>;
10367 interrupts = <117 2 0 0>;
10368 };
10369 bman-portal@1c000 {
10370 + cell-index = <7>;
10371 compatible = "fsl,bman-portal";
10372 reg = <0x1c000 0x4000>, <0x107000 0x1000>;
10373 interrupts = <119 2 0 0>;
10374 };
10375 bman-portal@20000 {
10376 + cell-index = <8>;
10377 compatible = "fsl,bman-portal";
10378 reg = <0x20000 0x4000>, <0x108000 0x1000>;
10379 interrupts = <121 2 0 0>;
10380 };
10381 bman-portal@24000 {
10382 + cell-index = <9>;
10383 compatible = "fsl,bman-portal";
10384 reg = <0x24000 0x4000>, <0x109000 0x1000>;
10385 interrupts = <123 2 0 0>;
10386 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10387 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10388 @@ -35,14 +35,14 @@
10389 fman@400000 {
10390 fman0_rx_0x10: port@90000 {
10391 cell-index = <0x10>;
10392 - compatible = "fsl,fman-v3-port-rx";
10393 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10394 reg = <0x90000 0x1000>;
10395 fsl,fman-10g-port;
10396 };
10397  
10398 fman0_tx_0x30: port@b0000 {
10399 cell-index = <0x30>;
10400 - compatible = "fsl,fman-v3-port-tx";
10401 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10402 reg = <0xb0000 0x1000>;
10403 fsl,fman-10g-port;
10404 };
10405 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10406 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10407 @@ -35,14 +35,14 @@
10408 fman@400000 {
10409 fman0_rx_0x11: port@91000 {
10410 cell-index = <0x11>;
10411 - compatible = "fsl,fman-v3-port-rx";
10412 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10413 reg = <0x91000 0x1000>;
10414 fsl,fman-10g-port;
10415 };
10416  
10417 fman0_tx_0x31: port@b1000 {
10418 cell-index = <0x31>;
10419 - compatible = "fsl,fman-v3-port-tx";
10420 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10421 reg = <0xb1000 0x1000>;
10422 fsl,fman-10g-port;
10423 };