OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 1aa83e0a2821cd7f4e8f3ddb367859f52e468bf1 Mon Sep 17 00:00:00 2001 |
2 | From: Hauke Mehrtens <hauke@hauke-m.de> |
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3 | Date: Mon, 27 Feb 2017 23:21:25 +0100 |
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4 | Subject: spi: lantiq-ssc: add LTQ_ prefix to defines |
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5 | |||
6 | The blackfin architecture has a SPI_STAT define which conflicts with |
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7 | the define from the spi-lantiq-ssc driver in compile test mode. Fix |
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8 | this by adding a prefix in front of every define. |
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9 | |||
10 | Reported-by: kbuild test robot <fengguang.wu@intel.com> |
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11 | Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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12 | Signed-off-by: Mark Brown <broonie@kernel.org> |
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13 | --- |
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14 | drivers/spi/spi-lantiq-ssc.c | 437 ++++++++++++++++++++++--------------------- |
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15 | 1 file changed, 222 insertions(+), 215 deletions(-) |
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16 | |||
17 | --- a/drivers/spi/spi-lantiq-ssc.c |
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18 | +++ b/drivers/spi/spi-lantiq-ssc.c |
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19 | @@ -26,136 +26,140 @@ |
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20 | #include <lantiq_soc.h> |
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21 | #endif |
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22 | |||
23 | -#define SPI_RX_IRQ_NAME "spi_rx" |
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24 | -#define SPI_TX_IRQ_NAME "spi_tx" |
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25 | -#define SPI_ERR_IRQ_NAME "spi_err" |
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26 | -#define SPI_FRM_IRQ_NAME "spi_frm" |
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27 | - |
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28 | -#define SPI_CLC 0x00 |
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29 | -#define SPI_PISEL 0x04 |
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30 | -#define SPI_ID 0x08 |
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31 | -#define SPI_CON 0x10 |
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32 | -#define SPI_STAT 0x14 |
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33 | -#define SPI_WHBSTATE 0x18 |
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34 | -#define SPI_TB 0x20 |
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35 | -#define SPI_RB 0x24 |
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36 | -#define SPI_RXFCON 0x30 |
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37 | -#define SPI_TXFCON 0x34 |
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38 | -#define SPI_FSTAT 0x38 |
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39 | -#define SPI_BRT 0x40 |
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40 | -#define SPI_BRSTAT 0x44 |
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41 | -#define SPI_SFCON 0x60 |
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42 | -#define SPI_SFSTAT 0x64 |
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43 | -#define SPI_GPOCON 0x70 |
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44 | -#define SPI_GPOSTAT 0x74 |
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45 | -#define SPI_FPGO 0x78 |
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46 | -#define SPI_RXREQ 0x80 |
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47 | -#define SPI_RXCNT 0x84 |
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48 | -#define SPI_DMACON 0xec |
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49 | -#define SPI_IRNEN 0xf4 |
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50 | -#define SPI_IRNICR 0xf8 |
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51 | -#define SPI_IRNCR 0xfc |
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52 | - |
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53 | -#define SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ |
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54 | -#define SPI_CLC_SMC_M (0xFF << SPI_CLC_SMC_S) |
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55 | -#define SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ |
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56 | -#define SPI_CLC_RMC_M (0xFF << SPI_CLC_RMC_S) |
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57 | -#define SPI_CLC_DISS BIT(1) /* Disable status bit */ |
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58 | -#define SPI_CLC_DISR BIT(0) /* Disable request bit */ |
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59 | - |
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60 | -#define SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ |
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61 | -#define SPI_ID_TXFS_M (0x3F << SPI_ID_TXFS_S) |
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62 | -#define SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ |
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63 | -#define SPI_ID_RXFS_M (0x3F << SPI_ID_RXFS_S) |
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64 | -#define SPI_ID_MOD_S 8 /* Module ID */ |
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65 | -#define SPI_ID_MOD_M (0xff << SPI_ID_MOD_S) |
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66 | -#define SPI_ID_CFG_S 5 /* DMA interface support */ |
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67 | -#define SPI_ID_CFG_M (1 << SPI_ID_CFG_S) |
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68 | -#define SPI_ID_REV_M 0x1F /* Hardware revision number */ |
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69 | - |
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70 | -#define SPI_CON_BM_S 16 /* Data width selection */ |
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71 | -#define SPI_CON_BM_M (0x1F << SPI_CON_BM_S) |
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72 | -#define SPI_CON_EM BIT(24) /* Echo mode */ |
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73 | -#define SPI_CON_IDLE BIT(23) /* Idle bit value */ |
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74 | -#define SPI_CON_ENBV BIT(22) /* Enable byte valid control */ |
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75 | -#define SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ |
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76 | -#define SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ |
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77 | -#define SPI_CON_AEN BIT(10) /* Abort error enable */ |
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78 | -#define SPI_CON_REN BIT(9) /* Receive overflow error enable */ |
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79 | -#define SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ |
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80 | -#define SPI_CON_LB BIT(7) /* Loopback control */ |
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81 | -#define SPI_CON_PO BIT(6) /* Clock polarity control */ |
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82 | -#define SPI_CON_PH BIT(5) /* Clock phase control */ |
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83 | -#define SPI_CON_HB BIT(4) /* Heading control */ |
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84 | -#define SPI_CON_RXOFF BIT(1) /* Switch receiver off */ |
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85 | -#define SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ |
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86 | - |
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87 | -#define SPI_STAT_RXBV_S 28 |
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88 | -#define SPI_STAT_RXBV_M (0x7 << SPI_STAT_RXBV_S) |
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89 | -#define SPI_STAT_BSY BIT(13) /* Busy flag */ |
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90 | -#define SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ |
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91 | -#define SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ |
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92 | -#define SPI_STAT_AE BIT(10) /* Abort error flag */ |
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93 | -#define SPI_STAT_RE BIT(9) /* Receive error flag */ |
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94 | -#define SPI_STAT_TE BIT(8) /* Transmit error flag */ |
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95 | -#define SPI_STAT_ME BIT(7) /* Mode error flag */ |
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96 | -#define SPI_STAT_MS BIT(1) /* Master/slave select bit */ |
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97 | -#define SPI_STAT_EN BIT(0) /* Enable bit */ |
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98 | -#define SPI_STAT_ERRORS (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \ |
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99 | - SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE) |
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100 | - |
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101 | -#define SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ |
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102 | -#define SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ |
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103 | -#define SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ |
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104 | -#define SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ |
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105 | -#define SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ |
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106 | -#define SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ |
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107 | -#define SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ |
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108 | -#define SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ |
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109 | -#define SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ |
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110 | -#define SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ |
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111 | -#define SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ |
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112 | -#define SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ |
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113 | -#define SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ |
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114 | -#define SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ |
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115 | -#define SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ |
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116 | -#define SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ |
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117 | -#define SPI_WHBSTATE_CLR_ERRORS (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \ |
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118 | - SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \ |
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119 | - SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE) |
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120 | - |
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121 | -#define SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ |
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122 | -#define SPI_RXFCON_RXFITL_M (0x3F << SPI_RXFCON_RXFITL_S) |
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123 | -#define SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ |
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124 | -#define SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ |
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125 | - |
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126 | -#define SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ |
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127 | -#define SPI_TXFCON_TXFITL_M (0x3F << SPI_TXFCON_TXFITL_S) |
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128 | -#define SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ |
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129 | -#define SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ |
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130 | - |
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131 | -#define SPI_FSTAT_RXFFL_S 0 |
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132 | -#define SPI_FSTAT_RXFFL_M (0x3f << SPI_FSTAT_RXFFL_S) |
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133 | -#define SPI_FSTAT_TXFFL_S 8 |
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134 | -#define SPI_FSTAT_TXFFL_M (0x3f << SPI_FSTAT_TXFFL_S) |
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135 | - |
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136 | -#define SPI_GPOCON_ISCSBN_S 8 |
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137 | -#define SPI_GPOCON_INVOUTN_S 0 |
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138 | - |
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139 | -#define SPI_FGPO_SETOUTN_S 8 |
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140 | -#define SPI_FGPO_CLROUTN_S 0 |
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141 | - |
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142 | -#define SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ |
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143 | -#define SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ |
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144 | - |
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145 | -#define SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ |
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146 | -#define SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ |
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147 | -#define SPI_IRNEN_E BIT(2) /* Error end interrupt request */ |
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148 | -#define SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ |
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149 | -#define SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ |
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150 | -#define SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ |
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151 | -#define SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ |
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152 | -#define SPI_IRNEN_ALL 0x1F |
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153 | +#define LTQ_SPI_RX_IRQ_NAME "spi_rx" |
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154 | +#define LTQ_SPI_TX_IRQ_NAME "spi_tx" |
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155 | +#define LTQ_SPI_ERR_IRQ_NAME "spi_err" |
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156 | +#define LTQ_SPI_FRM_IRQ_NAME "spi_frm" |
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157 | + |
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158 | +#define LTQ_SPI_CLC 0x00 |
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159 | +#define LTQ_SPI_PISEL 0x04 |
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160 | +#define LTQ_SPI_ID 0x08 |
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161 | +#define LTQ_SPI_CON 0x10 |
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162 | +#define LTQ_SPI_STAT 0x14 |
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163 | +#define LTQ_SPI_WHBSTATE 0x18 |
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164 | +#define LTQ_SPI_TB 0x20 |
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165 | +#define LTQ_SPI_RB 0x24 |
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166 | +#define LTQ_SPI_RXFCON 0x30 |
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167 | +#define LTQ_SPI_TXFCON 0x34 |
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168 | +#define LTQ_SPI_FSTAT 0x38 |
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169 | +#define LTQ_SPI_BRT 0x40 |
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170 | +#define LTQ_SPI_BRSTAT 0x44 |
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171 | +#define LTQ_SPI_SFCON 0x60 |
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172 | +#define LTQ_SPI_SFSTAT 0x64 |
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173 | +#define LTQ_SPI_GPOCON 0x70 |
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174 | +#define LTQ_SPI_GPOSTAT 0x74 |
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175 | +#define LTQ_SPI_FPGO 0x78 |
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176 | +#define LTQ_SPI_RXREQ 0x80 |
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177 | +#define LTQ_SPI_RXCNT 0x84 |
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178 | +#define LTQ_SPI_DMACON 0xec |
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179 | +#define LTQ_SPI_IRNEN 0xf4 |
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180 | +#define LTQ_SPI_IRNICR 0xf8 |
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181 | +#define LTQ_SPI_IRNCR 0xfc |
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182 | + |
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183 | +#define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ |
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184 | +#define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S) |
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185 | +#define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ |
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186 | +#define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S) |
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187 | +#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ |
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188 | +#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ |
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189 | + |
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190 | +#define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ |
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191 | +#define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S) |
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192 | +#define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ |
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193 | +#define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S) |
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194 | +#define LTQ_SPI_ID_MOD_S 8 /* Module ID */ |
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195 | +#define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S) |
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196 | +#define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */ |
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197 | +#define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S) |
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198 | +#define LTQ_SPI_ID_REV_M 0x1F /* Hardware revision number */ |
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199 | + |
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200 | +#define LTQ_SPI_CON_BM_S 16 /* Data width selection */ |
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201 | +#define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S) |
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202 | +#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ |
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203 | +#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ |
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204 | +#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ |
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205 | +#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ |
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206 | +#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ |
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207 | +#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ |
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208 | +#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ |
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209 | +#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ |
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210 | +#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ |
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211 | +#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ |
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212 | +#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ |
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213 | +#define LTQ_SPI_CON_HB BIT(4) /* Heading control */ |
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214 | +#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ |
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215 | +#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ |
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216 | + |
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217 | +#define LTQ_SPI_STAT_RXBV_S 28 |
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218 | +#define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S) |
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219 | +#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ |
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220 | +#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ |
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221 | +#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ |
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222 | +#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ |
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223 | +#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ |
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224 | +#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ |
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225 | +#define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */ |
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226 | +#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ |
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227 | +#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ |
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228 | +#define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \ |
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229 | + LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \ |
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230 | + LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE) |
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231 | + |
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232 | +#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ |
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233 | +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ |
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234 | +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ |
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235 | +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ |
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236 | +#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ |
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237 | +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ |
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238 | +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ |
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239 | +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ |
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240 | +#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ |
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241 | +#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ |
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242 | +#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ |
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243 | +#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ |
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244 | +#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ |
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245 | +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ |
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246 | +#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ |
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247 | +#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ |
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248 | +#define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \ |
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249 | + LTQ_SPI_WHBSTATE_CLRME | \ |
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250 | + LTQ_SPI_WHBSTATE_CLRTE | \ |
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251 | + LTQ_SPI_WHBSTATE_CLRRE | \ |
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252 | + LTQ_SPI_WHBSTATE_CLRAE | \ |
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253 | + LTQ_SPI_WHBSTATE_CLRTUE) |
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254 | + |
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255 | +#define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ |
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256 | +#define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S) |
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257 | +#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ |
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258 | +#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ |
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259 | + |
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260 | +#define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ |
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261 | +#define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S) |
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262 | +#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ |
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263 | +#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ |
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264 | + |
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265 | +#define LTQ_SPI_FSTAT_RXFFL_S 0 |
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266 | +#define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S) |
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267 | +#define LTQ_SPI_FSTAT_TXFFL_S 8 |
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268 | +#define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S) |
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269 | + |
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270 | +#define LTQ_SPI_GPOCON_ISCSBN_S 8 |
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271 | +#define LTQ_SPI_GPOCON_INVOUTN_S 0 |
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272 | + |
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273 | +#define LTQ_SPI_FGPO_SETOUTN_S 8 |
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274 | +#define LTQ_SPI_FGPO_CLROUTN_S 0 |
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275 | + |
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276 | +#define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ |
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277 | +#define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ |
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278 | + |
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279 | +#define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ |
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280 | +#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ |
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281 | +#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ |
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282 | +#define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ |
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283 | +#define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ |
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284 | +#define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ |
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285 | +#define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ |
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286 | +#define LTQ_SPI_IRNEN_ALL 0x1F |
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287 | |||
288 | struct lantiq_ssc_hwcfg { |
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289 | unsigned int irnen_r; |
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290 | @@ -208,16 +212,16 @@ static void lantiq_ssc_maskl(const struc |
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291 | |||
292 | static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi) |
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293 | { |
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294 | - u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); |
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295 | + u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); |
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296 | |||
297 | - return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S; |
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298 | + return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S; |
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299 | } |
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300 | |||
301 | static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi) |
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302 | { |
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303 | - u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); |
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304 | + u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); |
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305 | |||
306 | - return fstat & SPI_FSTAT_RXFFL_M; |
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307 | + return fstat & LTQ_SPI_FSTAT_RXFFL_M; |
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308 | } |
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309 | |||
310 | static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) |
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311 | @@ -227,38 +231,38 @@ static unsigned int tx_fifo_free(const s |
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312 | |||
313 | static void rx_fifo_reset(const struct lantiq_ssc_spi *spi) |
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314 | { |
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315 | - u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S; |
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316 | + u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S; |
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317 | |||
318 | - val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU; |
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319 | - lantiq_ssc_writel(spi, val, SPI_RXFCON); |
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320 | + val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; |
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321 | + lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON); |
||
322 | } |
||
323 | |||
324 | static void tx_fifo_reset(const struct lantiq_ssc_spi *spi) |
||
325 | { |
||
326 | - u32 val = 1 << SPI_TXFCON_TXFITL_S; |
||
327 | + u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S; |
||
328 | |||
329 | - val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU; |
||
330 | - lantiq_ssc_writel(spi, val, SPI_TXFCON); |
||
331 | + val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; |
||
332 | + lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON); |
||
333 | } |
||
334 | |||
335 | static void rx_fifo_flush(const struct lantiq_ssc_spi *spi) |
||
336 | { |
||
337 | - lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON); |
||
338 | + lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); |
||
339 | } |
||
340 | |||
341 | static void tx_fifo_flush(const struct lantiq_ssc_spi *spi) |
||
342 | { |
||
343 | - lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON); |
||
344 | + lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); |
||
345 | } |
||
346 | |||
347 | static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi) |
||
348 | { |
||
349 | - lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE); |
||
350 | + lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); |
||
351 | } |
||
352 | |||
353 | static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi) |
||
354 | { |
||
355 | - lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE); |
||
356 | + lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); |
||
357 | } |
||
358 | |||
359 | static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, |
||
360 | @@ -287,7 +291,7 @@ static void hw_setup_speed_hz(const stru |
||
361 | dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n", |
||
362 | spi_clk, max_speed_hz, brt); |
||
363 | |||
364 | - lantiq_ssc_writel(spi, brt, SPI_BRT); |
||
365 | + lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT); |
||
366 | } |
||
367 | |||
368 | static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, |
||
369 | @@ -296,9 +300,9 @@ static void hw_setup_bits_per_word(const |
||
370 | u32 bm; |
||
371 | |||
372 | /* CON.BM value = bits_per_word - 1 */ |
||
373 | - bm = (bits_per_word - 1) << SPI_CON_BM_S; |
||
374 | + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S; |
||
375 | |||
376 | - lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON); |
||
377 | + lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON); |
||
378 | } |
||
379 | |||
380 | static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, |
||
381 | @@ -315,28 +319,28 @@ static void hw_setup_clock_mode(const st |
||
382 | * 3 1 1 1 0 |
||
383 | */ |
||
384 | if (mode & SPI_CPHA) |
||
385 | - con_clr |= SPI_CON_PH; |
||
386 | + con_clr |= LTQ_SPI_CON_PH; |
||
387 | else |
||
388 | - con_set |= SPI_CON_PH; |
||
389 | + con_set |= LTQ_SPI_CON_PH; |
||
390 | |||
391 | if (mode & SPI_CPOL) |
||
392 | - con_set |= SPI_CON_PO | SPI_CON_IDLE; |
||
393 | + con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; |
||
394 | else |
||
395 | - con_clr |= SPI_CON_PO | SPI_CON_IDLE; |
||
396 | + con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; |
||
397 | |||
398 | /* Set heading control */ |
||
399 | if (mode & SPI_LSB_FIRST) |
||
400 | - con_clr |= SPI_CON_HB; |
||
401 | + con_clr |= LTQ_SPI_CON_HB; |
||
402 | else |
||
403 | - con_set |= SPI_CON_HB; |
||
404 | + con_set |= LTQ_SPI_CON_HB; |
||
405 | |||
406 | /* Set loopback mode */ |
||
407 | if (mode & SPI_LOOP) |
||
408 | - con_set |= SPI_CON_LB; |
||
409 | + con_set |= LTQ_SPI_CON_LB; |
||
410 | else |
||
411 | - con_clr |= SPI_CON_LB; |
||
412 | + con_clr |= LTQ_SPI_CON_LB; |
||
413 | |||
414 | - lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON); |
||
415 | + lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON); |
||
416 | } |
||
417 | |||
418 | static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) |
||
419 | @@ -347,37 +351,39 @@ static void lantiq_ssc_hw_init(const str |
||
420 | * Set clock divider for run mode to 1 to |
||
421 | * run at same frequency as FPI bus |
||
422 | */ |
||
423 | - lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC); |
||
424 | + lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC); |
||
425 | |||
426 | /* Put controller into config mode */ |
||
427 | hw_enter_config_mode(spi); |
||
428 | |||
429 | /* Clear error flags */ |
||
430 | - lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); |
||
431 | + lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); |
||
432 | |||
433 | /* Enable error checking, disable TX/RX */ |
||
434 | - lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN | |
||
435 | - SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); |
||
436 | + lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | |
||
437 | + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF | |
||
438 | + LTQ_SPI_CON_RXOFF, LTQ_SPI_CON); |
||
439 | |||
440 | /* Setup default SPI mode */ |
||
441 | hw_setup_bits_per_word(spi, spi->bits_per_word); |
||
442 | hw_setup_clock_mode(spi, SPI_MODE_0); |
||
443 | |||
444 | /* Enable master mode and clear error flags */ |
||
445 | - lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS, |
||
446 | - SPI_WHBSTATE); |
||
447 | + lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS | |
||
448 | + LTQ_SPI_WHBSTATE_CLR_ERRORS, |
||
449 | + LTQ_SPI_WHBSTATE); |
||
450 | |||
451 | /* Reset GPIO/CS registers */ |
||
452 | - lantiq_ssc_writel(spi, 0, SPI_GPOCON); |
||
453 | - lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO); |
||
454 | + lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON); |
||
455 | + lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO); |
||
456 | |||
457 | /* Enable and flush FIFOs */ |
||
458 | rx_fifo_reset(spi); |
||
459 | tx_fifo_reset(spi); |
||
460 | |||
461 | /* Enable interrupts */ |
||
462 | - lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E, |
||
463 | - SPI_IRNEN); |
||
464 | + lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | |
||
465 | + LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN); |
||
466 | } |
||
467 | |||
468 | static int lantiq_ssc_setup(struct spi_device *spidev) |
||
469 | @@ -400,13 +406,13 @@ static int lantiq_ssc_setup(struct spi_d |
||
470 | } |
||
471 | |||
472 | /* set GPO pin to CS mode */ |
||
473 | - gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S); |
||
474 | + gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S); |
||
475 | |||
476 | /* invert GPO pin */ |
||
477 | if (spidev->mode & SPI_CS_HIGH) |
||
478 | gpocon |= 1 << (cs - spi->base_cs); |
||
479 | |||
480 | - lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON); |
||
481 | + lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON); |
||
482 | |||
483 | return 0; |
||
484 | } |
||
485 | @@ -442,18 +448,18 @@ static void hw_setup_transfer(struct lan |
||
486 | } |
||
487 | |||
488 | /* Configure transmitter and receiver */ |
||
489 | - con = lantiq_ssc_readl(spi, SPI_CON); |
||
490 | + con = lantiq_ssc_readl(spi, LTQ_SPI_CON); |
||
491 | if (t->tx_buf) |
||
492 | - con &= ~SPI_CON_TXOFF; |
||
493 | + con &= ~LTQ_SPI_CON_TXOFF; |
||
494 | else |
||
495 | - con |= SPI_CON_TXOFF; |
||
496 | + con |= LTQ_SPI_CON_TXOFF; |
||
497 | |||
498 | if (t->rx_buf) |
||
499 | - con &= ~SPI_CON_RXOFF; |
||
500 | + con &= ~LTQ_SPI_CON_RXOFF; |
||
501 | else |
||
502 | - con |= SPI_CON_RXOFF; |
||
503 | + con |= LTQ_SPI_CON_RXOFF; |
||
504 | |||
505 | - lantiq_ssc_writel(spi, con, SPI_CON); |
||
506 | + lantiq_ssc_writel(spi, con, LTQ_SPI_CON); |
||
507 | } |
||
508 | |||
509 | static int lantiq_ssc_unprepare_message(struct spi_master *master, |
||
510 | @@ -464,7 +470,8 @@ static int lantiq_ssc_unprepare_message( |
||
511 | flush_workqueue(spi->wq); |
||
512 | |||
513 | /* Disable transmitter and receiver while idle */ |
||
514 | - lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); |
||
515 | + lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF, |
||
516 | + LTQ_SPI_CON); |
||
517 | |||
518 | return 0; |
||
519 | } |
||
520 | @@ -503,7 +510,7 @@ static void tx_fifo_write(struct lantiq_ |
||
521 | break; |
||
522 | } |
||
523 | |||
524 | - lantiq_ssc_writel(spi, data, SPI_TB); |
||
525 | + lantiq_ssc_writel(spi, data, LTQ_SPI_TB); |
||
526 | tx_free--; |
||
527 | } |
||
528 | } |
||
529 | @@ -517,7 +524,7 @@ static void rx_fifo_read_full_duplex(str |
||
530 | unsigned int rx_fill = rx_fifo_level(spi); |
||
531 | |||
532 | while (rx_fill) { |
||
533 | - data = lantiq_ssc_readl(spi, SPI_RB); |
||
534 | + data = lantiq_ssc_readl(spi, LTQ_SPI_RB); |
||
535 | |||
536 | switch (spi->bits_per_word) { |
||
537 | case 2 ... 8: |
||
538 | @@ -563,9 +570,9 @@ static void rx_fifo_read_half_duplex(str |
||
539 | */ |
||
540 | while (rx_fill) { |
||
541 | if (spi->rx_todo < 4) { |
||
542 | - rxbv = (lantiq_ssc_readl(spi, SPI_STAT) & |
||
543 | - SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S; |
||
544 | - data = lantiq_ssc_readl(spi, SPI_RB); |
||
545 | + rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) & |
||
546 | + LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S; |
||
547 | + data = lantiq_ssc_readl(spi, LTQ_SPI_RB); |
||
548 | |||
549 | shift = (rxbv - 1) * 8; |
||
550 | rx8 = spi->rx; |
||
551 | @@ -578,7 +585,7 @@ static void rx_fifo_read_half_duplex(str |
||
552 | spi->rx++; |
||
553 | } |
||
554 | } else { |
||
555 | - data = lantiq_ssc_readl(spi, SPI_RB); |
||
556 | + data = lantiq_ssc_readl(spi, LTQ_SPI_RB); |
||
557 | rx32 = (u32 *) spi->rx; |
||
558 | |||
559 | *rx32++ = data; |
||
560 | @@ -603,7 +610,7 @@ static void rx_request(struct lantiq_ssc |
||
561 | if (rxreq > rxreq_max) |
||
562 | rxreq = rxreq_max; |
||
563 | |||
564 | - lantiq_ssc_writel(spi, rxreq, SPI_RXREQ); |
||
565 | + lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ); |
||
566 | } |
||
567 | |||
568 | static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data) |
||
569 | @@ -642,26 +649,26 @@ completed: |
||
570 | static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data) |
||
571 | { |
||
572 | struct lantiq_ssc_spi *spi = data; |
||
573 | - u32 stat = lantiq_ssc_readl(spi, SPI_STAT); |
||
574 | + u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); |
||
575 | |||
576 | - if (!(stat & SPI_STAT_ERRORS)) |
||
577 | + if (!(stat & LTQ_SPI_STAT_ERRORS)) |
||
578 | return IRQ_NONE; |
||
579 | |||
580 | - if (stat & SPI_STAT_RUE) |
||
581 | + if (stat & LTQ_SPI_STAT_RUE) |
||
582 | dev_err(spi->dev, "receive underflow error\n"); |
||
583 | - if (stat & SPI_STAT_TUE) |
||
584 | + if (stat & LTQ_SPI_STAT_TUE) |
||
585 | dev_err(spi->dev, "transmit underflow error\n"); |
||
586 | - if (stat & SPI_STAT_AE) |
||
587 | + if (stat & LTQ_SPI_STAT_AE) |
||
588 | dev_err(spi->dev, "abort error\n"); |
||
589 | - if (stat & SPI_STAT_RE) |
||
590 | + if (stat & LTQ_SPI_STAT_RE) |
||
591 | dev_err(spi->dev, "receive overflow error\n"); |
||
592 | - if (stat & SPI_STAT_TE) |
||
593 | + if (stat & LTQ_SPI_STAT_TE) |
||
594 | dev_err(spi->dev, "transmit overflow error\n"); |
||
595 | - if (stat & SPI_STAT_ME) |
||
596 | + if (stat & LTQ_SPI_STAT_ME) |
||
597 | dev_err(spi->dev, "mode error\n"); |
||
598 | |||
599 | /* Clear error flags */ |
||
600 | - lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); |
||
601 | + lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); |
||
602 | |||
603 | /* set bad status so it can be retried */ |
||
604 | if (spi->master->cur_msg) |
||
605 | @@ -721,9 +728,9 @@ static void lantiq_ssc_bussy_work(struct |
||
606 | |||
607 | end = jiffies + msecs_to_jiffies(timeout); |
||
608 | do { |
||
609 | - u32 stat = lantiq_ssc_readl(spi, SPI_STAT); |
||
610 | + u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); |
||
611 | |||
612 | - if (!(stat & SPI_STAT_BSY)) { |
||
613 | + if (!(stat & LTQ_SPI_STAT_BSY)) { |
||
614 | spi_finalize_current_transfer(spi->master); |
||
615 | return; |
||
616 | } |
||
617 | @@ -755,9 +762,9 @@ static void lantiq_ssc_set_cs(struct spi |
||
618 | if (!!(spidev->mode & SPI_CS_HIGH) == enable) |
||
619 | fgpo = (1 << (cs - spi->base_cs)); |
||
620 | else |
||
621 | - fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S)); |
||
622 | + fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S)); |
||
623 | |||
624 | - lantiq_ssc_writel(spi, fgpo, SPI_FPGO); |
||
625 | + lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO); |
||
626 | } |
||
627 | |||
628 | static int lantiq_ssc_transfer_one(struct spi_master *master, |
||
629 | @@ -772,13 +779,13 @@ static int lantiq_ssc_transfer_one(struc |
||
630 | } |
||
631 | |||
632 | static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = { |
||
633 | - .irnen_r = SPI_IRNEN_R_XWAY, |
||
634 | - .irnen_t = SPI_IRNEN_T_XWAY, |
||
635 | + .irnen_r = LTQ_SPI_IRNEN_R_XWAY, |
||
636 | + .irnen_t = LTQ_SPI_IRNEN_T_XWAY, |
||
637 | }; |
||
638 | |||
639 | static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = { |
||
640 | - .irnen_r = SPI_IRNEN_R_XRX, |
||
641 | - .irnen_t = SPI_IRNEN_T_XRX, |
||
642 | + .irnen_r = LTQ_SPI_IRNEN_R_XRX, |
||
643 | + .irnen_t = LTQ_SPI_IRNEN_T_XRX, |
||
644 | }; |
||
645 | |||
646 | static const struct of_device_id lantiq_ssc_match[] = { |
||
647 | @@ -814,21 +821,21 @@ static int lantiq_ssc_probe(struct platf |
||
648 | return -ENXIO; |
||
649 | } |
||
650 | |||
651 | - rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME); |
||
652 | + rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME); |
||
653 | if (rx_irq < 0) { |
||
654 | - dev_err(dev, "failed to get %s\n", SPI_RX_IRQ_NAME); |
||
655 | + dev_err(dev, "failed to get %s\n", LTQ_SPI_RX_IRQ_NAME); |
||
656 | return -ENXIO; |
||
657 | } |
||
658 | |||
659 | - tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME); |
||
660 | + tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME); |
||
661 | if (tx_irq < 0) { |
||
662 | - dev_err(dev, "failed to get %s\n", SPI_TX_IRQ_NAME); |
||
663 | + dev_err(dev, "failed to get %s\n", LTQ_SPI_TX_IRQ_NAME); |
||
664 | return -ENXIO; |
||
665 | } |
||
666 | |||
667 | - err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME); |
||
668 | + err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME); |
||
669 | if (err_irq < 0) { |
||
670 | - dev_err(dev, "failed to get %s\n", SPI_ERR_IRQ_NAME); |
||
671 | + dev_err(dev, "failed to get %s\n", LTQ_SPI_ERR_IRQ_NAME); |
||
672 | return -ENXIO; |
||
673 | } |
||
674 | |||
675 | @@ -849,17 +856,17 @@ static int lantiq_ssc_probe(struct platf |
||
676 | } |
||
677 | |||
678 | err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt, |
||
679 | - 0, SPI_RX_IRQ_NAME, spi); |
||
680 | + 0, LTQ_SPI_RX_IRQ_NAME, spi); |
||
681 | if (err) |
||
682 | goto err_master_put; |
||
683 | |||
684 | err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt, |
||
685 | - 0, SPI_TX_IRQ_NAME, spi); |
||
686 | + 0, LTQ_SPI_TX_IRQ_NAME, spi); |
||
687 | if (err) |
||
688 | goto err_master_put; |
||
689 | |||
690 | err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt, |
||
691 | - 0, SPI_ERR_IRQ_NAME, spi); |
||
692 | + 0, LTQ_SPI_ERR_IRQ_NAME, spi); |
||
693 | if (err) |
||
694 | goto err_master_put; |
||
695 | |||
696 | @@ -916,11 +923,11 @@ static int lantiq_ssc_probe(struct platf |
||
697 | } |
||
698 | INIT_WORK(&spi->work, lantiq_ssc_bussy_work); |
||
699 | |||
700 | - id = lantiq_ssc_readl(spi, SPI_ID); |
||
701 | - spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S; |
||
702 | - spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S; |
||
703 | - supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S; |
||
704 | - revision = id & SPI_ID_REV_M; |
||
705 | + id = lantiq_ssc_readl(spi, LTQ_SPI_ID); |
||
706 | + spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S; |
||
707 | + spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S; |
||
708 | + supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S; |
||
709 | + revision = id & LTQ_SPI_ID_REV_M; |
||
710 | |||
711 | lantiq_ssc_hw_init(spi); |
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712 | |||
713 | @@ -952,8 +959,8 @@ static int lantiq_ssc_remove(struct plat |
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714 | { |
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715 | struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev); |
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716 | |||
717 | - lantiq_ssc_writel(spi, 0, SPI_IRNEN); |
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718 | - lantiq_ssc_writel(spi, 0, SPI_CLC); |
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719 | + lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN); |
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720 | + lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC); |
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721 | rx_fifo_flush(spi); |
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722 | tx_fifo_flush(spi); |
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723 | hw_enter_config_mode(spi); |