OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001 |
2 | From: Hauke Mehrtens <hauke@hauke-m.de> |
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3 | Date: Fri, 6 Jan 2017 17:55:24 +0100 |
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4 | Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs |
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5 | |||
6 | The size of the internal RAM of the DesignWare USB controller changed |
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7 | between the different Lantiq SoCs. We have the following sizes: |
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8 | |||
9 | Amazon + Danube: 8 KByte |
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10 | Amazon SE + arx100: 2 KByte |
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11 | xrx200 + xrx300: 2.5 KByte |
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12 | |||
13 | For Danube SoC we do not provide the params and let the driver decide |
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14 | to use sane defaults, for the Amazon SE and arx100 we use small fifos |
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15 | and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo. |
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16 | The auto detection of max_transfer_size and max_packet_count should |
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17 | work, so remove it. |
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18 | |||
19 | Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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20 | --- |
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21 | drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++------- |
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22 | 1 file changed, 39 insertions(+), 7 deletions(-) |
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23 | |||
24 | --- a/drivers/usb/dwc2/platform.c |
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25 | +++ b/drivers/usb/dwc2/platform.c |
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26 | @@ -151,7 +151,38 @@ static const struct dwc2_core_params par |
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27 | .hibernation = -1, |
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28 | }; |
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29 | |||
30 | -static const struct dwc2_core_params params_ltq = { |
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31 | +static const struct dwc2_core_params params_danube = { |
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32 | + .otg_cap = 2, /* non-HNP/non-SRP */ |
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33 | + .otg_ver = -1, |
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34 | + .dma_enable = -1, |
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35 | + .dma_desc_enable = -1, |
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36 | + .dma_desc_fs_enable = -1, |
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37 | + .speed = -1, |
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38 | + .enable_dynamic_fifo = -1, |
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39 | + .en_multiple_tx_fifo = -1, |
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40 | + .host_rx_fifo_size = -1, |
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41 | + .host_nperio_tx_fifo_size = -1, |
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42 | + .host_perio_tx_fifo_size = -1, |
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43 | + .max_transfer_size = -1, |
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44 | + .max_packet_count = -1, |
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45 | + .host_channels = -1, |
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46 | + .phy_type = -1, |
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47 | + .phy_utmi_width = -1, |
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48 | + .phy_ulpi_ddr = -1, |
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49 | + .phy_ulpi_ext_vbus = -1, |
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50 | + .i2c_enable = -1, |
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51 | + .ulpi_fs_ls = -1, |
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52 | + .host_support_fs_ls_low_power = -1, |
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53 | + .host_ls_low_power_phy_clk = -1, |
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54 | + .ts_dline = -1, |
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55 | + .reload_ctl = -1, |
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56 | + .ahbcfg = -1, |
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57 | + .uframe_sched = -1, |
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58 | + .external_id_pin_ctl = -1, |
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59 | + .hibernation = -1, |
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60 | +}; |
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61 | + |
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62 | +static const struct dwc2_core_params params_ase = { |
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63 | .otg_cap = 2, /* non-HNP/non-SRP */ |
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64 | .otg_ver = -1, |
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65 | .dma_enable = -1, |
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66 | @@ -163,8 +194,8 @@ static const struct dwc2_core_params par |
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67 | .host_rx_fifo_size = 288, /* 288 DWORDs */ |
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68 | .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ |
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69 | .host_perio_tx_fifo_size = 96, /* 96 DWORDs */ |
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70 | - .max_transfer_size = 65535, |
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71 | - .max_packet_count = 511, |
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72 | + .max_transfer_size = -1, |
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73 | + .max_packet_count = -1, |
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74 | .host_channels = -1, |
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75 | .phy_type = -1, |
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76 | .phy_utmi_width = -1, |
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77 | @@ -176,8 +207,37 @@ static const struct dwc2_core_params par |
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78 | .host_ls_low_power_phy_clk = -1, |
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79 | .ts_dline = -1, |
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80 | .reload_ctl = -1, |
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81 | - .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << |
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82 | - GAHBCFG_HBSTLEN_SHIFT, |
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83 | + .ahbcfg = -1, |
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84 | + .uframe_sched = -1, |
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85 | + .external_id_pin_ctl = -1, |
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86 | + .hibernation = -1, |
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87 | +}; |
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88 | + |
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89 | +static const struct dwc2_core_params params_xrx200 = { |
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90 | + .otg_cap = 2, /* non-HNP/non-SRP */ |
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91 | + .otg_ver = -1, |
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92 | + .dma_enable = -1, |
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93 | + .dma_desc_enable = -1, |
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94 | + .speed = -1, |
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95 | + .enable_dynamic_fifo = -1, |
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96 | + .en_multiple_tx_fifo = -1, |
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97 | + .host_rx_fifo_size = 288, /* 288 DWORDs */ |
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98 | + .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ |
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99 | + .host_perio_tx_fifo_size = 136, /* 136 DWORDs */ |
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100 | + .max_transfer_size = -1, |
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101 | + .max_packet_count = -1, |
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102 | + .host_channels = -1, |
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103 | + .phy_type = -1, |
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104 | + .phy_utmi_width = -1, |
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105 | + .phy_ulpi_ddr = -1, |
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106 | + .phy_ulpi_ext_vbus = -1, |
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107 | + .i2c_enable = -1, |
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108 | + .ulpi_fs_ls = -1, |
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109 | + .host_support_fs_ls_low_power = -1, |
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110 | + .host_ls_low_power_phy_clk = -1, |
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111 | + .ts_dline = -1, |
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112 | + .reload_ctl = -1, |
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113 | + .ahbcfg = -1, |
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114 | .uframe_sched = -1, |
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115 | .external_id_pin_ctl = -1, |
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116 | .hibernation = -1, |
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117 | @@ -515,8 +575,11 @@ static const struct of_device_id dwc2_of |
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118 | { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 }, |
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119 | { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 }, |
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120 | { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 }, |
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121 | - { .compatible = "lantiq,arx100-usb", .data = ¶ms_ltq }, |
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122 | - { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq }, |
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123 | + { .compatible = "lantiq,danube-usb", .data = ¶ms_danube }, |
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124 | + { .compatible = "lantiq,ase-usb", .data = ¶ms_ase }, |
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125 | + { .compatible = "lantiq,arx100-usb", .data = ¶ms_ase }, |
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126 | + { .compatible = "lantiq,xrx200-usb", .data = ¶ms_xrx200 }, |
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127 | + { .compatible = "lantiq,xrx300-usb", .data = ¶ms_xrx200 }, |
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128 | { .compatible = "snps,dwc2", .data = NULL }, |
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129 | { .compatible = "samsung,s3c6400-hsotg", .data = NULL}, |
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130 | { .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic }, |