OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From fb0c9601f4414c39ff68e26b88681bef0bb04954 Mon Sep 17 00:00:00 2001 |
2 | From: John Crispin <blogic@openwrt.org> |
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3 | Date: Mon, 22 Oct 2012 12:22:23 +0200 |
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4 | Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net |
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5 | |||
6 | --- |
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7 | drivers/net/ethernet/Kconfig | 8 +- |
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8 | drivers/net/ethernet/Makefile | 1 + |
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9 | drivers/net/ethernet/lantiq_pce.h | 163 +++ |
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10 | drivers/net/ethernet/lantiq_xrx200.c | 1798 +++++++++++++++++++++++++++++++ |
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11 | drivers/net/ethernet/lantiq_xrx200_sw.h | 1328 +++++++++++++++++++++++ |
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12 | 5 files changed, 3297 insertions(+), 1 deletion(-) |
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13 | create mode 100644 drivers/net/ethernet/lantiq_pce.h |
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14 | create mode 100644 drivers/net/ethernet/lantiq_xrx200.c |
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15 | create mode 100644 drivers/net/ethernet/lantiq_xrx200_sw.h |
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16 | |||
17 | --- a/drivers/net/ethernet/Kconfig |
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18 | +++ b/drivers/net/ethernet/Kconfig |
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19 | @@ -104,7 +104,13 @@ config LANTIQ_ETOP |
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20 | tristate "Lantiq SoC ETOP driver" |
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21 | depends on SOC_TYPE_XWAY |
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22 | ---help--- |
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23 | - Support for the MII0 inside the Lantiq SoC |
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24 | + Support for the MII0 inside the Lantiq ADSL SoC |
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25 | + |
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26 | +config LANTIQ_XRX200 |
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27 | + tristate "Lantiq SoC XRX200 driver" |
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28 | + depends on SOC_TYPE_XWAY |
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29 | + ---help--- |
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30 | + Support for the MII0 inside the Lantiq VDSL SoC |
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31 | |||
32 | source "drivers/net/ethernet/marvell/Kconfig" |
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33 | source "drivers/net/ethernet/mediatek/Kconfig" |
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34 | --- a/drivers/net/ethernet/Makefile |
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35 | +++ b/drivers/net/ethernet/Makefile |
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36 | @@ -46,6 +46,7 @@ obj-$(CONFIG_NET_VENDOR_XSCALE) += xscal |
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37 | obj-$(CONFIG_JME) += jme.o |
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38 | obj-$(CONFIG_KORINA) += korina.o |
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39 | obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o |
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40 | +obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o |
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41 | obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ |
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42 | obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/ |
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43 | obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ |
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44 | --- /dev/null |
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45 | +++ b/drivers/net/ethernet/lantiq_pce.h |
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46 | @@ -0,0 +1,163 @@ |
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47 | +/* |
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48 | + * This program is free software; you can redistribute it and/or modify it |
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49 | + * under the terms of the GNU General Public License version 2 as published |
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50 | + * by the Free Software Foundation. |
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51 | + * |
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52 | + * This program is distributed in the hope that it will be useful, |
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53 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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54 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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55 | + * GNU General Public License for more details. |
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56 | + * |
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57 | + * You should have received a copy of the GNU General Public License |
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58 | + * along with this program; if not, write to the Free Software |
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59 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
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60 | + * |
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61 | + * Copyright (C) 2010 Lantiq Deutschland GmbH |
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62 | + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> |
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63 | + * |
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64 | + * PCE microcode extracted from UGW5.2 switch api |
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65 | + */ |
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66 | + |
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67 | +/* Switch API Micro Code V0.3 */ |
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68 | +enum { |
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69 | + OUT_MAC0 = 0, |
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70 | + OUT_MAC1, |
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71 | + OUT_MAC2, |
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72 | + OUT_MAC3, |
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73 | + OUT_MAC4, |
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74 | + OUT_MAC5, |
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75 | + OUT_ETHTYP, |
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76 | + OUT_VTAG0, |
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77 | + OUT_VTAG1, |
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78 | + OUT_ITAG0, |
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79 | + OUT_ITAG1, /*10 */ |
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80 | + OUT_ITAG2, |
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81 | + OUT_ITAG3, |
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82 | + OUT_IP0, |
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83 | + OUT_IP1, |
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84 | + OUT_IP2, |
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85 | + OUT_IP3, |
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86 | + OUT_SIP0, |
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87 | + OUT_SIP1, |
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88 | + OUT_SIP2, |
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89 | + OUT_SIP3, /*20*/ |
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90 | + OUT_SIP4, |
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91 | + OUT_SIP5, |
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92 | + OUT_SIP6, |
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93 | + OUT_SIP7, |
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94 | + OUT_DIP0, |
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95 | + OUT_DIP1, |
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96 | + OUT_DIP2, |
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97 | + OUT_DIP3, |
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98 | + OUT_DIP4, |
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99 | + OUT_DIP5, /*30*/ |
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100 | + OUT_DIP6, |
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101 | + OUT_DIP7, |
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102 | + OUT_SESID, |
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103 | + OUT_PROT, |
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104 | + OUT_APP0, |
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105 | + OUT_APP1, |
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106 | + OUT_IGMP0, |
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107 | + OUT_IGMP1, |
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108 | + OUT_IPOFF, /*39*/ |
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109 | + OUT_NONE = 63 |
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110 | +}; |
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111 | + |
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112 | +/* parser's microcode length type */ |
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113 | +#define INSTR 0 |
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114 | +#define IPV6 1 |
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115 | +#define LENACCU 2 |
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116 | + |
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117 | +/* parser's microcode flag type */ |
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118 | +enum { |
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119 | + FLAG_ITAG = 0, |
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120 | + FLAG_VLAN, |
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121 | + FLAG_SNAP, |
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122 | + FLAG_PPPOE, |
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123 | + FLAG_IPV6, |
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124 | + FLAG_IPV6FL, |
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125 | + FLAG_IPV4, |
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126 | + FLAG_IGMP, |
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127 | + FLAG_TU, |
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128 | + FLAG_HOP, |
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129 | + FLAG_NN1, /*10 */ |
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130 | + FLAG_NN2, |
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131 | + FLAG_END, |
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132 | + FLAG_NO, /*13*/ |
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133 | +}; |
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134 | + |
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135 | +/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */ |
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136 | +#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \ |
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137 | + { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }} |
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138 | +struct pce_microcode { |
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139 | + unsigned short val[4]; |
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140 | +/* unsigned short val_2; |
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141 | + unsigned short val_1; |
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142 | + unsigned short val_0;*/ |
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143 | +} pce_microcode[] = { |
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144 | + /* value mask ns fields L type flags ipv4_len */ |
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145 | + MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0), |
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146 | + MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), |
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147 | + MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), |
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148 | + MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), |
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149 | + MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), |
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150 | + MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), |
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151 | + MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), |
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152 | + MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), |
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153 | + MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0), |
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154 | + MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), |
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155 | + MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), |
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156 | + MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0), |
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157 | + MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0), |
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158 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), |
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159 | + MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0), |
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160 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), |
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161 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0), |
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162 | + MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0), |
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163 | + MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0), |
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164 | + MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0), |
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165 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), |
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166 | + MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1), |
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167 | + MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0), |
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168 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), |
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169 | + MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0), |
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170 | + MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0), |
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171 | + MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0), |
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172 | + MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), |
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173 | + MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), |
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174 | + MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0), |
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175 | + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0), |
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176 | + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0), |
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177 | + MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), |
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178 | + MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0), |
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179 | + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0), |
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180 | + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0), |
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181 | + MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0), |
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182 | + MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0), |
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183 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0), |
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184 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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185 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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186 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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187 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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188 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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189 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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190 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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191 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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192 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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193 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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194 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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195 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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196 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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197 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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198 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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199 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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200 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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201 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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202 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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203 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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204 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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205 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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206 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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207 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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208 | + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), |
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209 | +}; |
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210 | --- /dev/null |
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211 | +++ b/drivers/net/ethernet/lantiq_xrx200.c |
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212 | @@ -0,0 +1,1851 @@ |
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213 | +/* |
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214 | + * This program is free software; you can redistribute it and/or modify it |
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215 | + * under the terms of the GNU General Public License version 2 as published |
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216 | + * by the Free Software Foundation. |
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217 | + * |
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218 | + * This program is distributed in the hope that it will be useful, |
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219 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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220 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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221 | + * GNU General Public License for more details. |
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222 | + * |
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223 | + * You should have received a copy of the GNU General Public License |
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224 | + * along with this program; if not, write to the Free Software |
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225 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
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226 | + * |
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227 | + * Copyright (C) 2010 Lantiq Deutschland |
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228 | + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> |
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229 | + */ |
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230 | + |
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231 | +#include <linux/switch.h> |
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232 | +#include <linux/etherdevice.h> |
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233 | +#include <linux/module.h> |
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234 | +#include <linux/platform_device.h> |
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235 | +#include <linux/interrupt.h> |
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236 | +#include <linux/clk.h> |
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237 | +#include <linux/if_vlan.h> |
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238 | +#include <asm/delay.h> |
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239 | + |
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240 | +#include <linux/of_net.h> |
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241 | +#include <linux/of_mdio.h> |
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242 | +#include <linux/of_gpio.h> |
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243 | + |
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244 | +#include <xway_dma.h> |
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245 | +#include <lantiq_soc.h> |
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246 | + |
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247 | +#include "lantiq_pce.h" |
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248 | +#include "lantiq_xrx200_sw.h" |
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249 | + |
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250 | +#define SW_POLLING |
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251 | +#define SW_ROUTING |
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252 | + |
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253 | +#ifdef SW_ROUTING |
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254 | +#define XRX200_MAX_DEV 2 |
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255 | +#else |
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256 | +#define XRX200_MAX_DEV 1 |
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257 | +#endif |
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258 | + |
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259 | +#define XRX200_MAX_VLAN 64 |
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260 | +#define XRX200_PCE_ACTVLAN_IDX 0x01 |
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261 | +#define XRX200_PCE_VLANMAP_IDX 0x02 |
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262 | + |
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263 | +#define XRX200_MAX_PORT 7 |
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264 | +#define XRX200_MAX_DMA 8 |
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265 | + |
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266 | +#define XRX200_HEADROOM 4 |
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267 | + |
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268 | +#define XRX200_TX_TIMEOUT (10 * HZ) |
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269 | + |
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270 | +/* port type */ |
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271 | +#define XRX200_PORT_TYPE_PHY 1 |
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272 | +#define XRX200_PORT_TYPE_MAC 2 |
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273 | + |
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274 | +/* DMA */ |
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275 | +#define XRX200_DMA_DATA_LEN 0x600 |
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276 | +#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0 |
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277 | +#define XRX200_DMA_RX 0 |
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278 | +#define XRX200_DMA_TX 1 |
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279 | +#define XRX200_DMA_TX_2 3 |
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280 | +#define XRX200_DMA_IS_TX(x) (x%2) |
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281 | +#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x)) |
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282 | + |
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283 | +/* fetch / store dma */ |
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284 | +#define FDMA_PCTRL0 0x2A00 |
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285 | +#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18)) |
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286 | +#define SDMA_PCTRL0 0x2F00 |
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287 | +#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18)) |
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288 | + |
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289 | +/* buffer management */ |
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290 | +#define BM_PCFG0 0x200 |
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291 | +#define BM_PCFGx(x) (BM_PCFG0 + (x * 8)) |
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292 | + |
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293 | +/* MDIO */ |
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294 | +#define MDIO_GLOB 0x0000 |
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295 | +#define MDIO_CTRL 0x0020 |
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296 | +#define MDIO_READ 0x0024 |
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297 | +#define MDIO_WRITE 0x0028 |
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298 | +#define MDIO_PHY0 0x0054 |
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299 | +#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned))) |
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300 | +#define MDIO_CLK_CFG0 0x002C |
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301 | +#define MDIO_CLK_CFG1 0x0030 |
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302 | + |
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303 | +#define MDIO_GLOB_ENABLE 0x8000 |
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304 | +#define MDIO_BUSY BIT(12) |
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305 | +#define MDIO_RD BIT(11) |
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306 | +#define MDIO_WR BIT(10) |
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307 | +#define MDIO_MASK 0x1f |
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308 | +#define MDIO_ADDRSHIFT 5 |
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309 | +#define MDIO1_25MHZ 9 |
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310 | + |
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311 | +#define MDIO_PHY_LINK_DOWN 0x4000 |
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312 | +#define MDIO_PHY_LINK_UP 0x2000 |
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313 | + |
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314 | +#define MDIO_PHY_SPEED_M10 0x0000 |
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315 | +#define MDIO_PHY_SPEED_M100 0x0800 |
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316 | +#define MDIO_PHY_SPEED_G1 0x1000 |
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317 | + |
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318 | +#define MDIO_PHY_FDUP_EN 0x0200 |
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319 | +#define MDIO_PHY_FDUP_DIS 0x0600 |
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320 | + |
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321 | +#define MDIO_PHY_LINK_MASK 0x6000 |
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322 | +#define MDIO_PHY_SPEED_MASK 0x1800 |
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323 | +#define MDIO_PHY_FDUP_MASK 0x0600 |
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324 | +#define MDIO_PHY_ADDR_MASK 0x001f |
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325 | +#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \ |
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326 | + MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK |
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327 | + |
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328 | +/* MII */ |
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329 | +#define MII_CFG(p) (p * 8) |
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330 | + |
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331 | +#define MII_CFG_EN BIT(14) |
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332 | + |
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333 | +#define MII_CFG_MODE_MIIP 0x0 |
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334 | +#define MII_CFG_MODE_MIIM 0x1 |
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335 | +#define MII_CFG_MODE_RMIIP 0x2 |
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336 | +#define MII_CFG_MODE_RMIIM 0x3 |
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337 | +#define MII_CFG_MODE_RGMII 0x4 |
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338 | +#define MII_CFG_MODE_MASK 0xf |
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339 | + |
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340 | +#define MII_CFG_RATE_M2P5 0x00 |
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341 | +#define MII_CFG_RATE_M25 0x10 |
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342 | +#define MII_CFG_RATE_M125 0x20 |
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343 | +#define MII_CFG_RATE_M50 0x30 |
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344 | +#define MII_CFG_RATE_AUTO 0x40 |
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345 | +#define MII_CFG_RATE_MASK 0x70 |
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346 | + |
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347 | +/* cpu port mac */ |
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348 | +#define PMAC_HD_CTL 0x0000 |
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349 | +#define PMAC_RX_IPG 0x0024 |
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350 | +#define PMAC_EWAN 0x002c |
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351 | + |
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352 | +#define PMAC_IPG_MASK 0xf |
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353 | +#define PMAC_HD_CTL_AS 0x0008 |
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354 | +#define PMAC_HD_CTL_AC 0x0004 |
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355 | +#define PMAC_HD_CTL_RC 0x0010 |
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356 | +#define PMAC_HD_CTL_RXSH 0x0040 |
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357 | +#define PMAC_HD_CTL_AST 0x0080 |
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358 | +#define PMAC_HD_CTL_RST 0x0100 |
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359 | + |
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360 | +/* PCE */ |
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361 | +#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4)) |
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362 | +#define PCE_TBL_MASK 0x1120 |
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363 | +#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4)) |
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364 | +#define PCE_TBL_ADDR 0x1138 |
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365 | +#define PCE_TBL_CTRL 0x113c |
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366 | +#define PCE_PMAP1 0x114c |
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367 | +#define PCE_PMAP2 0x1150 |
||
368 | +#define PCE_PMAP3 0x1154 |
||
369 | +#define PCE_GCTRL_REG(x) (0x1158 + (x * 4)) |
||
370 | +#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4)) |
||
371 | + |
||
372 | +#define PCE_TBL_BUSY BIT(15) |
||
373 | +#define PCE_TBL_CFG_ADDR_MASK 0x1f |
||
374 | +#define PCE_TBL_CFG_ADWR 0x20 |
||
375 | +#define PCE_TBL_CFG_ADWR_MASK 0x60 |
||
376 | +#define PCE_INGRESS BIT(11) |
||
377 | + |
||
378 | +/* MAC */ |
||
379 | +#define MAC_FLEN_REG (0x2314) |
||
380 | +#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4)) |
||
381 | + |
||
382 | +/* buffer management */ |
||
383 | +#define BM_PCFG(p) (0x200 + (p * 8)) |
||
384 | + |
||
385 | +/* special tag in TX path header */ |
||
386 | +#define SPID_SHIFT 24 |
||
387 | +#define DPID_SHIFT 16 |
||
388 | +#define DPID_ENABLE 1 |
||
389 | +#define SPID_CPU_PORT 2 |
||
390 | +#define PORT_MAP_SEL BIT(15) |
||
391 | +#define PORT_MAP_EN BIT(14) |
||
392 | +#define PORT_MAP_SHIFT 1 |
||
393 | +#define PORT_MAP_MASK 0x3f |
||
394 | + |
||
395 | +#define SPPID_MASK 0x7 |
||
396 | +#define SPPID_SHIFT 4 |
||
397 | + |
||
398 | +/* MII regs not yet in linux */ |
||
399 | +#define MDIO_DEVAD_NONE (-1) |
||
400 | +#define ADVERTIZE_MPD (1 << 10) |
||
401 | + |
||
402 | +struct xrx200_port { |
||
403 | + u8 num; |
||
404 | + u8 phy_addr; |
||
405 | + u16 flags; |
||
406 | + phy_interface_t phy_if; |
||
407 | + |
||
408 | + int link; |
||
409 | + int gpio; |
||
410 | + enum of_gpio_flags gpio_flags; |
||
411 | + |
||
412 | + struct phy_device *phydev; |
||
413 | + struct device_node *phy_node; |
||
414 | +}; |
||
415 | + |
||
416 | +struct xrx200_chan { |
||
417 | + int idx; |
||
418 | + int refcount; |
||
419 | + int tx_free; |
||
420 | + |
||
421 | + struct net_device dummy_dev; |
||
422 | + struct net_device *devs[XRX200_MAX_DEV]; |
||
423 | + |
||
424 | + struct tasklet_struct tasklet; |
||
425 | + struct napi_struct napi; |
||
426 | + struct ltq_dma_channel dma; |
||
427 | + struct sk_buff *skb[LTQ_DESC_NUM]; |
||
428 | + |
||
429 | + spinlock_t lock; |
||
430 | +}; |
||
431 | + |
||
432 | +struct xrx200_hw { |
||
433 | + struct clk *clk; |
||
434 | + struct mii_bus *mii_bus; |
||
435 | + |
||
436 | + struct xrx200_chan chan[XRX200_MAX_DMA]; |
||
437 | + u16 vlan_vid[XRX200_MAX_VLAN]; |
||
438 | + u16 vlan_port_map[XRX200_MAX_VLAN]; |
||
439 | + |
||
440 | + struct net_device *devs[XRX200_MAX_DEV]; |
||
441 | + int num_devs; |
||
442 | + |
||
443 | + int port_map[XRX200_MAX_PORT]; |
||
444 | + unsigned short wan_map; |
||
445 | + |
||
446 | + struct switch_dev swdev; |
||
447 | +}; |
||
448 | + |
||
449 | +struct xrx200_priv { |
||
450 | + struct net_device_stats stats; |
||
451 | + int id; |
||
452 | + |
||
453 | + struct xrx200_port port[XRX200_MAX_PORT]; |
||
454 | + int num_port; |
||
455 | + bool wan; |
||
456 | + bool sw; |
||
457 | + unsigned short port_map; |
||
458 | + unsigned char mac[6]; |
||
459 | + |
||
460 | + struct xrx200_hw *hw; |
||
461 | +}; |
||
462 | + |
||
463 | +static __iomem void *xrx200_switch_membase; |
||
464 | +static __iomem void *xrx200_mii_membase; |
||
465 | +static __iomem void *xrx200_mdio_membase; |
||
466 | +static __iomem void *xrx200_pmac_membase; |
||
467 | + |
||
468 | +#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x)) |
||
469 | +#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y)) |
||
470 | +#define ltq_switch_w32_mask(x, y, z) \ |
||
471 | + ltq_w32_mask(x, y, xrx200_switch_membase + (z)) |
||
472 | + |
||
473 | +#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x)) |
||
474 | +#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y)) |
||
475 | +#define ltq_mdio_w32_mask(x, y, z) \ |
||
476 | + ltq_w32_mask(x, y, xrx200_mdio_membase + (z)) |
||
477 | + |
||
478 | +#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x)) |
||
479 | +#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y)) |
||
480 | +#define ltq_mii_w32_mask(x, y, z) \ |
||
481 | + ltq_w32_mask(x, y, xrx200_mii_membase + (z)) |
||
482 | + |
||
483 | +#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x)) |
||
484 | +#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y)) |
||
485 | +#define ltq_pmac_w32_mask(x, y, z) \ |
||
486 | + ltq_w32_mask(x, y, xrx200_pmac_membase + (z)) |
||
487 | + |
||
488 | +#define XRX200_GLOBAL_REGATTR(reg) \ |
||
489 | + .id = reg, \ |
||
490 | + .type = SWITCH_TYPE_INT, \ |
||
491 | + .set = xrx200_set_global_attr, \ |
||
492 | + .get = xrx200_get_global_attr |
||
493 | + |
||
494 | +#define XRX200_PORT_REGATTR(reg) \ |
||
495 | + .id = reg, \ |
||
496 | + .type = SWITCH_TYPE_INT, \ |
||
497 | + .set = xrx200_set_port_attr, \ |
||
498 | + .get = xrx200_get_port_attr |
||
499 | + |
||
500 | +static int xrx200sw_read_x(int reg, int x) |
||
501 | +{ |
||
502 | + int value, mask, addr; |
||
503 | + |
||
504 | + addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); |
||
505 | + value = ltq_switch_r32(addr); |
||
506 | + mask = (1 << xrx200sw_reg[reg].size) - 1; |
||
507 | + value = (value >> xrx200sw_reg[reg].shift); |
||
508 | + |
||
509 | + return (value & mask); |
||
510 | +} |
||
511 | + |
||
512 | +static int xrx200sw_read(int reg) |
||
513 | +{ |
||
514 | + return xrx200sw_read_x(reg, 0); |
||
515 | +} |
||
516 | + |
||
517 | +static void xrx200sw_write_x(int value, int reg, int x) |
||
518 | +{ |
||
519 | + int mask, addr; |
||
520 | + |
||
521 | + addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); |
||
522 | + mask = (1 << xrx200sw_reg[reg].size) - 1; |
||
523 | + mask = (mask << xrx200sw_reg[reg].shift); |
||
524 | + value = (value << xrx200sw_reg[reg].shift) & mask; |
||
525 | + |
||
526 | + ltq_switch_w32_mask(mask, value, addr); |
||
527 | +} |
||
528 | + |
||
529 | +static void xrx200sw_write(int value, int reg) |
||
530 | +{ |
||
531 | + xrx200sw_write_x(value, reg, 0); |
||
532 | +} |
||
533 | + |
||
534 | +struct xrx200_pce_table_entry { |
||
535 | + int index; // PCE_TBL_ADDR.ADDR = pData->table_index |
||
536 | + int table; // PCE_TBL_CTRL.ADDR = pData->table |
||
537 | + unsigned short key[8]; |
||
538 | + unsigned short val[5]; |
||
539 | + unsigned short mask; |
||
540 | + unsigned short type; |
||
541 | + unsigned short valid; |
||
542 | + unsigned short gmap; |
||
543 | +}; |
||
544 | + |
||
545 | +static int xrx200_pce_table_entry_read(struct xrx200_pce_table_entry *tbl) |
||
546 | +{ |
||
547 | + // wait until hardware is ready |
||
548 | + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; |
||
549 | + |
||
550 | + // prepare the table access: |
||
551 | + // PCE_TBL_ADDR.ADDR = pData->table_index |
||
552 | + xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); |
||
553 | + // PCE_TBL_CTRL.ADDR = pData->table |
||
554 | + xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); |
||
555 | + |
||
556 | + //(address-based read) |
||
557 | + xrx200sw_write(0, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD |
||
558 | + |
||
559 | + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access |
||
560 | + |
||
561 | + // wait until hardware is ready |
||
562 | + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; |
||
563 | + |
||
564 | + // read the keys |
||
565 | + tbl->key[7] = xrx200sw_read(XRX200_PCE_TBL_KEY_7); |
||
566 | + tbl->key[6] = xrx200sw_read(XRX200_PCE_TBL_KEY_6); |
||
567 | + tbl->key[5] = xrx200sw_read(XRX200_PCE_TBL_KEY_5); |
||
568 | + tbl->key[4] = xrx200sw_read(XRX200_PCE_TBL_KEY_4); |
||
569 | + tbl->key[3] = xrx200sw_read(XRX200_PCE_TBL_KEY_3); |
||
570 | + tbl->key[2] = xrx200sw_read(XRX200_PCE_TBL_KEY_2); |
||
571 | + tbl->key[1] = xrx200sw_read(XRX200_PCE_TBL_KEY_1); |
||
572 | + tbl->key[0] = xrx200sw_read(XRX200_PCE_TBL_KEY_0); |
||
573 | + |
||
574 | + // read the values |
||
575 | + tbl->val[4] = xrx200sw_read(XRX200_PCE_TBL_VAL_4); |
||
576 | + tbl->val[3] = xrx200sw_read(XRX200_PCE_TBL_VAL_3); |
||
577 | + tbl->val[2] = xrx200sw_read(XRX200_PCE_TBL_VAL_2); |
||
578 | + tbl->val[1] = xrx200sw_read(XRX200_PCE_TBL_VAL_1); |
||
579 | + tbl->val[0] = xrx200sw_read(XRX200_PCE_TBL_VAL_0); |
||
580 | + |
||
581 | + // read the mask |
||
582 | + tbl->mask = xrx200sw_read(XRX200_PCE_TBL_MASK_0); |
||
583 | + // read the type |
||
584 | + tbl->type = xrx200sw_read(XRX200_PCE_TBL_CTRL_TYPE); |
||
585 | + // read the valid flag |
||
586 | + tbl->valid = xrx200sw_read(XRX200_PCE_TBL_CTRL_VLD); |
||
587 | + // read the group map |
||
588 | + tbl->gmap = xrx200sw_read(XRX200_PCE_TBL_CTRL_GMAP); |
||
589 | + |
||
590 | + return 0; |
||
591 | +} |
||
592 | + |
||
593 | +static int xrx200_pce_table_entry_write(struct xrx200_pce_table_entry *tbl) |
||
594 | +{ |
||
595 | + // wait until hardware is ready |
||
596 | + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; |
||
597 | + |
||
598 | + // prepare the table access: |
||
599 | + // PCE_TBL_ADDR.ADDR = pData->table_index |
||
600 | + xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); |
||
601 | + // PCE_TBL_CTRL.ADDR = pData->table |
||
602 | + xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); |
||
603 | + |
||
604 | + //(address-based write) |
||
605 | + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD |
||
606 | + |
||
607 | + // read the keys |
||
608 | + xrx200sw_write(tbl->key[7], XRX200_PCE_TBL_KEY_7); |
||
609 | + xrx200sw_write(tbl->key[6], XRX200_PCE_TBL_KEY_6); |
||
610 | + xrx200sw_write(tbl->key[5], XRX200_PCE_TBL_KEY_5); |
||
611 | + xrx200sw_write(tbl->key[4], XRX200_PCE_TBL_KEY_4); |
||
612 | + xrx200sw_write(tbl->key[3], XRX200_PCE_TBL_KEY_3); |
||
613 | + xrx200sw_write(tbl->key[2], XRX200_PCE_TBL_KEY_2); |
||
614 | + xrx200sw_write(tbl->key[1], XRX200_PCE_TBL_KEY_1); |
||
615 | + xrx200sw_write(tbl->key[0], XRX200_PCE_TBL_KEY_0); |
||
616 | + |
||
617 | + // read the values |
||
618 | + xrx200sw_write(tbl->val[4], XRX200_PCE_TBL_VAL_4); |
||
619 | + xrx200sw_write(tbl->val[3], XRX200_PCE_TBL_VAL_3); |
||
620 | + xrx200sw_write(tbl->val[2], XRX200_PCE_TBL_VAL_2); |
||
621 | + xrx200sw_write(tbl->val[1], XRX200_PCE_TBL_VAL_1); |
||
622 | + xrx200sw_write(tbl->val[0], XRX200_PCE_TBL_VAL_0); |
||
623 | + |
||
624 | + // read the mask |
||
625 | + xrx200sw_write(tbl->mask, XRX200_PCE_TBL_MASK_0); |
||
626 | + // read the type |
||
627 | + xrx200sw_write(tbl->type, XRX200_PCE_TBL_CTRL_TYPE); |
||
628 | + // read the valid flag |
||
629 | + xrx200sw_write(tbl->valid, XRX200_PCE_TBL_CTRL_VLD); |
||
630 | + // read the group map |
||
631 | + xrx200sw_write(tbl->gmap, XRX200_PCE_TBL_CTRL_GMAP); |
||
632 | + |
||
633 | + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access |
||
634 | + |
||
635 | + // wait until hardware is ready |
||
636 | + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; |
||
637 | + |
||
638 | + return 0; |
||
639 | +} |
||
640 | + |
||
641 | +static void xrx200sw_fixup_pvids(void) |
||
642 | +{ |
||
643 | + int index, p, portmap, untagged; |
||
644 | + struct xrx200_pce_table_entry tem; |
||
645 | + struct xrx200_pce_table_entry tev; |
||
646 | + |
||
647 | + portmap = 0; |
||
648 | + for (p = 0; p < XRX200_MAX_PORT; p++) |
||
649 | + portmap |= BIT(p); |
||
650 | + |
||
651 | + tem.table = XRX200_PCE_VLANMAP_IDX; |
||
652 | + tev.table = XRX200_PCE_ACTVLAN_IDX; |
||
653 | + |
||
654 | + for (index = XRX200_MAX_VLAN; index-- > 0;) |
||
655 | + { |
||
656 | + tev.index = index; |
||
657 | + xrx200_pce_table_entry_read(&tev); |
||
658 | + |
||
659 | + if (tev.valid == 0) |
||
660 | + continue; |
||
661 | + |
||
662 | + tem.index = index; |
||
663 | + xrx200_pce_table_entry_read(&tem); |
||
664 | + |
||
665 | + if (tem.val[0] == 0) |
||
666 | + continue; |
||
667 | + |
||
668 | + untagged = portmap & (tem.val[1] ^ tem.val[2]); |
||
669 | + |
||
670 | + for (p = 0; p < XRX200_MAX_PORT; p++) |
||
671 | + if (untagged & BIT(p)) |
||
672 | + { |
||
673 | + portmap &= ~BIT(p); |
||
674 | + xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); |
||
675 | + } |
||
676 | + |
||
677 | + for (p = 0; p < XRX200_MAX_PORT; p++) |
||
678 | + if (portmap & BIT(p)) |
||
679 | + xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); |
||
680 | + } |
||
681 | +} |
||
682 | + |
||
683 | +// swconfig interface |
||
684 | +static void xrx200_hw_init(struct xrx200_hw *hw); |
||
685 | + |
||
686 | +// global |
||
687 | +static int xrx200sw_reset_switch(struct switch_dev *dev) |
||
688 | +{ |
||
689 | + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); |
||
690 | + |
||
691 | + xrx200_hw_init(hw); |
||
692 | + |
||
693 | + return 0; |
||
694 | +} |
||
695 | + |
||
696 | +static int xrx200_set_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) |
||
697 | +{ |
||
698 | + int p; |
||
699 | + |
||
700 | + if ((attr->max > 0) && (val->value.i > attr->max)) |
||
701 | + return -EINVAL; |
||
702 | + |
||
703 | + for (p = 0; p < XRX200_MAX_PORT; p++) { |
||
704 | + xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VEMR, p); |
||
705 | + xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VIMR, p); |
||
706 | + } |
||
707 | + |
||
708 | + xrx200sw_write(val->value.i, XRX200_PCE_GCTRL_0_VLAN); |
||
709 | + return 0; |
||
710 | +} |
||
711 | + |
||
712 | +static int xrx200_get_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) |
||
713 | +{ |
||
714 | + val->value.i = xrx200sw_read(attr->id); |
||
715 | + return 0; |
||
716 | +} |
||
717 | + |
||
718 | +static int xrx200_set_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) |
||
719 | +{ |
||
720 | + if ((attr->max > 0) && (val->value.i > attr->max)) |
||
721 | + return -EINVAL; |
||
722 | + |
||
723 | + xrx200sw_write(val->value.i, attr->id); |
||
724 | + return 0; |
||
725 | +} |
||
726 | + |
||
727 | +static int xrx200_get_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) |
||
728 | +{ |
||
729 | + val->value.i = xrx200sw_read(attr->id); |
||
730 | + return 0; |
||
731 | +} |
||
732 | + |
||
733 | +// vlan |
||
734 | +static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, |
||
735 | + struct switch_val *val) |
||
736 | +{ |
||
737 | + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); |
||
738 | + int i; |
||
739 | + struct xrx200_pce_table_entry tev; |
||
740 | + struct xrx200_pce_table_entry tem; |
||
741 | + |
||
742 | + tev.table = XRX200_PCE_ACTVLAN_IDX; |
||
743 | + |
||
744 | + for (i = 0; i < XRX200_MAX_VLAN; i++) |
||
745 | + { |
||
746 | + tev.index = i; |
||
747 | + xrx200_pce_table_entry_read(&tev); |
||
748 | + if (tev.key[0] == val->value.i && i != val->port_vlan) |
||
749 | + return -EINVAL; |
||
750 | + } |
||
751 | + |
||
752 | + hw->vlan_vid[val->port_vlan] = val->value.i; |
||
753 | + |
||
754 | + tev.index = val->port_vlan; |
||
755 | + xrx200_pce_table_entry_read(&tev); |
||
756 | + tev.key[0] = val->value.i; |
||
757 | + tev.valid = val->value.i > 0; |
||
758 | + xrx200_pce_table_entry_write(&tev); |
||
759 | + |
||
760 | + tem.table = XRX200_PCE_VLANMAP_IDX; |
||
761 | + tem.index = val->port_vlan; |
||
762 | + xrx200_pce_table_entry_read(&tem); |
||
763 | + tem.val[0] = val->value.i; |
||
764 | + xrx200_pce_table_entry_write(&tem); |
||
765 | + |
||
766 | + xrx200sw_fixup_pvids(); |
||
767 | + return 0; |
||
768 | +} |
||
769 | + |
||
770 | +static int xrx200sw_get_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, |
||
771 | + struct switch_val *val) |
||
772 | +{ |
||
773 | + struct xrx200_pce_table_entry te; |
||
774 | + |
||
775 | + te.table = XRX200_PCE_ACTVLAN_IDX; |
||
776 | + te.index = val->port_vlan; |
||
777 | + xrx200_pce_table_entry_read(&te); |
||
778 | + val->value.i = te.key[0]; |
||
779 | + |
||
780 | + return 0; |
||
781 | +} |
||
782 | + |
||
783 | +static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) |
||
784 | +{ |
||
785 | + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); |
||
786 | + int i, portmap, tagmap, untagged; |
||
787 | + struct xrx200_pce_table_entry tem; |
||
788 | + |
||
789 | + portmap = 0; |
||
790 | + tagmap = 0; |
||
791 | + for (i = 0; i < val->len; i++) |
||
792 | + { |
||
793 | + struct switch_port *p = &val->value.ports[i]; |
||
794 | + |
||
795 | + portmap |= (1 << p->id); |
||
796 | + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) |
||
797 | + tagmap |= (1 << p->id); |
||
798 | + } |
||
799 | + |
||
800 | + tem.table = XRX200_PCE_VLANMAP_IDX; |
||
801 | + |
||
802 | + untagged = portmap ^ tagmap; |
||
803 | + for (i = 0; i < XRX200_MAX_VLAN; i++) |
||
804 | + { |
||
805 | + tem.index = i; |
||
806 | + xrx200_pce_table_entry_read(&tem); |
||
807 | + |
||
808 | + if (tem.val[0] == 0) |
||
809 | + continue; |
||
810 | + |
||
811 | + if ((untagged & (tem.val[1] ^ tem.val[2])) && (val->port_vlan != i)) |
||
812 | + return -EINVAL; |
||
813 | + } |
||
814 | + |
||
815 | + tem.index = val->port_vlan; |
||
816 | + xrx200_pce_table_entry_read(&tem); |
||
817 | + |
||
818 | + // auto-enable this vlan if not enabled already |
||
819 | + if (tem.val[0] == 0) |
||
820 | + { |
||
821 | + struct switch_val v; |
||
822 | + v.port_vlan = val->port_vlan; |
||
823 | + v.value.i = val->port_vlan; |
||
824 | + if(xrx200sw_set_vlan_vid(dev, NULL, &v)) |
||
825 | + return -EINVAL; |
||
826 | + |
||
827 | + //read updated tem |
||
828 | + tem.index = val->port_vlan; |
||
829 | + xrx200_pce_table_entry_read(&tem); |
||
830 | + } |
||
831 | + |
||
832 | + tem.val[1] = portmap; |
||
833 | + tem.val[2] = tagmap; |
||
834 | + xrx200_pce_table_entry_write(&tem); |
||
835 | + |
||
836 | + ltq_switch_w32_mask(0, portmap, PCE_PMAP2); |
||
837 | + ltq_switch_w32_mask(0, portmap, PCE_PMAP3); |
||
838 | + hw->vlan_port_map[val->port_vlan] = portmap; |
||
839 | + |
||
840 | + xrx200sw_fixup_pvids(); |
||
841 | + |
||
842 | + return 0; |
||
843 | +} |
||
844 | + |
||
845 | +static int xrx200sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) |
||
846 | +{ |
||
847 | + int i; |
||
848 | + unsigned short ports, tags; |
||
849 | + struct xrx200_pce_table_entry tem; |
||
850 | + |
||
851 | + tem.table = XRX200_PCE_VLANMAP_IDX; |
||
852 | + tem.index = val->port_vlan; |
||
853 | + xrx200_pce_table_entry_read(&tem); |
||
854 | + |
||
855 | + ports = tem.val[1]; |
||
856 | + tags = tem.val[2]; |
||
857 | + |
||
858 | + for (i = 0; i < XRX200_MAX_PORT; i++) { |
||
859 | + struct switch_port *p; |
||
860 | + |
||
861 | + if (!(ports & (1 << i))) |
||
862 | + continue; |
||
863 | + |
||
864 | + p = &val->value.ports[val->len++]; |
||
865 | + p->id = i; |
||
866 | + if (tags & (1 << i)) |
||
867 | + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); |
||
868 | + else |
||
869 | + p->flags = 0; |
||
870 | + } |
||
871 | + |
||
872 | + return 0; |
||
873 | +} |
||
874 | + |
||
875 | +static int xrx200sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, |
||
876 | + struct switch_val *val) |
||
877 | +{ |
||
878 | + struct xrx200_pce_table_entry tev; |
||
879 | + |
||
880 | + tev.table = XRX200_PCE_ACTVLAN_IDX; |
||
881 | + tev.index = val->port_vlan; |
||
882 | + xrx200_pce_table_entry_read(&tev); |
||
883 | + |
||
884 | + if (tev.key[0] == 0) |
||
885 | + return -EINVAL; |
||
886 | + |
||
887 | + tev.valid = val->value.i; |
||
888 | + xrx200_pce_table_entry_write(&tev); |
||
889 | + |
||
890 | + xrx200sw_fixup_pvids(); |
||
891 | + return 0; |
||
892 | +} |
||
893 | + |
||
894 | +static int xrx200sw_get_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, |
||
895 | + struct switch_val *val) |
||
896 | +{ |
||
897 | + struct xrx200_pce_table_entry tev; |
||
898 | + |
||
899 | + tev.table = XRX200_PCE_ACTVLAN_IDX; |
||
900 | + tev.index = val->port_vlan; |
||
901 | + xrx200_pce_table_entry_read(&tev); |
||
902 | + val->value.i = tev.valid; |
||
903 | + |
||
904 | + return 0; |
||
905 | +} |
||
906 | + |
||
907 | +// port |
||
908 | +static int xrx200sw_get_port_pvid(struct switch_dev *dev, int port, int *val) |
||
909 | +{ |
||
910 | + struct xrx200_pce_table_entry tev; |
||
911 | + |
||
912 | + if (port >= XRX200_MAX_PORT) |
||
913 | + return -EINVAL; |
||
914 | + |
||
915 | + tev.table = XRX200_PCE_ACTVLAN_IDX; |
||
916 | + tev.index = xrx200sw_read_x(XRX200_PCE_DEFPVID_PVID, port); |
||
917 | + xrx200_pce_table_entry_read(&tev); |
||
918 | + |
||
919 | + *val = tev.key[0]; |
||
920 | + return 0; |
||
921 | +} |
||
922 | + |
||
923 | +static int xrx200sw_get_port_link(struct switch_dev *dev, |
||
924 | + int port, |
||
925 | + struct switch_port_link *link) |
||
926 | +{ |
||
927 | + if (port >= XRX200_MAX_PORT) |
||
928 | + return -EINVAL; |
||
929 | + |
||
930 | + link->link = xrx200sw_read_x(XRX200_MAC_PSTAT_LSTAT, port); |
||
931 | + if (!link->link) |
||
932 | + return 0; |
||
933 | + |
||
934 | + link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port); |
||
935 | + |
||
936 | + link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010); |
||
937 | + link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020); |
||
938 | + link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port)); |
||
939 | + |
||
940 | + link->speed = SWITCH_PORT_SPEED_10; |
||
941 | + if (xrx200sw_read_x(XRX200_MAC_PSTAT_MBIT, port)) |
||
942 | + link->speed = SWITCH_PORT_SPEED_100; |
||
943 | + if (xrx200sw_read_x(XRX200_MAC_PSTAT_GBIT, port)) |
||
944 | + link->speed = SWITCH_PORT_SPEED_1000; |
||
945 | + |
||
946 | + return 0; |
||
947 | +} |
||
948 | + |
||
949 | +static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) |
||
950 | +{ |
||
951 | + if (val->port_vlan >= XRX200_MAX_PORT) |
||
952 | + return -EINVAL; |
||
953 | + |
||
954 | + if ((attr->max > 0) && (val->value.i > attr->max)) |
||
955 | + return -EINVAL; |
||
956 | + |
||
957 | + xrx200sw_write_x(val->value.i, attr->id, val->port_vlan); |
||
958 | + return 0; |
||
959 | +} |
||
960 | + |
||
961 | +static int xrx200_get_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) |
||
962 | +{ |
||
963 | + if (val->port_vlan >= XRX200_MAX_PORT) |
||
964 | + return -EINVAL; |
||
965 | + |
||
966 | + val->value.i = xrx200sw_read_x(attr->id, val->port_vlan); |
||
967 | + return 0; |
||
968 | +} |
||
969 | + |
||
970 | +// attributes |
||
971 | +static struct switch_attr xrx200sw_globals[] = { |
||
972 | + { |
||
973 | + .type = SWITCH_TYPE_INT, |
||
974 | + .set = xrx200_set_vlan_mode_enable, |
||
975 | + .get = xrx200_get_vlan_mode_enable, |
||
976 | + .name = "enable_vlan", |
||
977 | + .description = "Enable VLAN mode", |
||
978 | + .max = 1}, |
||
979 | +}; |
||
980 | + |
||
981 | +static struct switch_attr xrx200sw_port[] = { |
||
982 | + { |
||
983 | + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_UVR), |
||
984 | + .name = "uvr", |
||
985 | + .description = "Unknown VLAN Rule", |
||
986 | + .max = 1, |
||
987 | + }, |
||
988 | + { |
||
989 | + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VSR), |
||
990 | + .name = "vsr", |
||
991 | + .description = "VLAN Security Rule", |
||
992 | + .max = 1, |
||
993 | + }, |
||
994 | + { |
||
995 | + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VINR), |
||
996 | + .name = "vinr", |
||
997 | + .description = "VLAN Ingress Tag Rule", |
||
998 | + .max = 2, |
||
999 | + }, |
||
1000 | + { |
||
1001 | + XRX200_PORT_REGATTR(XRX200_PCE_PCTRL_0_TVM), |
||
1002 | + .name = "tvm", |
||
1003 | + .description = "Transparent VLAN Mode", |
||
1004 | + .max = 1, |
||
1005 | + }, |
||
1006 | +}; |
||
1007 | + |
||
1008 | +static struct switch_attr xrx200sw_vlan[] = { |
||
1009 | + { |
||
1010 | + .type = SWITCH_TYPE_INT, |
||
1011 | + .name = "vid", |
||
1012 | + .description = "VLAN ID (0-4094)", |
||
1013 | + .set = xrx200sw_set_vlan_vid, |
||
1014 | + .get = xrx200sw_get_vlan_vid, |
||
1015 | + .max = 4094, |
||
1016 | + }, |
||
1017 | + { |
||
1018 | + .type = SWITCH_TYPE_INT, |
||
1019 | + .name = "enable", |
||
1020 | + .description = "Enable VLAN", |
||
1021 | + .set = xrx200sw_set_vlan_enable, |
||
1022 | + .get = xrx200sw_get_vlan_enable, |
||
1023 | + .max = 1, |
||
1024 | + }, |
||
1025 | +}; |
||
1026 | + |
||
1027 | +static const struct switch_dev_ops xrx200sw_ops = { |
||
1028 | + .attr_global = { |
||
1029 | + .attr = xrx200sw_globals, |
||
1030 | + .n_attr = ARRAY_SIZE(xrx200sw_globals), |
||
1031 | + }, |
||
1032 | + .attr_port = { |
||
1033 | + .attr = xrx200sw_port, |
||
1034 | + .n_attr = ARRAY_SIZE(xrx200sw_port), |
||
1035 | + }, |
||
1036 | + .attr_vlan = { |
||
1037 | + .attr = xrx200sw_vlan, |
||
1038 | + .n_attr = ARRAY_SIZE(xrx200sw_vlan), |
||
1039 | + }, |
||
1040 | + .get_vlan_ports = xrx200sw_get_vlan_ports, |
||
1041 | + .set_vlan_ports = xrx200sw_set_vlan_ports, |
||
1042 | + .get_port_pvid = xrx200sw_get_port_pvid, |
||
1043 | + .reset_switch = xrx200sw_reset_switch, |
||
1044 | + .get_port_link = xrx200sw_get_port_link, |
||
1045 | +// .get_port_stats = xrx200sw_get_port_stats, //TODO |
||
1046 | +}; |
||
1047 | + |
||
1048 | +static int xrx200sw_init(struct xrx200_hw *hw) |
||
1049 | +{ |
||
1050 | + int netdev_num; |
||
1051 | + |
||
1052 | + for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++) |
||
1053 | + { |
||
1054 | + struct switch_dev *swdev; |
||
1055 | + struct net_device *dev = hw->devs[netdev_num]; |
||
1056 | + struct xrx200_priv *priv = netdev_priv(dev); |
||
1057 | + if (!priv->sw) |
||
1058 | + continue; |
||
1059 | + |
||
1060 | + swdev = &hw->swdev; |
||
1061 | + |
||
1062 | + swdev->name = "Lantiq XRX200 Switch"; |
||
1063 | + swdev->vlans = XRX200_MAX_VLAN; |
||
1064 | + swdev->ports = XRX200_MAX_PORT; |
||
1065 | + swdev->cpu_port = 6; |
||
1066 | + swdev->ops = &xrx200sw_ops; |
||
1067 | + |
||
1068 | + register_switch(swdev, dev); |
||
1069 | + return 0; // enough switches |
||
1070 | + } |
||
1071 | + return 0; |
||
1072 | +} |
||
1073 | + |
||
1074 | +static int xrx200_open(struct net_device *dev) |
||
1075 | +{ |
||
1076 | + struct xrx200_priv *priv = netdev_priv(dev); |
||
1077 | + int i; |
||
1078 | + |
||
1079 | + for (i = 0; i < XRX200_MAX_DMA; i++) { |
||
1080 | + if (!priv->hw->chan[i].dma.irq) |
||
1081 | + continue; |
||
1082 | + spin_lock_bh(&priv->hw->chan[i].lock); |
||
1083 | + if (!priv->hw->chan[i].refcount) { |
||
1084 | + if (XRX200_DMA_IS_RX(i)) |
||
1085 | + napi_enable(&priv->hw->chan[i].napi); |
||
1086 | + ltq_dma_open(&priv->hw->chan[i].dma); |
||
1087 | + } |
||
1088 | + priv->hw->chan[i].refcount++; |
||
1089 | + spin_unlock_bh(&priv->hw->chan[i].lock); |
||
1090 | + } |
||
1091 | + for (i = 0; i < priv->num_port; i++) |
||
1092 | + if (priv->port[i].phydev) |
||
1093 | + phy_start(priv->port[i].phydev); |
||
1094 | + netif_wake_queue(dev); |
||
1095 | + |
||
1096 | + return 0; |
||
1097 | +} |
||
1098 | + |
||
1099 | +static int xrx200_close(struct net_device *dev) |
||
1100 | +{ |
||
1101 | + struct xrx200_priv *priv = netdev_priv(dev); |
||
1102 | + int i; |
||
1103 | + |
||
1104 | + netif_stop_queue(dev); |
||
1105 | + |
||
1106 | + for (i = 0; i < priv->num_port; i++) |
||
1107 | + if (priv->port[i].phydev) |
||
1108 | + phy_stop(priv->port[i].phydev); |
||
1109 | + |
||
1110 | + for (i = 0; i < XRX200_MAX_DMA; i++) { |
||
1111 | + if (!priv->hw->chan[i].dma.irq) |
||
1112 | + continue; |
||
1113 | + |
||
1114 | + priv->hw->chan[i].refcount--; |
||
1115 | + if (!priv->hw->chan[i].refcount) { |
||
1116 | + if (XRX200_DMA_IS_RX(i)) |
||
1117 | + napi_disable(&priv->hw->chan[i].napi); |
||
1118 | + spin_lock_bh(&priv->hw->chan[i].lock); |
||
1119 | + ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma); |
||
1120 | + spin_unlock_bh(&priv->hw->chan[i].lock); |
||
1121 | + } |
||
1122 | + } |
||
1123 | + |
||
1124 | + return 0; |
||
1125 | +} |
||
1126 | + |
||
1127 | +static int xrx200_alloc_skb(struct xrx200_chan *ch) |
||
1128 | +{ |
||
1129 | +#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD) |
||
1130 | + ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD); |
||
1131 | + if (!ch->skb[ch->dma.desc]) |
||
1132 | + goto skip; |
||
1133 | + |
||
1134 | + skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD); |
||
1135 | + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, |
||
1136 | + ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN, |
||
1137 | + DMA_FROM_DEVICE); |
||
1138 | + ch->dma.desc_base[ch->dma.desc].addr = |
||
1139 | + CPHYSADDR(ch->skb[ch->dma.desc]->data); |
||
1140 | + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); |
||
1141 | + |
||
1142 | +skip: |
||
1143 | + ch->dma.desc_base[ch->dma.desc].ctl = |
||
1144 | + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | |
||
1145 | + XRX200_DMA_DATA_LEN; |
||
1146 | + |
||
1147 | + return 0; |
||
1148 | +} |
||
1149 | + |
||
1150 | +static void xrx200_hw_receive(struct xrx200_chan *ch, int id) |
||
1151 | +{ |
||
1152 | + struct net_device *dev = ch->devs[id]; |
||
1153 | + struct xrx200_priv *priv = netdev_priv(dev); |
||
1154 | + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; |
||
1155 | + struct sk_buff *skb = ch->skb[ch->dma.desc]; |
||
1156 | + int len = (desc->ctl & LTQ_DMA_SIZE_MASK); |
||
1157 | + int ret; |
||
1158 | + |
||
1159 | + ret = xrx200_alloc_skb(ch); |
||
1160 | + |
||
1161 | + ch->dma.desc++; |
||
1162 | + ch->dma.desc %= LTQ_DESC_NUM; |
||
1163 | + |
||
1164 | + if (ret) { |
||
1165 | + netdev_err(dev, |
||
1166 | + "failed to allocate new rx buffer\n"); |
||
1167 | + return; |
||
1168 | + } |
||
1169 | + |
||
1170 | + skb_put(skb, len); |
||
1171 | +#ifdef SW_ROUTING |
||
1172 | + skb_pull(skb, 8); |
||
1173 | +#endif |
||
1174 | + skb->dev = dev; |
||
1175 | + skb->protocol = eth_type_trans(skb, dev); |
||
1176 | + netif_receive_skb(skb); |
||
1177 | + priv->stats.rx_packets++; |
||
1178 | + priv->stats.rx_bytes+=len; |
||
1179 | +} |
||
1180 | + |
||
1181 | +static int xrx200_poll_rx(struct napi_struct *napi, int budget) |
||
1182 | +{ |
||
1183 | + struct xrx200_chan *ch = container_of(napi, |
||
1184 | + struct xrx200_chan, napi); |
||
1185 | + struct xrx200_priv *priv = netdev_priv(ch->devs[0]); |
||
1186 | + int rx = 0; |
||
1187 | + int complete = 0; |
||
1188 | + |
||
1189 | + while ((rx < budget) && !complete) { |
||
1190 | + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; |
||
1191 | + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { |
||
1192 | +#ifdef SW_ROUTING |
||
1193 | + struct sk_buff *skb = ch->skb[ch->dma.desc]; |
||
1194 | + u8 *special_tag = (u8*)skb->data; |
||
1195 | + int port = (special_tag[7] >> SPPID_SHIFT) & SPPID_MASK; |
||
1196 | + xrx200_hw_receive(ch, priv->hw->port_map[port]); |
||
1197 | +#else |
||
1198 | + xrx200_hw_receive(ch, 0); |
||
1199 | +#endif |
||
1200 | + rx++; |
||
1201 | + } else { |
||
1202 | + complete = 1; |
||
1203 | + } |
||
1204 | + } |
||
1205 | + |
||
1206 | + if (complete || !rx) { |
||
1207 | + napi_complete(&ch->napi); |
||
1208 | + ltq_dma_enable_irq(&ch->dma); |
||
1209 | + } |
||
1210 | + |
||
1211 | + return rx; |
||
1212 | +} |
||
1213 | + |
||
1214 | +static void xrx200_tx_housekeeping(unsigned long ptr) |
||
1215 | +{ |
||
1216 | + struct xrx200_chan *ch = (struct xrx200_chan *) ptr; |
||
1217 | + int pkts = 0; |
||
1218 | + int i; |
||
1219 | + |
||
1220 | + spin_lock_bh(&ch->lock); |
||
1221 | + ltq_dma_ack_irq(&ch->dma); |
||
1222 | + while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { |
||
1223 | + struct sk_buff *skb = ch->skb[ch->tx_free]; |
||
1224 | + |
||
1225 | + pkts++; |
||
1226 | + ch->skb[ch->tx_free] = NULL; |
||
1227 | + dev_kfree_skb(skb); |
||
1228 | + memset(&ch->dma.desc_base[ch->tx_free], 0, |
||
1229 | + sizeof(struct ltq_dma_desc)); |
||
1230 | + ch->tx_free++; |
||
1231 | + ch->tx_free %= LTQ_DESC_NUM; |
||
1232 | + } |
||
1233 | + ltq_dma_enable_irq(&ch->dma); |
||
1234 | + spin_unlock_bh(&ch->lock); |
||
1235 | + |
||
1236 | + if (!pkts) |
||
1237 | + return; |
||
1238 | + |
||
1239 | + for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) |
||
1240 | + netif_wake_queue(ch->devs[i]); |
||
1241 | +} |
||
1242 | + |
||
1243 | +static struct net_device_stats *xrx200_get_stats (struct net_device *dev) |
||
1244 | +{ |
||
1245 | + struct xrx200_priv *priv = netdev_priv(dev); |
||
1246 | + |
||
1247 | + return &priv->stats; |
||
1248 | +} |
||
1249 | + |
||
1250 | +static void xrx200_tx_timeout(struct net_device *dev) |
||
1251 | +{ |
||
1252 | + struct xrx200_priv *priv = netdev_priv(dev); |
||
1253 | + |
||
1254 | + printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name); |
||
1255 | + |
||
1256 | + priv->stats.tx_errors++; |
||
1257 | + netif_wake_queue(dev); |
||
1258 | +} |
||
1259 | + |
||
1260 | +static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev) |
||
1261 | +{ |
||
1262 | + struct xrx200_priv *priv = netdev_priv(dev); |
||
1263 | + struct xrx200_chan *ch; |
||
1264 | + struct ltq_dma_desc *desc; |
||
1265 | + u32 byte_offset; |
||
1266 | + int ret = NETDEV_TX_OK; |
||
1267 | + int len; |
||
1268 | +#ifdef SW_ROUTING |
||
1269 | + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE; |
||
1270 | +#endif |
||
1271 | + if(priv->id) |
||
1272 | + ch = &priv->hw->chan[XRX200_DMA_TX_2]; |
||
1273 | + else |
||
1274 | + ch = &priv->hw->chan[XRX200_DMA_TX]; |
||
1275 | + |
||
1276 | + desc = &ch->dma.desc_base[ch->dma.desc]; |
||
1277 | + |
||
1278 | + skb->dev = dev; |
||
1279 | + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; |
||
1280 | + |
||
1281 | +#ifdef SW_ROUTING |
||
1282 | + if (is_multicast_ether_addr(eth_hdr(skb)->h_dest)) { |
||
1283 | + u16 port_map = priv->port_map; |
||
1284 | + |
||
1285 | + if (priv->sw && skb->protocol == htons(ETH_P_8021Q)) { |
||
1286 | + u16 vid; |
||
1287 | + int i; |
||
1288 | + |
||
1289 | + port_map = 0; |
||
1290 | + if (!__vlan_get_tag(skb, &vid)) { |
||
1291 | + for (i = 0; i < XRX200_MAX_VLAN; i++) { |
||
1292 | + if (priv->hw->vlan_vid[i] != vid) |
||
1293 | + continue; |
||
1294 | + port_map = priv->hw->vlan_port_map[i]; |
||
1295 | + break; |
||
1296 | + } |
||
1297 | + } |
||
1298 | + } |
||
1299 | + |
||
1300 | + special_tag |= (port_map << PORT_MAP_SHIFT) | |
||
1301 | + PORT_MAP_SEL | PORT_MAP_EN; |
||
1302 | + } |
||
1303 | + if(priv->wan) |
||
1304 | + special_tag |= (1 << DPID_SHIFT); |
||
1305 | + if(skb_headroom(skb) < 4) { |
||
1306 | + struct sk_buff *tmp = skb_realloc_headroom(skb, 4); |
||
1307 | + dev_kfree_skb_any(skb); |
||
1308 | + skb = tmp; |
||
1309 | + } |
||
1310 | + skb_push(skb, 4); |
||
1311 | + memcpy(skb->data, &special_tag, sizeof(u32)); |
||
1312 | + len += 4; |
||
1313 | +#endif |
||
1314 | + |
||
1315 | + /* dma needs to start on a 16 byte aligned address */ |
||
1316 | + byte_offset = CPHYSADDR(skb->data) % 16; |
||
1317 | + |
||
1318 | + spin_lock_bh(&ch->lock); |
||
1319 | + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { |
||
1320 | + netdev_err(dev, "tx ring full\n"); |
||
1321 | + netif_stop_queue(dev); |
||
1322 | + ret = NETDEV_TX_BUSY; |
||
1323 | + goto out; |
||
1324 | + } |
||
1325 | + |
||
1326 | + ch->skb[ch->dma.desc] = skb; |
||
1327 | + |
||
1328 | + netif_trans_update(dev); |
||
1329 | + |
||
1330 | + desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, |
||
1331 | + DMA_TO_DEVICE)) - byte_offset; |
||
1332 | + wmb(); |
||
1333 | + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | |
||
1334 | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); |
||
1335 | + ch->dma.desc++; |
||
1336 | + ch->dma.desc %= LTQ_DESC_NUM; |
||
1337 | + if (ch->dma.desc == ch->tx_free) |
||
1338 | + netif_stop_queue(dev); |
||
1339 | + |
||
1340 | + |
||
1341 | + priv->stats.tx_packets++; |
||
1342 | + priv->stats.tx_bytes+=len; |
||
1343 | + |
||
1344 | +out: |
||
1345 | + spin_unlock_bh(&ch->lock); |
||
1346 | + |
||
1347 | + return ret; |
||
1348 | +} |
||
1349 | + |
||
1350 | +static irqreturn_t xrx200_dma_irq(int irq, void *priv) |
||
1351 | +{ |
||
1352 | + struct xrx200_hw *hw = priv; |
||
1353 | + int chnr = irq - XRX200_DMA_IRQ; |
||
1354 | + struct xrx200_chan *ch = &hw->chan[chnr]; |
||
1355 | + |
||
1356 | + ltq_dma_disable_irq(&ch->dma); |
||
1357 | + ltq_dma_ack_irq(&ch->dma); |
||
1358 | + |
||
1359 | + if (chnr % 2) |
||
1360 | + tasklet_schedule(&ch->tasklet); |
||
1361 | + else |
||
1362 | + napi_schedule(&ch->napi); |
||
1363 | + |
||
1364 | + return IRQ_HANDLED; |
||
1365 | +} |
||
1366 | + |
||
1367 | +static int xrx200_dma_init(struct xrx200_hw *hw) |
||
1368 | +{ |
||
1369 | + int i, err = 0; |
||
1370 | + |
||
1371 | + ltq_dma_init_port(DMA_PORT_ETOP); |
||
1372 | + |
||
1373 | + for (i = 0; i < 8 && !err; i++) { |
||
1374 | + int irq = XRX200_DMA_IRQ + i; |
||
1375 | + struct xrx200_chan *ch = &hw->chan[i]; |
||
1376 | + |
||
1377 | + spin_lock_init(&ch->lock); |
||
1378 | + |
||
1379 | + ch->idx = ch->dma.nr = i; |
||
1380 | + |
||
1381 | + if (i == XRX200_DMA_TX) { |
||
1382 | + ltq_dma_alloc_tx(&ch->dma); |
||
1383 | + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw); |
||
1384 | + } else if (i == XRX200_DMA_TX_2) { |
||
1385 | + ltq_dma_alloc_tx(&ch->dma); |
||
1386 | + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx_2", hw); |
||
1387 | + } else if (i == XRX200_DMA_RX) { |
||
1388 | + ltq_dma_alloc_rx(&ch->dma); |
||
1389 | + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; |
||
1390 | + ch->dma.desc++) |
||
1391 | + if (xrx200_alloc_skb(ch)) |
||
1392 | + err = -ENOMEM; |
||
1393 | + ch->dma.desc = 0; |
||
1394 | + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw); |
||
1395 | + } else |
||
1396 | + continue; |
||
1397 | + |
||
1398 | + if (!err) |
||
1399 | + ch->dma.irq = irq; |
||
1400 | + else |
||
1401 | + pr_err("net-xrx200: failed to request irq %d\n", irq); |
||
1402 | + } |
||
1403 | + |
||
1404 | + return err; |
||
1405 | +} |
||
1406 | + |
||
1407 | +#ifdef SW_POLLING |
||
1408 | +static void xrx200_gmac_update(struct xrx200_port *port) |
||
1409 | +{ |
||
1410 | + u16 phyaddr = port->phydev->mdio.addr & MDIO_PHY_ADDR_MASK; |
||
1411 | + u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK; |
||
1412 | + u16 miirate = 0; |
||
1413 | + |
||
1414 | + switch (port->phydev->speed) { |
||
1415 | + case SPEED_1000: |
||
1416 | + phyaddr |= MDIO_PHY_SPEED_G1; |
||
1417 | + miirate = MII_CFG_RATE_M125; |
||
1418 | + break; |
||
1419 | + |
||
1420 | + case SPEED_100: |
||
1421 | + phyaddr |= MDIO_PHY_SPEED_M100; |
||
1422 | + switch (miimode) { |
||
1423 | + case MII_CFG_MODE_RMIIM: |
||
1424 | + case MII_CFG_MODE_RMIIP: |
||
1425 | + miirate = MII_CFG_RATE_M50; |
||
1426 | + break; |
||
1427 | + default: |
||
1428 | + miirate = MII_CFG_RATE_M25; |
||
1429 | + break; |
||
1430 | + } |
||
1431 | + break; |
||
1432 | + |
||
1433 | + default: |
||
1434 | + phyaddr |= MDIO_PHY_SPEED_M10; |
||
1435 | + miirate = MII_CFG_RATE_M2P5; |
||
1436 | + break; |
||
1437 | + } |
||
1438 | + |
||
1439 | + if (port->phydev->link) |
||
1440 | + phyaddr |= MDIO_PHY_LINK_UP; |
||
1441 | + else |
||
1442 | + phyaddr |= MDIO_PHY_LINK_DOWN; |
||
1443 | + |
||
1444 | + if (port->phydev->duplex == DUPLEX_FULL) |
||
1445 | + phyaddr |= MDIO_PHY_FDUP_EN; |
||
1446 | + else |
||
1447 | + phyaddr |= MDIO_PHY_FDUP_DIS; |
||
1448 | + |
||
1449 | + ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num)); |
||
1450 | + ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num)); |
||
1451 | + udelay(1); |
||
1452 | +} |
||
1453 | +#else |
||
1454 | +static void xrx200_gmac_update(struct xrx200_port *port) |
||
1455 | +{ |
||
1456 | + |
||
1457 | +} |
||
1458 | +#endif |
||
1459 | + |
||
1460 | +static void xrx200_mdio_link(struct net_device *dev) |
||
1461 | +{ |
||
1462 | + struct xrx200_priv *priv = netdev_priv(dev); |
||
1463 | + bool link = false; |
||
1464 | + int i; |
||
1465 | + |
||
1466 | + for (i = 0; i < priv->num_port; i++) { |
||
1467 | + if (!priv->port[i].phydev) |
||
1468 | + continue; |
||
1469 | + |
||
1470 | + if (priv->port[i].phydev->link) |
||
1471 | + link = true; |
||
1472 | + |
||
1473 | + if (priv->port[i].link != priv->port[i].phydev->link) { |
||
1474 | + xrx200_gmac_update(&priv->port[i]); |
||
1475 | + priv->port[i].link = priv->port[i].phydev->link; |
||
1476 | + netdev_info(dev, "port %d %s link\n", |
||
1477 | + priv->port[i].num, |
||
1478 | + (priv->port[i].link)?("got"):("lost")); |
||
1479 | + } |
||
1480 | + } |
||
1481 | + if (netif_carrier_ok(dev) && !link) |
||
1482 | + netif_carrier_off(dev); |
||
1483 | +} |
||
1484 | + |
||
1485 | +static inline int xrx200_mdio_poll(struct mii_bus *bus) |
||
1486 | +{ |
||
1487 | + unsigned cnt = 10000; |
||
1488 | + |
||
1489 | + while (likely(cnt--)) { |
||
1490 | + unsigned ctrl = ltq_mdio_r32(MDIO_CTRL); |
||
1491 | + if ((ctrl & MDIO_BUSY) == 0) |
||
1492 | + return 0; |
||
1493 | + } |
||
1494 | + |
||
1495 | + return 1; |
||
1496 | +} |
||
1497 | + |
||
1498 | +static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) |
||
1499 | +{ |
||
1500 | + if (xrx200_mdio_poll(bus)) |
||
1501 | + return 1; |
||
1502 | + |
||
1503 | + ltq_mdio_w32(val, MDIO_WRITE); |
||
1504 | + ltq_mdio_w32(MDIO_BUSY | MDIO_WR | |
||
1505 | + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | |
||
1506 | + (reg & MDIO_MASK), |
||
1507 | + MDIO_CTRL); |
||
1508 | + |
||
1509 | + return 0; |
||
1510 | +} |
||
1511 | + |
||
1512 | +static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg) |
||
1513 | +{ |
||
1514 | + if (xrx200_mdio_poll(bus)) |
||
1515 | + return -1; |
||
1516 | + |
||
1517 | + ltq_mdio_w32(MDIO_BUSY | MDIO_RD | |
||
1518 | + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | |
||
1519 | + (reg & MDIO_MASK), |
||
1520 | + MDIO_CTRL); |
||
1521 | + |
||
1522 | + if (xrx200_mdio_poll(bus)) |
||
1523 | + return -1; |
||
1524 | + |
||
1525 | + return ltq_mdio_r32(MDIO_READ); |
||
1526 | +} |
||
1527 | + |
||
1528 | +static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port) |
||
1529 | +{ |
||
1530 | + struct xrx200_priv *priv = netdev_priv(dev); |
||
1531 | + struct phy_device *phydev = NULL; |
||
1532 | + unsigned val; |
||
1533 | + |
||
1534 | + phydev = mdiobus_get_phy(priv->hw->mii_bus, port->phy_addr); |
||
1535 | + |
||
1536 | + if (!phydev) { |
||
1537 | + netdev_err(dev, "no PHY found\n"); |
||
1538 | + return -ENODEV; |
||
1539 | + } |
||
1540 | + |
||
1541 | + phydev = phy_connect(dev, phydev_name(phydev), &xrx200_mdio_link, |
||
1542 | + port->phy_if); |
||
1543 | + |
||
1544 | + if (IS_ERR(phydev)) { |
||
1545 | + netdev_err(dev, "Could not attach to PHY\n"); |
||
1546 | + return PTR_ERR(phydev); |
||
1547 | + } |
||
1548 | + |
||
1549 | + phydev->supported &= (SUPPORTED_10baseT_Half |
||
1550 | + | SUPPORTED_10baseT_Full |
||
1551 | + | SUPPORTED_100baseT_Half |
||
1552 | + | SUPPORTED_100baseT_Full |
||
1553 | + | SUPPORTED_1000baseT_Half |
||
1554 | + | SUPPORTED_1000baseT_Full |
||
1555 | + | SUPPORTED_Autoneg |
||
1556 | + | SUPPORTED_MII |
||
1557 | + | SUPPORTED_TP); |
||
1558 | + phydev->advertising = phydev->supported; |
||
1559 | + port->phydev = phydev; |
||
1560 | + phydev->no_auto_carrier_off = true; |
||
1561 | + |
||
1562 | + phy_attached_info(phydev); |
||
1563 | + |
||
1564 | +#ifdef SW_POLLING |
||
1565 | + phy_read_status(phydev); |
||
1566 | + |
||
1567 | + val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000); |
||
1568 | + val |= ADVERTIZE_MPD; |
||
1569 | + xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val); |
||
1570 | + xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040); |
||
1571 | + |
||
1572 | + phy_start_aneg(phydev); |
||
1573 | +#endif |
||
1574 | + return 0; |
||
1575 | +} |
||
1576 | + |
||
1577 | +static void xrx200_port_config(struct xrx200_priv *priv, |
||
1578 | + const struct xrx200_port *port) |
||
1579 | +{ |
||
1580 | + u16 miimode = 0; |
||
1581 | + |
||
1582 | + switch (port->num) { |
||
1583 | + case 0: /* xMII0 */ |
||
1584 | + case 1: /* xMII1 */ |
||
1585 | + switch (port->phy_if) { |
||
1586 | + case PHY_INTERFACE_MODE_MII: |
||
1587 | + if (port->flags & XRX200_PORT_TYPE_PHY) |
||
1588 | + /* MII MAC mode, connected to external PHY */ |
||
1589 | + miimode = MII_CFG_MODE_MIIM; |
||
1590 | + else |
||
1591 | + /* MII PHY mode, connected to external MAC */ |
||
1592 | + miimode = MII_CFG_MODE_MIIP; |
||
1593 | + break; |
||
1594 | + case PHY_INTERFACE_MODE_RMII: |
||
1595 | + if (port->flags & XRX200_PORT_TYPE_PHY) |
||
1596 | + /* RMII MAC mode, connected to external PHY */ |
||
1597 | + miimode = MII_CFG_MODE_RMIIM; |
||
1598 | + else |
||
1599 | + /* RMII PHY mode, connected to external MAC */ |
||
1600 | + miimode = MII_CFG_MODE_RMIIP; |
||
1601 | + break; |
||
1602 | + case PHY_INTERFACE_MODE_RGMII: |
||
1603 | + /* RGMII MAC mode, connected to external PHY */ |
||
1604 | + miimode = MII_CFG_MODE_RGMII; |
||
1605 | + break; |
||
1606 | + default: |
||
1607 | + break; |
||
1608 | + } |
||
1609 | + break; |
||
1610 | + case 2: /* internal GPHY0 */ |
||
1611 | + case 3: /* internal GPHY0 */ |
||
1612 | + case 4: /* internal GPHY1 */ |
||
1613 | + switch (port->phy_if) { |
||
1614 | + case PHY_INTERFACE_MODE_MII: |
||
1615 | + case PHY_INTERFACE_MODE_GMII: |
||
1616 | + /* MII MAC mode, connected to internal GPHY */ |
||
1617 | + miimode = MII_CFG_MODE_MIIM; |
||
1618 | + break; |
||
1619 | + default: |
||
1620 | + break; |
||
1621 | + } |
||
1622 | + break; |
||
1623 | + case 5: /* internal GPHY1 or xMII2 */ |
||
1624 | + switch (port->phy_if) { |
||
1625 | + case PHY_INTERFACE_MODE_MII: |
||
1626 | + /* MII MAC mode, connected to internal GPHY */ |
||
1627 | + miimode = MII_CFG_MODE_MIIM; |
||
1628 | + break; |
||
1629 | + case PHY_INTERFACE_MODE_RGMII: |
||
1630 | + /* RGMII MAC mode, connected to external PHY */ |
||
1631 | + miimode = MII_CFG_MODE_RGMII; |
||
1632 | + break; |
||
1633 | + default: |
||
1634 | + break; |
||
1635 | + } |
||
1636 | + break; |
||
1637 | + default: |
||
1638 | + break; |
||
1639 | + } |
||
1640 | + |
||
1641 | + ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN, |
||
1642 | + MII_CFG(port->num)); |
||
1643 | +} |
||
1644 | + |
||
1645 | +static int xrx200_init(struct net_device *dev) |
||
1646 | +{ |
||
1647 | + struct xrx200_priv *priv = netdev_priv(dev); |
||
1648 | + struct sockaddr mac; |
||
1649 | + int err, i; |
||
1650 | + |
||
1651 | +#ifndef SW_POLLING |
||
1652 | + unsigned int reg = 0; |
||
1653 | + |
||
1654 | + /* enable auto polling */ |
||
1655 | + for (i = 0; i < priv->num_port; i++) |
||
1656 | + reg |= BIT(priv->port[i].num); |
||
1657 | + ltq_mdio_w32(reg, MDIO_CLK_CFG0); |
||
1658 | + ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1); |
||
1659 | +#endif |
||
1660 | + |
||
1661 | + /* setup each port */ |
||
1662 | + for (i = 0; i < priv->num_port; i++) |
||
1663 | + xrx200_port_config(priv, &priv->port[i]); |
||
1664 | + |
||
1665 | + memcpy(&mac.sa_data, priv->mac, ETH_ALEN); |
||
1666 | + if (!is_valid_ether_addr(mac.sa_data)) { |
||
1667 | + pr_warn("net-xrx200: invalid MAC, using random\n"); |
||
1668 | + eth_random_addr(mac.sa_data); |
||
1669 | + dev->addr_assign_type |= NET_ADDR_RANDOM; |
||
1670 | + } |
||
1671 | + |
||
1672 | + err = eth_mac_addr(dev, &mac); |
||
1673 | + if (err) |
||
1674 | + goto err_netdev; |
||
1675 | + |
||
1676 | + for (i = 0; i < priv->num_port; i++) |
||
1677 | + if (xrx200_mdio_probe(dev, &priv->port[i])) |
||
1678 | + pr_warn("xrx200-mdio: probing phy of port %d failed\n", |
||
1679 | + priv->port[i].num); |
||
1680 | + |
||
1681 | + return 0; |
||
1682 | + |
||
1683 | +err_netdev: |
||
1684 | + unregister_netdev(dev); |
||
1685 | + free_netdev(dev); |
||
1686 | + return err; |
||
1687 | +} |
||
1688 | + |
||
1689 | +static void xrx200_pci_microcode(void) |
||
1690 | +{ |
||
1691 | + int i; |
||
1692 | + |
||
1693 | + ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK, |
||
1694 | + PCE_TBL_CFG_ADWR, PCE_TBL_CTRL); |
||
1695 | + ltq_switch_w32(0, PCE_TBL_MASK); |
||
1696 | + |
||
1697 | + for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) { |
||
1698 | + ltq_switch_w32(i, PCE_TBL_ADDR); |
||
1699 | + ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0)); |
||
1700 | + ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1)); |
||
1701 | + ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2)); |
||
1702 | + ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3)); |
||
1703 | + |
||
1704 | + // start the table access: |
||
1705 | + ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL); |
||
1706 | + while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY); |
||
1707 | + } |
||
1708 | + |
||
1709 | + /* tell the switch that the microcode is loaded */ |
||
1710 | + ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0)); |
||
1711 | +} |
||
1712 | + |
||
1713 | +static void xrx200_hw_init(struct xrx200_hw *hw) |
||
1714 | +{ |
||
1715 | + int i; |
||
1716 | + |
||
1717 | + /* enable clock gate */ |
||
1718 | + clk_enable(hw->clk); |
||
1719 | + |
||
1720 | + ltq_switch_w32(1, 0); |
||
1721 | + mdelay(100); |
||
1722 | + ltq_switch_w32(0, 0); |
||
1723 | + /* |
||
1724 | + * TODO: we should really disbale all phys/miis here and explicitly |
||
1725 | + * enable them in the device secific init function |
||
1726 | + */ |
||
1727 | + |
||
1728 | + /* disable port fetch/store dma */ |
||
1729 | + for (i = 0; i < 7; i++ ) { |
||
1730 | + ltq_switch_w32(0, FDMA_PCTRLx(i)); |
||
1731 | + ltq_switch_w32(0, SDMA_PCTRLx(i)); |
||
1732 | + } |
||
1733 | + |
||
1734 | + /* enable Switch */ |
||
1735 | + ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB); |
||
1736 | + |
||
1737 | + /* load the pce microcode */ |
||
1738 | + xrx200_pci_microcode(); |
||
1739 | + |
||
1740 | + /* Default unknown Broadcat/Multicast/Unicast port maps */ |
||
1741 | + ltq_switch_w32(0x40, PCE_PMAP1); |
||
1742 | + ltq_switch_w32(0x40, PCE_PMAP2); |
||
1743 | + ltq_switch_w32(0x40, PCE_PMAP3); |
||
1744 | + |
||
1745 | + /* RMON Counter Enable for all physical ports */ |
||
1746 | + for (i = 0; i < 7; i++) |
||
1747 | + ltq_switch_w32(0x1, BM_PCFG(i)); |
||
1748 | + |
||
1749 | + /* disable auto polling */ |
||
1750 | + ltq_mdio_w32(0x0, MDIO_CLK_CFG0); |
||
1751 | + |
||
1752 | + /* enable port statistic counters */ |
||
1753 | + for (i = 0; i < 7; i++) |
||
1754 | + ltq_switch_w32(0x1, BM_PCFGx(i)); |
||
1755 | + |
||
1756 | + /* set IPG to 12 */ |
||
1757 | + ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG); |
||
1758 | + |
||
1759 | +#ifdef SW_ROUTING |
||
1760 | + /* enable status header, enable CRC */ |
||
1761 | + ltq_pmac_w32_mask(0, |
||
1762 | + PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, |
||
1763 | + PMAC_HD_CTL); |
||
1764 | +#else |
||
1765 | + /* disable status header, enable CRC */ |
||
1766 | + ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS, |
||
1767 | + PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, |
||
1768 | + PMAC_HD_CTL); |
||
1769 | +#endif |
||
1770 | + |
||
1771 | + /* enable port fetch/store dma & VLAN Modification */ |
||
1772 | + for (i = 0; i < 7; i++ ) { |
||
1773 | + ltq_switch_w32_mask(0, 0x19, FDMA_PCTRLx(i)); |
||
1774 | + ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i)); |
||
1775 | + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0)); |
||
1776 | + } |
||
1777 | + |
||
1778 | + /* enable special tag insertion on cpu port */ |
||
1779 | + ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6)); |
||
1780 | + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0)); |
||
1781 | + ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2)); |
||
1782 | + ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG); |
||
1783 | + xrx200sw_write_x(1, XRX200_BM_QUEUE_GCTRL_GL_MOD, 0); |
||
1784 | + |
||
1785 | + for (i = 0; i < XRX200_MAX_VLAN; i++) |
||
1786 | + hw->vlan_vid[i] = i; |
||
1787 | +} |
||
1788 | + |
||
1789 | +static void xrx200_hw_cleanup(struct xrx200_hw *hw) |
||
1790 | +{ |
||
1791 | + int i; |
||
1792 | + |
||
1793 | + /* disable the switch */ |
||
1794 | + ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB); |
||
1795 | + |
||
1796 | + /* free the channels and IRQs */ |
||
1797 | + for (i = 0; i < 2; i++) { |
||
1798 | + ltq_dma_free(&hw->chan[i].dma); |
||
1799 | + if (hw->chan[i].dma.irq) |
||
1800 | + free_irq(hw->chan[i].dma.irq, hw); |
||
1801 | + } |
||
1802 | + |
||
1803 | + /* free the allocated RX ring */ |
||
1804 | + for (i = 0; i < LTQ_DESC_NUM; i++) |
||
1805 | + dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]); |
||
1806 | + |
||
1807 | + /* clear the mdio bus */ |
||
1808 | + mdiobus_unregister(hw->mii_bus); |
||
1809 | + mdiobus_free(hw->mii_bus); |
||
1810 | + |
||
1811 | + /* release the clock */ |
||
1812 | + clk_disable(hw->clk); |
||
1813 | + clk_put(hw->clk); |
||
1814 | +} |
||
1815 | + |
||
1816 | +static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np) |
||
1817 | +{ |
||
1818 | + hw->mii_bus = mdiobus_alloc(); |
||
1819 | + if (!hw->mii_bus) |
||
1820 | + return -ENOMEM; |
||
1821 | + |
||
1822 | + hw->mii_bus->read = xrx200_mdio_rd; |
||
1823 | + hw->mii_bus->write = xrx200_mdio_wr; |
||
1824 | + hw->mii_bus->name = "lantiq,xrx200-mdio"; |
||
1825 | + snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); |
||
1826 | + |
||
1827 | + if (of_mdiobus_register(hw->mii_bus, np)) { |
||
1828 | + mdiobus_free(hw->mii_bus); |
||
1829 | + return -ENXIO; |
||
1830 | + } |
||
1831 | + |
||
1832 | + return 0; |
||
1833 | +} |
||
1834 | + |
||
1835 | +static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port) |
||
1836 | +{ |
||
1837 | + const __be32 *addr, *id = of_get_property(port, "reg", NULL); |
||
1838 | + struct xrx200_port *p = &priv->port[priv->num_port]; |
||
1839 | + |
||
1840 | + if (!id) |
||
1841 | + return; |
||
1842 | + |
||
1843 | + memset(p, 0, sizeof(struct xrx200_port)); |
||
1844 | + p->phy_node = of_parse_phandle(port, "phy-handle", 0); |
||
1845 | + addr = of_get_property(p->phy_node, "reg", NULL); |
||
1846 | + if (!addr) |
||
1847 | + return; |
||
1848 | + |
||
1849 | + p->num = *id; |
||
1850 | + p->phy_addr = *addr; |
||
1851 | + p->phy_if = of_get_phy_mode(port); |
||
1852 | + if (p->phy_addr > 0x10) |
||
1853 | + p->flags = XRX200_PORT_TYPE_MAC; |
||
1854 | + else |
||
1855 | + p->flags = XRX200_PORT_TYPE_PHY; |
||
1856 | + priv->num_port++; |
||
1857 | + |
||
1858 | + p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags); |
||
1859 | + if (gpio_is_valid(p->gpio)) |
||
1860 | + if (!gpio_request(p->gpio, "phy-reset")) { |
||
1861 | + gpio_direction_output(p->gpio, |
||
1862 | + (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0)); |
||
1863 | + udelay(100); |
||
1864 | + gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1)); |
||
1865 | + } |
||
1866 | + /* is this port a wan port ? */ |
||
1867 | + if (priv->wan) |
||
1868 | + priv->hw->wan_map |= BIT(p->num); |
||
1869 | + |
||
1870 | + priv->port_map |= BIT(p->num); |
||
1871 | + |
||
1872 | + /* store the port id in the hw struct so we can map ports -> devices */ |
||
1873 | + priv->hw->port_map[p->num] = priv->hw->num_devs; |
||
1874 | +} |
||
1875 | + |
||
1876 | +static const struct net_device_ops xrx200_netdev_ops = { |
||
1877 | + .ndo_init = xrx200_init, |
||
1878 | + .ndo_open = xrx200_open, |
||
1879 | + .ndo_stop = xrx200_close, |
||
1880 | + .ndo_start_xmit = xrx200_start_xmit, |
||
1881 | + .ndo_set_mac_address = eth_mac_addr, |
||
1882 | + .ndo_validate_addr = eth_validate_addr, |
||
1883 | + .ndo_change_mtu = eth_change_mtu, |
||
1884 | + .ndo_get_stats = xrx200_get_stats, |
||
1885 | + .ndo_tx_timeout = xrx200_tx_timeout, |
||
1886 | +}; |
||
1887 | + |
||
1888 | +static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface, struct device *dev) |
||
1889 | +{ |
||
1890 | + struct xrx200_priv *priv; |
||
1891 | + struct device_node *port; |
||
1892 | + const __be32 *wan; |
||
1893 | + const u8 *mac; |
||
1894 | + |
||
1895 | + /* alloc the network device */ |
||
1896 | + hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv)); |
||
1897 | + if (!hw->devs[hw->num_devs]) |
||
1898 | + return; |
||
1899 | + |
||
1900 | + /* setup the network device */ |
||
1901 | + strcpy(hw->devs[hw->num_devs]->name, "eth%d"); |
||
1902 | + hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops; |
||
1903 | + hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT; |
||
1904 | + hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM; |
||
1905 | + SET_NETDEV_DEV(hw->devs[hw->num_devs], dev); |
||
1906 | + |
||
1907 | + /* setup our private data */ |
||
1908 | + priv = netdev_priv(hw->devs[hw->num_devs]); |
||
1909 | + priv->hw = hw; |
||
1910 | + priv->id = hw->num_devs; |
||
1911 | + |
||
1912 | + mac = of_get_mac_address(iface); |
||
1913 | + if (mac) |
||
1914 | + memcpy(priv->mac, mac, ETH_ALEN); |
||
1915 | + |
||
1916 | + /* is this the wan interface ? */ |
||
1917 | + wan = of_get_property(iface, "lantiq,wan", NULL); |
||
1918 | + if (wan && (*wan == 1)) |
||
1919 | + priv->wan = 1; |
||
1920 | + |
||
1921 | + /* should the switch be enabled on this interface ? */ |
||
1922 | + if (of_find_property(iface, "lantiq,switch", NULL)) |
||
1923 | + priv->sw = 1; |
||
1924 | + |
||
1925 | + /* load the ports that are part of the interface */ |
||
1926 | + for_each_child_of_node(iface, port) |
||
1927 | + if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port")) |
||
1928 | + xrx200_of_port(priv, port); |
||
1929 | + |
||
1930 | + /* register the actual device */ |
||
1931 | + if (!register_netdev(hw->devs[hw->num_devs])) |
||
1932 | + hw->num_devs++; |
||
1933 | +} |
||
1934 | + |
||
1935 | +static struct xrx200_hw xrx200_hw; |
||
1936 | + |
||
1937 | +static int xrx200_probe(struct platform_device *pdev) |
||
1938 | +{ |
||
1939 | + struct resource *res[4]; |
||
1940 | + struct device_node *mdio_np, *iface_np; |
||
1941 | + int i; |
||
1942 | + |
||
1943 | + /* load the memory ranges */ |
||
1944 | + for (i = 0; i < 4; i++) { |
||
1945 | + res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i); |
||
1946 | + if (!res[i]) { |
||
1947 | + dev_err(&pdev->dev, "failed to get resources\n"); |
||
1948 | + return -ENOENT; |
||
1949 | + } |
||
1950 | + } |
||
1951 | + xrx200_switch_membase = devm_ioremap_resource(&pdev->dev, res[0]); |
||
1952 | + xrx200_mdio_membase = devm_ioremap_resource(&pdev->dev, res[1]); |
||
1953 | + xrx200_mii_membase = devm_ioremap_resource(&pdev->dev, res[2]); |
||
1954 | + xrx200_pmac_membase = devm_ioremap_resource(&pdev->dev, res[3]); |
||
1955 | + if (!xrx200_switch_membase || !xrx200_mdio_membase || |
||
1956 | + !xrx200_mii_membase || !xrx200_pmac_membase) { |
||
1957 | + dev_err(&pdev->dev, "failed to request and remap io ranges \n"); |
||
1958 | + return -ENOMEM; |
||
1959 | + } |
||
1960 | + |
||
1961 | + /* get the clock */ |
||
1962 | + xrx200_hw.clk = clk_get(&pdev->dev, NULL); |
||
1963 | + if (IS_ERR(xrx200_hw.clk)) { |
||
1964 | + dev_err(&pdev->dev, "failed to get clock\n"); |
||
1965 | + return PTR_ERR(xrx200_hw.clk); |
||
1966 | + } |
||
1967 | + |
||
1968 | + /* bring up the dma engine and IP core */ |
||
1969 | + xrx200_dma_init(&xrx200_hw); |
||
1970 | + xrx200_hw_init(&xrx200_hw); |
||
1971 | + tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX]); |
||
1972 | + tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX_2].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX_2]); |
||
1973 | + |
||
1974 | + /* bring up the mdio bus */ |
||
1975 | + mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL, |
||
1976 | + "lantiq,xrx200-mdio"); |
||
1977 | + if (mdio_np) |
||
1978 | + if (xrx200_of_mdio(&xrx200_hw, mdio_np)) |
||
1979 | + dev_err(&pdev->dev, "mdio probe failed\n"); |
||
1980 | + |
||
1981 | + /* load the interfaces */ |
||
1982 | + for_each_child_of_node(pdev->dev.of_node, iface_np) |
||
1983 | + if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) { |
||
1984 | + if (xrx200_hw.num_devs < XRX200_MAX_DEV) |
||
1985 | + xrx200_of_iface(&xrx200_hw, iface_np, &pdev->dev); |
||
1986 | + else |
||
1987 | + dev_err(&pdev->dev, |
||
1988 | + "only %d interfaces allowed\n", |
||
1989 | + XRX200_MAX_DEV); |
||
1990 | + } |
||
1991 | + |
||
1992 | + if (!xrx200_hw.num_devs) { |
||
1993 | + xrx200_hw_cleanup(&xrx200_hw); |
||
1994 | + dev_err(&pdev->dev, "failed to load interfaces\n"); |
||
1995 | + return -ENOENT; |
||
1996 | + } |
||
1997 | + |
||
1998 | + xrx200sw_init(&xrx200_hw); |
||
1999 | + |
||
2000 | + /* set wan port mask */ |
||
2001 | + ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN); |
||
2002 | + |
||
2003 | + for (i = 0; i < xrx200_hw.num_devs; i++) { |
||
2004 | + xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i]; |
||
2005 | + xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i]; |
||
2006 | + xrx200_hw.chan[XRX200_DMA_TX_2].devs[i] = xrx200_hw.devs[i]; |
||
2007 | + } |
||
2008 | + |
||
2009 | + /* setup NAPI */ |
||
2010 | + init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev); |
||
2011 | + netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev, |
||
2012 | + &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32); |
||
2013 | + |
||
2014 | + platform_set_drvdata(pdev, &xrx200_hw); |
||
2015 | + |
||
2016 | + return 0; |
||
2017 | +} |
||
2018 | + |
||
2019 | +static int xrx200_remove(struct platform_device *pdev) |
||
2020 | +{ |
||
2021 | + struct net_device *dev = platform_get_drvdata(pdev); |
||
2022 | + struct xrx200_priv *priv; |
||
2023 | + |
||
2024 | + if (!dev) |
||
2025 | + return 0; |
||
2026 | + |
||
2027 | + priv = netdev_priv(dev); |
||
2028 | + |
||
2029 | + /* free stack related instances */ |
||
2030 | + netif_stop_queue(dev); |
||
2031 | + netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi); |
||
2032 | + |
||
2033 | + /* shut down hardware */ |
||
2034 | + xrx200_hw_cleanup(&xrx200_hw); |
||
2035 | + |
||
2036 | + /* remove the actual device */ |
||
2037 | + unregister_netdev(dev); |
||
2038 | + free_netdev(dev); |
||
2039 | + |
||
2040 | + return 0; |
||
2041 | +} |
||
2042 | + |
||
2043 | +static const struct of_device_id xrx200_match[] = { |
||
2044 | + { .compatible = "lantiq,xrx200-net" }, |
||
2045 | + {}, |
||
2046 | +}; |
||
2047 | +MODULE_DEVICE_TABLE(of, xrx200_match); |
||
2048 | + |
||
2049 | +static struct platform_driver xrx200_driver = { |
||
2050 | + .probe = xrx200_probe, |
||
2051 | + .remove = xrx200_remove, |
||
2052 | + .driver = { |
||
2053 | + .name = "lantiq,xrx200-net", |
||
2054 | + .of_match_table = xrx200_match, |
||
2055 | + .owner = THIS_MODULE, |
||
2056 | + }, |
||
2057 | +}; |
||
2058 | + |
||
2059 | +module_platform_driver(xrx200_driver); |
||
2060 | + |
||
2061 | +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); |
||
2062 | +MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet"); |
||
2063 | +MODULE_LICENSE("GPL"); |
||
2064 | --- /dev/null |
||
2065 | +++ b/drivers/net/ethernet/lantiq_xrx200_sw.h |
||
2066 | @@ -0,0 +1,1328 @@ |
||
2067 | +/* |
||
2068 | + * This program is free software; you can redistribute it and/or modify it |
||
2069 | + * under the terms of the GNU General Public License version 2 as published |
||
2070 | + * by the Free Software Foundation. |
||
2071 | + * |
||
2072 | + * This program is distributed in the hope that it will be useful, |
||
2073 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
2074 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
2075 | + * GNU General Public License for more details. |
||
2076 | + * |
||
2077 | + * You should have received a copy of the GNU General Public License |
||
2078 | + * along with this program; if not, write to the Free Software |
||
2079 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
||
2080 | + * |
||
2081 | + * Copyright (C) 2010 Lantiq Deutschland GmbH |
||
2082 | + * Copyright (C) 2013 Antonios Vamporakis <vamporakis@yahoo.com> |
||
2083 | + * |
||
2084 | + * VR9 switch registers extracted from 310TUJ0 switch api |
||
2085 | + * WARNING mult values of 0x00 may not be correct |
||
2086 | + * |
||
2087 | + */ |
||
2088 | + |
||
2089 | +enum { |
||
2090 | +// XRX200_ETHSW_SWRES, /* Ethernet Switch ResetControl Register */ |
||
2091 | +// XRX200_ETHSW_SWRES_R1, /* Hardware Reset */ |
||
2092 | +// XRX200_ETHSW_SWRES_R0, /* Register Configuration */ |
||
2093 | +// XRX200_ETHSW_CLK_MAC_GAT, /* Ethernet Switch Clock ControlRegister */ |
||
2094 | +// XRX200_ETHSW_CLK_EXP_SLEEP, /* Exponent to put system into sleep */ |
||
2095 | +// XRX200_ETHSW_CLK_EXP_WAKE, /* Exponent to wake up system */ |
||
2096 | +// XRX200_ETHSW_CLK_CLK2_EN, /* CLK2 Input for MAC */ |
||
2097 | +// XRX200_ETHSW_CLK_EXT_DIV_EN, /* External Clock Divider Enable */ |
||
2098 | +// XRX200_ETHSW_CLK_RAM_DBG_EN, /* Clock Gating Enable */ |
||
2099 | +// XRX200_ETHSW_CLK_REG_GAT_EN, /* Clock Gating Enable */ |
||
2100 | +// XRX200_ETHSW_CLK_GAT_EN, /* Clock Gating Enable */ |
||
2101 | +// XRX200_ETHSW_CLK_MAC_GAT_EN, /* Clock Gating Enable */ |
||
2102 | +// XRX200_ETHSW_DBG_STEP, /* Ethernet Switch Debug ControlRegister */ |
||
2103 | +// XRX200_ETHSW_DBG_CLK_SEL, /* Trigger Enable */ |
||
2104 | +// XRX200_ETHSW_DBG_MON_EN, /* Monitoring Enable */ |
||
2105 | +// XRX200_ETHSW_DBG_TRIG_EN, /* Trigger Enable */ |
||
2106 | +// XRX200_ETHSW_DBG_MODE, /* Debug Mode */ |
||
2107 | +// XRX200_ETHSW_DBG_STEP_TIME, /* Clock Step Size */ |
||
2108 | +// XRX200_ETHSW_SSB_MODE, /* Ethernet Switch SharedSegment Buffer Mode Register */ |
||
2109 | +// XRX200_ETHSW_SSB_MODE_ADDE, /* Memory Address */ |
||
2110 | +// XRX200_ETHSW_SSB_MODE_MODE, /* Memory Access Mode */ |
||
2111 | +// XRX200_ETHSW_SSB_ADDR, /* Ethernet Switch SharedSegment Buffer Address Register */ |
||
2112 | +// XRX200_ETHSW_SSB_ADDR_ADDE, /* Memory Address */ |
||
2113 | +// XRX200_ETHSW_SSB_DATA, /* Ethernet Switch SharedSegment Buffer Data Register */ |
||
2114 | +// XRX200_ETHSW_SSB_DATA_DATA, /* Data Value */ |
||
2115 | +// XRX200_ETHSW_CAP_0, /* Ethernet Switch CapabilityRegister 0 */ |
||
2116 | +// XRX200_ETHSW_CAP_0_SPEED, /* Clock frequency */ |
||
2117 | +// XRX200_ETHSW_CAP_1, /* Ethernet Switch CapabilityRegister 1 */ |
||
2118 | +// XRX200_ETHSW_CAP_1_GMAC, /* MAC operation mode */ |
||
2119 | +// XRX200_ETHSW_CAP_1_QUEUE, /* Number of queues */ |
||
2120 | +// XRX200_ETHSW_CAP_1_VPORTS, /* Number of virtual ports */ |
||
2121 | +// XRX200_ETHSW_CAP_1_PPORTS, /* Number of physical ports */ |
||
2122 | +// XRX200_ETHSW_CAP_2, /* Ethernet Switch CapabilityRegister 2 */ |
||
2123 | +// XRX200_ETHSW_CAP_2_PACKETS, /* Number of packets */ |
||
2124 | +// XRX200_ETHSW_CAP_3, /* Ethernet Switch CapabilityRegister 3 */ |
||
2125 | +// XRX200_ETHSW_CAP_3_METERS, /* Number of traffic meters */ |
||
2126 | +// XRX200_ETHSW_CAP_3_SHAPERS, /* Number of traffic shapers */ |
||
2127 | +// XRX200_ETHSW_CAP_4, /* Ethernet Switch CapabilityRegister 4 */ |
||
2128 | +// XRX200_ETHSW_CAP_4_PPPOE, /* PPPoE table size */ |
||
2129 | +// XRX200_ETHSW_CAP_4_VLAN, /* Active VLAN table size */ |
||
2130 | +// XRX200_ETHSW_CAP_5, /* Ethernet Switch CapabilityRegister 5 */ |
||
2131 | +// XRX200_ETHSW_CAP_5_IPPLEN, /* IP packet length table size */ |
||
2132 | +// XRX200_ETHSW_CAP_5_PROT, /* Protocol table size */ |
||
2133 | +// XRX200_ETHSW_CAP_6, /* Ethernet Switch CapabilityRegister 6 */ |
||
2134 | +// XRX200_ETHSW_CAP_6_MACDASA, /* MAC DA/SA table size */ |
||
2135 | +// XRX200_ETHSW_CAP_6_APPL, /* Application table size */ |
||
2136 | +// XRX200_ETHSW_CAP_7, /* Ethernet Switch CapabilityRegister 7 */ |
||
2137 | +// XRX200_ETHSW_CAP_7_IPDASAM, /* IP DA/SA MSB table size */ |
||
2138 | +// XRX200_ETHSW_CAP_7_IPDASAL, /* IP DA/SA LSB table size */ |
||
2139 | +// XRX200_ETHSW_CAP_8, /* Ethernet Switch CapabilityRegister 8 */ |
||
2140 | +// XRX200_ETHSW_CAP_8_MCAST, /* Multicast table size */ |
||
2141 | +// XRX200_ETHSW_CAP_9, /* Ethernet Switch CapabilityRegister 9 */ |
||
2142 | +// XRX200_ETHSW_CAP_9_FLAGG, /* Flow Aggregation table size */ |
||
2143 | +// XRX200_ETHSW_CAP_10, /* Ethernet Switch CapabilityRegister 10 */ |
||
2144 | +// XRX200_ETHSW_CAP_10_MACBT, /* MAC bridging table size */ |
||
2145 | +// XRX200_ETHSW_CAP_11, /* Ethernet Switch CapabilityRegister 11 */ |
||
2146 | +// XRX200_ETHSW_CAP_11_BSIZEL, /* Packet buffer size (lower part, in byte) */ |
||
2147 | +// XRX200_ETHSW_CAP_12, /* Ethernet Switch CapabilityRegister 12 */ |
||
2148 | +// XRX200_ETHSW_CAP_12_BSIZEH, /* Packet buffer size (higher part, in byte) */ |
||
2149 | +// XRX200_ETHSW_VERSION_REV, /* Ethernet Switch VersionRegister */ |
||
2150 | +// XRX200_ETHSW_VERSION_MOD_ID, /* Module Identification */ |
||
2151 | +// XRX200_ETHSW_VERSION_REV_ID, /* Hardware Revision Identification */ |
||
2152 | +// XRX200_ETHSW_IER, /* Interrupt Enable Register */ |
||
2153 | +// XRX200_ETHSW_IER_FDMAIE, /* Fetch DMA Interrupt Enable */ |
||
2154 | +// XRX200_ETHSW_IER_SDMAIE, /* Store DMA Interrupt Enable */ |
||
2155 | +// XRX200_ETHSW_IER_MACIE, /* Ethernet MAC Interrupt Enable */ |
||
2156 | +// XRX200_ETHSW_IER_PCEIE, /* Parser and Classification Engine Interrupt Enable */ |
||
2157 | +// XRX200_ETHSW_IER_BMIE, /* Buffer Manager Interrupt Enable */ |
||
2158 | +// XRX200_ETHSW_ISR, /* Interrupt Status Register */ |
||
2159 | +// XRX200_ETHSW_ISR_FDMAINT, /* Fetch DMA Interrupt */ |
||
2160 | +// XRX200_ETHSW_ISR_SDMAINT, /* Store DMA Interrupt */ |
||
2161 | +// XRX200_ETHSW_ISR_MACINT, /* Ethernet MAC Interrupt */ |
||
2162 | +// XRX200_ETHSW_ISR_PCEINT, /* Parser and Classification Engine Interrupt */ |
||
2163 | +// XRX200_ETHSW_ISR_BMINT, /* Buffer Manager Interrupt */ |
||
2164 | +// XRX200_ETHSW_SPARE_0, /* Ethernet Switch SpareCells 0 */ |
||
2165 | +// XRX200_ETHSW_SPARE_0_SPARE, /* SPARE0 */ |
||
2166 | +// XRX200_ETHSW_SPARE_1, /* Ethernet Switch SpareCells 1 */ |
||
2167 | +// XRX200_ETHSW_SPARE_1_SPARE, /* SPARE1 */ |
||
2168 | +// XRX200_ETHSW_SPARE_2, /* Ethernet Switch SpareCells 2 */ |
||
2169 | +// XRX200_ETHSW_SPARE_2_SPARE, /* SPARE2 */ |
||
2170 | +// XRX200_ETHSW_SPARE_3, /* Ethernet Switch SpareCells 3 */ |
||
2171 | +// XRX200_ETHSW_SPARE_3_SPARE, /* SPARE3 */ |
||
2172 | +// XRX200_ETHSW_SPARE_4, /* Ethernet Switch SpareCells 4 */ |
||
2173 | +// XRX200_ETHSW_SPARE_4_SPARE, /* SPARE4 */ |
||
2174 | +// XRX200_ETHSW_SPARE_5, /* Ethernet Switch SpareCells 5 */ |
||
2175 | +// XRX200_ETHSW_SPARE_5_SPARE, /* SPARE5 */ |
||
2176 | +// XRX200_ETHSW_SPARE_6, /* Ethernet Switch SpareCells 6 */ |
||
2177 | +// XRX200_ETHSW_SPARE_6_SPARE, /* SPARE6 */ |
||
2178 | +// XRX200_ETHSW_SPARE_7, /* Ethernet Switch SpareCells 7 */ |
||
2179 | +// XRX200_ETHSW_SPARE_7_SPARE, /* SPARE7 */ |
||
2180 | +// XRX200_ETHSW_SPARE_8, /* Ethernet Switch SpareCells 8 */ |
||
2181 | +// XRX200_ETHSW_SPARE_8_SPARE, /* SPARE8 */ |
||
2182 | +// XRX200_ETHSW_SPARE_9, /* Ethernet Switch SpareCells 9 */ |
||
2183 | +// XRX200_ETHSW_SPARE_9_SPARE, /* SPARE9 */ |
||
2184 | +// XRX200_ETHSW_SPARE_10, /* Ethernet Switch SpareCells 10 */ |
||
2185 | +// XRX200_ETHSW_SPARE_10_SPARE, /* SPARE10 */ |
||
2186 | +// XRX200_ETHSW_SPARE_11, /* Ethernet Switch SpareCells 11 */ |
||
2187 | +// XRX200_ETHSW_SPARE_11_SPARE, /* SPARE11 */ |
||
2188 | +// XRX200_ETHSW_SPARE_12, /* Ethernet Switch SpareCells 12 */ |
||
2189 | +// XRX200_ETHSW_SPARE_12_SPARE, /* SPARE12 */ |
||
2190 | +// XRX200_ETHSW_SPARE_13, /* Ethernet Switch SpareCells 13 */ |
||
2191 | +// XRX200_ETHSW_SPARE_13_SPARE, /* SPARE13 */ |
||
2192 | +// XRX200_ETHSW_SPARE_14, /* Ethernet Switch SpareCells 14 */ |
||
2193 | +// XRX200_ETHSW_SPARE_14_SPARE, /* SPARE14 */ |
||
2194 | +// XRX200_ETHSW_SPARE_15, /* Ethernet Switch SpareCells 15 */ |
||
2195 | +// XRX200_ETHSW_SPARE_15_SPARE, /* SPARE15 */ |
||
2196 | +// XRX200_BM_RAM_VAL_3, /* RAM Value Register 3 */ |
||
2197 | +// XRX200_BM_RAM_VAL_3_VAL3, /* Data value [15:0] */ |
||
2198 | +// XRX200_BM_RAM_VAL_2, /* RAM Value Register 2 */ |
||
2199 | +// XRX200_BM_RAM_VAL_2_VAL2, /* Data value [15:0] */ |
||
2200 | +// XRX200_BM_RAM_VAL_1, /* RAM Value Register 1 */ |
||
2201 | +// XRX200_BM_RAM_VAL_1_VAL1, /* Data value [15:0] */ |
||
2202 | +// XRX200_BM_RAM_VAL_0, /* RAM Value Register 0 */ |
||
2203 | +// XRX200_BM_RAM_VAL_0_VAL0, /* Data value [15:0] */ |
||
2204 | +// XRX200_BM_RAM_ADDR, /* RAM Address Register */ |
||
2205 | +// XRX200_BM_RAM_ADDR_ADDR, /* RAM Address */ |
||
2206 | +// XRX200_BM_RAM_CTRL, /* RAM Access Control Register */ |
||
2207 | +// XRX200_BM_RAM_CTRL_BAS, /* Access Busy/Access Start */ |
||
2208 | +// XRX200_BM_RAM_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ |
||
2209 | +// XRX200_BM_RAM_CTRL_ADDR, /* Address for RAM selection */ |
||
2210 | +// XRX200_BM_FSQM_GCTRL, /* Free Segment Queue ManagerGlobal Control Register */ |
||
2211 | +// XRX200_BM_FSQM_GCTRL_SEGNUM, /* Maximum Segment Number */ |
||
2212 | +// XRX200_BM_CONS_SEG, /* Number of Consumed SegmentsRegister */ |
||
2213 | +// XRX200_BM_CONS_SEG_FSEG, /* Number of Consumed Segments */ |
||
2214 | +// XRX200_BM_CONS_PKT, /* Number of Consumed PacketPointers Register */ |
||
2215 | +// XRX200_BM_CONS_PKT_FQP, /* Number of Consumed Packet Pointers */ |
||
2216 | +// XRX200_BM_GCTRL_F, /* Buffer Manager Global ControlRegister 0 */ |
||
2217 | +// XRX200_BM_GCTRL_BM_STA, /* Buffer Manager Initialization Status Bit */ |
||
2218 | +// XRX200_BM_GCTRL_SAT, /* RMON Counter Update Mode */ |
||
2219 | +// XRX200_BM_GCTRL_FR_RBC, /* Freeze RMON RX Bad Byte 64 Bit Counter */ |
||
2220 | +// XRX200_BM_GCTRL_FR_RGC, /* Freeze RMON RX Good Byte 64 Bit Counter */ |
||
2221 | +// XRX200_BM_GCTRL_FR_TGC, /* Freeze RMON TX Good Byte 64 Bit Counter */ |
||
2222 | +// XRX200_BM_GCTRL_I_FIN, /* RAM initialization finished */ |
||
2223 | +// XRX200_BM_GCTRL_CX_INI, /* PQM Context RAM initialization */ |
||
2224 | +// XRX200_BM_GCTRL_FP_INI, /* FPQM RAM initialization */ |
||
2225 | +// XRX200_BM_GCTRL_FS_INI, /* FSQM RAM initialization */ |
||
2226 | +// XRX200_BM_GCTRL_R_SRES, /* Software Reset for RMON */ |
||
2227 | +// XRX200_BM_GCTRL_S_SRES, /* Software Reset for Scheduler */ |
||
2228 | +// XRX200_BM_GCTRL_A_SRES, /* Software Reset for AVG */ |
||
2229 | +// XRX200_BM_GCTRL_P_SRES, /* Software Reset for PQM */ |
||
2230 | +// XRX200_BM_GCTRL_F_SRES, /* Software Reset for FSQM */ |
||
2231 | +// XRX200_BM_QUEUE_GCTRL, /* Queue Manager GlobalControl Register 0 */ |
||
2232 | + XRX200_BM_QUEUE_GCTRL_GL_MOD, /* WRED Mode Signal */ |
||
2233 | +// XRX200_BM_QUEUE_GCTRL_AQUI, /* Average Queue Update Interval */ |
||
2234 | +// XRX200_BM_QUEUE_GCTRL_AQWF, /* Average Queue Weight Factor */ |
||
2235 | +// XRX200_BM_QUEUE_GCTRL_QAVGEN, /* Queue Average Calculation Enable */ |
||
2236 | +// XRX200_BM_QUEUE_GCTRL_DPROB, /* Drop Probability Profile */ |
||
2237 | +// XRX200_BM_WRED_RTH_0, /* WRED Red Threshold Register0 */ |
||
2238 | +// XRX200_BM_WRED_RTH_0_MINTH, /* Minimum Threshold */ |
||
2239 | +// XRX200_BM_WRED_RTH_1, /* WRED Red Threshold Register1 */ |
||
2240 | +// XRX200_BM_WRED_RTH_1_MAXTH, /* Maximum Threshold */ |
||
2241 | +// XRX200_BM_WRED_YTH_0, /* WRED Yellow ThresholdRegister 0 */ |
||
2242 | +// XRX200_BM_WRED_YTH_0_MINTH, /* Minimum Threshold */ |
||
2243 | +// XRX200_BM_WRED_YTH_1, /* WRED Yellow ThresholdRegister 1 */ |
||
2244 | +// XRX200_BM_WRED_YTH_1_MAXTH, /* Maximum Threshold */ |
||
2245 | +// XRX200_BM_WRED_GTH_0, /* WRED Green ThresholdRegister 0 */ |
||
2246 | +// XRX200_BM_WRED_GTH_0_MINTH, /* Minimum Threshold */ |
||
2247 | +// XRX200_BM_WRED_GTH_1, /* WRED Green ThresholdRegister 1 */ |
||
2248 | +// XRX200_BM_WRED_GTH_1_MAXTH, /* Maximum Threshold */ |
||
2249 | +// XRX200_BM_DROP_GTH_0_THR, /* Drop Threshold ConfigurationRegister 0 */ |
||
2250 | +// XRX200_BM_DROP_GTH_0_THR_FQ, /* Threshold for frames marked red */ |
||
2251 | +// XRX200_BM_DROP_GTH_1_THY, /* Drop Threshold ConfigurationRegister 1 */ |
||
2252 | +// XRX200_BM_DROP_GTH_1_THY_FQ, /* Threshold for frames marked yellow */ |
||
2253 | +// XRX200_BM_DROP_GTH_2_THG, /* Drop Threshold ConfigurationRegister 2 */ |
||
2254 | +// XRX200_BM_DROP_GTH_2_THG_FQ, /* Threshold for frames marked green */ |
||
2255 | +// XRX200_BM_IER, /* Buffer Manager Global InterruptEnable Register */ |
||
2256 | +// XRX200_BM_IER_CNT4, /* Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ |
||
2257 | +// XRX200_BM_IER_CNT3, /* Counter Group 3 (RMON-PQM) Interrupt Enable */ |
||
2258 | +// XRX200_BM_IER_CNT2, /* Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ |
||
2259 | +// XRX200_BM_IER_CNT1, /* Counter Group 1 (RMON-QFETCH) Interrupt Enable */ |
||
2260 | +// XRX200_BM_IER_CNT0, /* Counter Group 0 (RMON-QSTOR) Interrupt Enable */ |
||
2261 | +// XRX200_BM_IER_DEQ, /* PQM dequeue Interrupt Enable */ |
||
2262 | +// XRX200_BM_IER_ENQ, /* PQM Enqueue Interrupt Enable */ |
||
2263 | +// XRX200_BM_IER_FSQM, /* Buffer Empty Interrupt Enable */ |
||
2264 | +// XRX200_BM_ISR, /* Buffer Manager Global InterruptStatus Register */ |
||
2265 | +// XRX200_BM_ISR_CNT4, /* Counter Group 4 Interrupt */ |
||
2266 | +// XRX200_BM_ISR_CNT3, /* Counter Group 3 Interrupt */ |
||
2267 | +// XRX200_BM_ISR_CNT2, /* Counter Group 2 Interrupt */ |
||
2268 | +// XRX200_BM_ISR_CNT1, /* Counter Group 1 Interrupt */ |
||
2269 | +// XRX200_BM_ISR_CNT0, /* Counter Group 0 Interrupt */ |
||
2270 | +// XRX200_BM_ISR_DEQ, /* PQM dequeue Interrupt Enable */ |
||
2271 | +// XRX200_BM_ISR_ENQ, /* PQM Enqueue Interrupt */ |
||
2272 | +// XRX200_BM_ISR_FSQM, /* Buffer Empty Interrupt */ |
||
2273 | +// XRX200_BM_CISEL, /* Buffer Manager RMON CounterInterrupt Select Register */ |
||
2274 | +// XRX200_BM_CISEL_PORT, /* Port Number */ |
||
2275 | +// XRX200_BM_DEBUG_CTRL_DBG, /* Debug Control Register */ |
||
2276 | +// XRX200_BM_DEBUG_CTRL_DBG_SEL, /* Select Signal for Debug Multiplexer */ |
||
2277 | +// XRX200_BM_DEBUG_VAL_DBG, /* Debug Value Register */ |
||
2278 | +// XRX200_BM_DEBUG_VAL_DBG_DAT, /* Debug Data Value */ |
||
2279 | +// XRX200_BM_PCFG, /* Buffer Manager PortConfiguration Register */ |
||
2280 | +// XRX200_BM_PCFG_CNTEN, /* RMON Counter Enable */ |
||
2281 | +// XRX200_BM_RMON_CTRL_RAM1, /* Buffer ManagerRMON Control Register */ |
||
2282 | +// XRX200_BM_RMON_CTRL_RAM2_RES, /* Software Reset for RMON RAM2 */ |
||
2283 | +// XRX200_BM_RMON_CTRL_RAM1_RES, /* Software Reset for RMON RAM1 */ |
||
2284 | +// XRX200_PQM_DP, /* Packet Queue ManagerDrop Probability Register */ |
||
2285 | +// XRX200_PQM_DP_DPROB, /* Drop Probability Profile */ |
||
2286 | +// XRX200_PQM_RS, /* Packet Queue ManagerRate Shaper Assignment Register */ |
||
2287 | +// XRX200_PQM_RS_EN2, /* Rate Shaper 2 Enable */ |
||
2288 | +// XRX200_PQM_RS_RS2, /* Rate Shaper 2 */ |
||
2289 | +// XRX200_PQM_RS_EN1, /* Rate Shaper 1 Enable */ |
||
2290 | +// XRX200_PQM_RS_RS1, /* Rate Shaper 1 */ |
||
2291 | +// XRX200_RS_CTRL, /* Rate Shaper ControlRegister */ |
||
2292 | +// XRX200_RS_CTRL_RSEN, /* Rate Shaper Enable */ |
||
2293 | +// XRX200_RS_CBS, /* Rate Shaper CommittedBurst Size Register */ |
||
2294 | +// XRX200_RS_CBS_CBS, /* Committed Burst Size */ |
||
2295 | +// XRX200_RS_IBS, /* Rate Shaper InstantaneousBurst Size Register */ |
||
2296 | +// XRX200_RS_IBS_IBS, /* Instantaneous Burst Size */ |
||
2297 | +// XRX200_RS_CIR_EXP, /* Rate Shaper RateExponent Register */ |
||
2298 | +// XRX200_RS_CIR_EXP_EXP, /* Exponent */ |
||
2299 | +// XRX200_RS_CIR_MANT, /* Rate Shaper RateMantissa Register */ |
||
2300 | +// XRX200_RS_CIR_MANT_MANT, /* Mantissa */ |
||
2301 | + XRX200_PCE_TBL_KEY_7, /* Table Key Data 7 */ |
||
2302 | +// XRX200_PCE_TBL_KEY_7_KEY7, /* Key Value[15:0] */ |
||
2303 | + XRX200_PCE_TBL_KEY_6, /* Table Key Data 6 */ |
||
2304 | +// XRX200_PCE_TBL_KEY_6_KEY6, /* Key Value[15:0] */ |
||
2305 | + XRX200_PCE_TBL_KEY_5, /* Table Key Data 5 */ |
||
2306 | +// XRX200_PCE_TBL_KEY_5_KEY5, /* Key Value[15:0] */ |
||
2307 | + XRX200_PCE_TBL_KEY_4, /* Table Key Data 4 */ |
||
2308 | +// XRX200_PCE_TBL_KEY_4_KEY4, /* Key Value[15:0] */ |
||
2309 | + XRX200_PCE_TBL_KEY_3, /* Table Key Data 3 */ |
||
2310 | +// XRX200_PCE_TBL_KEY_3_KEY3, /* Key Value[15:0] */ |
||
2311 | + XRX200_PCE_TBL_KEY_2, /* Table Key Data 2 */ |
||
2312 | +// XRX200_PCE_TBL_KEY_2_KEY2, /* Key Value[15:0] */ |
||
2313 | + XRX200_PCE_TBL_KEY_1, /* Table Key Data 1 */ |
||
2314 | +// XRX200_PCE_TBL_KEY_1_KEY1, /* Key Value[31:16] */ |
||
2315 | + XRX200_PCE_TBL_KEY_0, /* Table Key Data 0 */ |
||
2316 | +// XRX200_PCE_TBL_KEY_0_KEY0, /* Key Value[15:0] */ |
||
2317 | + XRX200_PCE_TBL_MASK_0, /* Table Mask Write Register0 */ |
||
2318 | +// XRX200_PCE_TBL_MASK_0_MASK0, /* Mask Pattern [15:0] */ |
||
2319 | + XRX200_PCE_TBL_VAL_4, /* Table Value Register4 */ |
||
2320 | +// XRX200_PCE_TBL_VAL_4_VAL4, /* Data value [15:0] */ |
||
2321 | + XRX200_PCE_TBL_VAL_3, /* Table Value Register3 */ |
||
2322 | +// XRX200_PCE_TBL_VAL_3_VAL3, /* Data value [15:0] */ |
||
2323 | + XRX200_PCE_TBL_VAL_2, /* Table Value Register2 */ |
||
2324 | +// XRX200_PCE_TBL_VAL_2_VAL2, /* Data value [15:0] */ |
||
2325 | + XRX200_PCE_TBL_VAL_1, /* Table Value Register1 */ |
||
2326 | +// XRX200_PCE_TBL_VAL_1_VAL1, /* Data value [15:0] */ |
||
2327 | + XRX200_PCE_TBL_VAL_0, /* Table Value Register0 */ |
||
2328 | +// XRX200_PCE_TBL_VAL_0_VAL0, /* Data value [15:0] */ |
||
2329 | +// XRX200_PCE_TBL_ADDR, /* Table Entry AddressRegister */ |
||
2330 | + XRX200_PCE_TBL_ADDR_ADDR, /* Table Address */ |
||
2331 | +// XRX200_PCE_TBL_CTRL, /* Table Access ControlRegister */ |
||
2332 | + XRX200_PCE_TBL_CTRL_BAS, /* Access Busy/Access Start */ |
||
2333 | + XRX200_PCE_TBL_CTRL_TYPE, /* Lookup Entry Type */ |
||
2334 | + XRX200_PCE_TBL_CTRL_VLD, /* Lookup Entry Valid */ |
||
2335 | + XRX200_PCE_TBL_CTRL_GMAP, /* Group Map */ |
||
2336 | + XRX200_PCE_TBL_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ |
||
2337 | + XRX200_PCE_TBL_CTRL_ADDR, /* Lookup Table Address */ |
||
2338 | +// XRX200_PCE_TBL_STAT, /* Table General StatusRegister */ |
||
2339 | +// XRX200_PCE_TBL_STAT_TBUSY, /* Table Access Busy */ |
||
2340 | +// XRX200_PCE_TBL_STAT_TEMPT, /* Table Empty */ |
||
2341 | +// XRX200_PCE_TBL_STAT_TFUL, /* Table Full */ |
||
2342 | +// XRX200_PCE_AGE_0, /* Aging Counter ConfigurationRegister 0 */ |
||
2343 | +// XRX200_PCE_AGE_0_EXP, /* Aging Counter Exponent Value */ |
||
2344 | +// XRX200_PCE_AGE_1, /* Aging Counter ConfigurationRegister 1 */ |
||
2345 | +// XRX200_PCE_AGE_1_MANT, /* Aging Counter Mantissa Value */ |
||
2346 | +// XRX200_PCE_PMAP_1, /* Port Map Register 1 */ |
||
2347 | +// XRX200_PCE_PMAP_1_MPMAP, /* Monitoring Port Map */ |
||
2348 | +// XRX200_PCE_PMAP_2, /* Port Map Register 2 */ |
||
2349 | +// XRX200_PCE_PMAP_2_DMCPMAP, /* Default Multicast Port Map */ |
||
2350 | +// XRX200_PCE_PMAP_3, /* Port Map Register 3 */ |
||
2351 | +// XRX200_PCE_PMAP_3_UUCMAP, /* Default Unknown Unicast Port Map */ |
||
2352 | +// XRX200_PCE_GCTRL_0, /* PCE Global Control Register0 */ |
||
2353 | +// XRX200_PCE_GCTRL_0_IGMP, /* IGMP Mode Selection */ |
||
2354 | + XRX200_PCE_GCTRL_0_VLAN, /* VLAN-aware Switching */ |
||
2355 | +// XRX200_PCE_GCTRL_0_NOPM, /* No Port Map Forwarding */ |
||
2356 | +// XRX200_PCE_GCTRL_0_SCONUC, /* Unknown Unicast Storm Control */ |
||
2357 | +// XRX200_PCE_GCTRL_0_SCONMC, /* Multicast Storm Control */ |
||
2358 | +// XRX200_PCE_GCTRL_0_SCONBC, /* Broadcast Storm Control */ |
||
2359 | +// XRX200_PCE_GCTRL_0_SCONMOD, /* Storm Control Mode */ |
||
2360 | +// XRX200_PCE_GCTRL_0_SCONMET, /* Storm Control Metering Instance */ |
||
2361 | +// XRX200_PCE_GCTRL_0_MC_VALID, /* Access Request */ |
||
2362 | +// XRX200_PCE_GCTRL_0_PLCKMOD, /* Port Lock Mode */ |
||
2363 | +// XRX200_PCE_GCTRL_0_PLIMMOD, /* MAC Address Learning Limitation Mode */ |
||
2364 | +// XRX200_PCE_GCTRL_0_MTFL, /* MAC Table Flushing */ |
||
2365 | +// XRX200_PCE_GCTRL_1, /* PCE Global Control Register1 */ |
||
2366 | +// XRX200_PCE_GCTRL_1_PCE_DIS, /* PCE Disable after currently processed packet */ |
||
2367 | +// XRX200_PCE_GCTRL_1_LRNMOD, /* MAC Address Learning Mode */ |
||
2368 | +// XRX200_PCE_TCM_GLOB_CTRL, /* Three-color MarkerGlobal Control Register */ |
||
2369 | +// XRX200_PCE_TCM_GLOB_CTRL_DPRED, /* Re-marking Drop Precedence Red Encoding */ |
||
2370 | +// XRX200_PCE_TCM_GLOB_CTRL_DPYEL, /* Re-marking Drop Precedence Yellow Encoding */ |
||
2371 | +// XRX200_PCE_TCM_GLOB_CTRL_DPGRN, /* Re-marking Drop Precedence Green Encoding */ |
||
2372 | +// XRX200_PCE_IGMP_CTRL, /* IGMP Control Register */ |
||
2373 | +// XRX200_PCE_IGMP_CTRL_FAGEEN, /* Force Aging of Table Entries Enable */ |
||
2374 | +// XRX200_PCE_IGMP_CTRL_FLEAVE, /* Fast Leave Enable */ |
||
2375 | +// XRX200_PCE_IGMP_CTRL_DMRTEN, /* Default Maximum Response Time Enable */ |
||
2376 | +// XRX200_PCE_IGMP_CTRL_JASUP, /* Join Aggregation Suppression Enable */ |
||
2377 | +// XRX200_PCE_IGMP_CTRL_REPSUP, /* Report Suppression Enable */ |
||
2378 | +// XRX200_PCE_IGMP_CTRL_SRPEN, /* Snooping of Router Port Enable */ |
||
2379 | +// XRX200_PCE_IGMP_CTRL_ROB, /* Robustness Variable */ |
||
2380 | +// XRX200_PCE_IGMP_CTRL_DMRT, /* IGMP Default Maximum Response Time */ |
||
2381 | +// XRX200_PCE_IGMP_DRPM, /* IGMP Default RouterPort Map Register */ |
||
2382 | +// XRX200_PCE_IGMP_DRPM_DRPM, /* IGMP Default Router Port Map */ |
||
2383 | +// XRX200_PCE_IGMP_AGE_0, /* IGMP Aging Register0 */ |
||
2384 | +// XRX200_PCE_IGMP_AGE_0_MANT, /* IGMP Group Aging Time Mantissa */ |
||
2385 | +// XRX200_PCE_IGMP_AGE_0_EXP, /* IGMP Group Aging Time Exponent */ |
||
2386 | +// XRX200_PCE_IGMP_AGE_1, /* IGMP Aging Register1 */ |
||
2387 | +// XRX200_PCE_IGMP_AGE_1_MANT, /* IGMP Router Port Aging Time Mantissa */ |
||
2388 | +// XRX200_PCE_IGMP_STAT, /* IGMP Status Register */ |
||
2389 | +// XRX200_PCE_IGMP_STAT_IGPM, /* IGMP Port Map */ |
||
2390 | +// XRX200_WOL_GLB_CTRL, /* Wake-on-LAN ControlRegister */ |
||
2391 | +// XRX200_WOL_GLB_CTRL_PASSEN, /* WoL Password Enable */ |
||
2392 | +// XRX200_WOL_DA_0, /* Wake-on-LAN DestinationAddress Register 0 */ |
||
2393 | +// XRX200_WOL_DA_0_DA0, /* WoL Destination Address [15:0] */ |
||
2394 | +// XRX200_WOL_DA_1, /* Wake-on-LAN DestinationAddress Register 1 */ |
||
2395 | +// XRX200_WOL_DA_1_DA1, /* WoL Destination Address [31:16] */ |
||
2396 | +// XRX200_WOL_DA_2, /* Wake-on-LAN DestinationAddress Register 2 */ |
||
2397 | +// XRX200_WOL_DA_2_DA2, /* WoL Destination Address [47:32] */ |
||
2398 | +// XRX200_WOL_PW_0, /* Wake-on-LAN Password Register0 */ |
||
2399 | +// XRX200_WOL_PW_0_PW0, /* WoL Password [15:0] */ |
||
2400 | +// XRX200_WOL_PW_1, /* Wake-on-LAN Password Register1 */ |
||
2401 | +// XRX200_WOL_PW_1_PW1, /* WoL Password [31:16] */ |
||
2402 | +// XRX200_WOL_PW_2, /* Wake-on-LAN Password Register2 */ |
||
2403 | +// XRX200_WOL_PW_2_PW2, /* WoL Password [47:32] */ |
||
2404 | +// XRX200_PCE_IER_0_PINT, /* Parser and ClassificationEngine Global Interrupt Enable Register 0 */ |
||
2405 | +// XRX200_PCE_IER_0_PINT_15, /* Port Interrupt Enable */ |
||
2406 | +// XRX200_PCE_IER_0_PINT_14, /* Port Interrupt Enable */ |
||
2407 | +// XRX200_PCE_IER_0_PINT_13, /* Port Interrupt Enable */ |
||
2408 | +// XRX200_PCE_IER_0_PINT_12, /* Port Interrupt Enable */ |
||
2409 | +// XRX200_PCE_IER_0_PINT_11, /* Port Interrupt Enable */ |
||
2410 | +// XRX200_PCE_IER_0_PINT_10, /* Port Interrupt Enable */ |
||
2411 | +// XRX200_PCE_IER_0_PINT_9, /* Port Interrupt Enable */ |
||
2412 | +// XRX200_PCE_IER_0_PINT_8, /* Port Interrupt Enable */ |
||
2413 | +// XRX200_PCE_IER_0_PINT_7, /* Port Interrupt Enable */ |
||
2414 | +// XRX200_PCE_IER_0_PINT_6, /* Port Interrupt Enable */ |
||
2415 | +// XRX200_PCE_IER_0_PINT_5, /* Port Interrupt Enable */ |
||
2416 | +// XRX200_PCE_IER_0_PINT_4, /* Port Interrupt Enable */ |
||
2417 | +// XRX200_PCE_IER_0_PINT_3, /* Port Interrupt Enable */ |
||
2418 | +// XRX200_PCE_IER_0_PINT_2, /* Port Interrupt Enable */ |
||
2419 | +// XRX200_PCE_IER_0_PINT_1, /* Port Interrupt Enable */ |
||
2420 | +// XRX200_PCE_IER_0_PINT_0, /* Port Interrupt Enable */ |
||
2421 | +// XRX200_PCE_IER_1, /* Parser and ClassificationEngine Global Interrupt Enable Register 1 */ |
||
2422 | +// XRX200_PCE_IER_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched Interrupt Enable */ |
||
2423 | +// XRX200_PCE_IER_1_CPH2, /* Classification Phase 2 Ready Interrupt Enable */ |
||
2424 | +// XRX200_PCE_IER_1_CPH1, /* Classification Phase 1 Ready Interrupt Enable */ |
||
2425 | +// XRX200_PCE_IER_1_CPH0, /* Classification Phase 0 Ready Interrupt Enable */ |
||
2426 | +// XRX200_PCE_IER_1_PRDY, /* Parser Ready Interrupt Enable */ |
||
2427 | +// XRX200_PCE_IER_1_IGTF, /* IGMP Table Full Interrupt Enable */ |
||
2428 | +// XRX200_PCE_IER_1_MTF, /* MAC Table Full Interrupt Enable */ |
||
2429 | +// XRX200_PCE_ISR_0_PINT, /* Parser and ClassificationEngine Global Interrupt Status Register 0 */ |
||
2430 | +// XRX200_PCE_ISR_0_PINT_15, /* Port Interrupt */ |
||
2431 | +// XRX200_PCE_ISR_0_PINT_14, /* Port Interrupt */ |
||
2432 | +// XRX200_PCE_ISR_0_PINT_13, /* Port Interrupt */ |
||
2433 | +// XRX200_PCE_ISR_0_PINT_12, /* Port Interrupt */ |
||
2434 | +// XRX200_PCE_ISR_0_PINT_11, /* Port Interrupt */ |
||
2435 | +// XRX200_PCE_ISR_0_PINT_10, /* Port Interrupt */ |
||
2436 | +// XRX200_PCE_ISR_0_PINT_9, /* Port Interrupt */ |
||
2437 | +// XRX200_PCE_ISR_0_PINT_8, /* Port Interrupt */ |
||
2438 | +// XRX200_PCE_ISR_0_PINT_7, /* Port Interrupt */ |
||
2439 | +// XRX200_PCE_ISR_0_PINT_6, /* Port Interrupt */ |
||
2440 | +// XRX200_PCE_ISR_0_PINT_5, /* Port Interrupt */ |
||
2441 | +// XRX200_PCE_ISR_0_PINT_4, /* Port Interrupt */ |
||
2442 | +// XRX200_PCE_ISR_0_PINT_3, /* Port Interrupt */ |
||
2443 | +// XRX200_PCE_ISR_0_PINT_2, /* Port Interrupt */ |
||
2444 | +// XRX200_PCE_ISR_0_PINT_1, /* Port Interrupt */ |
||
2445 | +// XRX200_PCE_ISR_0_PINT_0, /* Port Interrupt */ |
||
2446 | +// XRX200_PCE_ISR_1, /* Parser and ClassificationEngine Global Interrupt Status Register 1 */ |
||
2447 | +// XRX200_PCE_ISR_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched */ |
||
2448 | +// XRX200_PCE_ISR_1_CPH2, /* Classification Phase 2 Ready Interrupt */ |
||
2449 | +// XRX200_PCE_ISR_1_CPH1, /* Classification Phase 1 Ready Interrupt */ |
||
2450 | +// XRX200_PCE_ISR_1_CPH0, /* Classification Phase 0 Ready Interrupt */ |
||
2451 | +// XRX200_PCE_ISR_1_PRDY, /* Parser Ready Interrupt */ |
||
2452 | +// XRX200_PCE_ISR_1_IGTF, /* IGMP Table Full Interrupt */ |
||
2453 | +// XRX200_PCE_ISR_1_MTF, /* MAC Table Full Interrupt */ |
||
2454 | +// XRX200_PARSER_STAT_FIFO, /* Parser Status Register */ |
||
2455 | +// XRX200_PARSER_STAT_FSM_DAT_CNT, /* Parser FSM Data Counter */ |
||
2456 | +// XRX200_PARSER_STAT_FSM_STATE, /* Parser FSM State */ |
||
2457 | +// XRX200_PARSER_STAT_PKT_ERR, /* Packet error detected */ |
||
2458 | +// XRX200_PARSER_STAT_FSM_FIN, /* Parser FSM finished */ |
||
2459 | +// XRX200_PARSER_STAT_FSM_START, /* Parser FSM start */ |
||
2460 | +// XRX200_PARSER_STAT_FIFO_RDY, /* Parser FIFO ready for read. */ |
||
2461 | +// XRX200_PARSER_STAT_FIFO_FULL, /* Parser */ |
||
2462 | +// XRX200_PCE_PCTRL_0, /* PCE Port ControlRegister 0 */ |
||
2463 | +// XRX200_PCE_PCTRL_0_MCST, /* Multicast Forwarding Mode Selection */ |
||
2464 | +// XRX200_PCE_PCTRL_0_EGSTEN, /* Table-based Egress Special Tag Enable */ |
||
2465 | +// XRX200_PCE_PCTRL_0_IGSTEN, /* Ingress Special Tag Enable */ |
||
2466 | +// XRX200_PCE_PCTRL_0_PCPEN, /* PCP Remarking Mode */ |
||
2467 | +// XRX200_PCE_PCTRL_0_CLPEN, /* Class Remarking Mode */ |
||
2468 | +// XRX200_PCE_PCTRL_0_DPEN, /* Drop Precedence Remarking Mode */ |
||
2469 | +// XRX200_PCE_PCTRL_0_CMOD, /* Three-color Marker Color Mode */ |
||
2470 | +// XRX200_PCE_PCTRL_0_VREP, /* VLAN Replacement Mode */ |
||
2471 | + XRX200_PCE_PCTRL_0_TVM, /* Transparent VLAN Mode */ |
||
2472 | +// XRX200_PCE_PCTRL_0_PLOCK, /* Port Locking Enable */ |
||
2473 | +// XRX200_PCE_PCTRL_0_AGEDIS, /* Aging Disable */ |
||
2474 | +// XRX200_PCE_PCTRL_0_PSTATE, /* Port State */ |
||
2475 | +// XRX200_PCE_PCTRL_1, /* PCE Port ControlRegister 1 */ |
||
2476 | +// XRX200_PCE_PCTRL_1_LRNLIM, /* MAC Address Learning Limit */ |
||
2477 | +// XRX200_PCE_PCTRL_2, /* PCE Port ControlRegister 2 */ |
||
2478 | +// XRX200_PCE_PCTRL_2_DSCPMOD, /* DSCP Mode Selection */ |
||
2479 | +// XRX200_PCE_PCTRL_2_DSCP, /* Enable DSCP to select the Class of Service */ |
||
2480 | +// XRX200_PCE_PCTRL_2_PCP, /* Enable VLAN PCP to select the Class of Service */ |
||
2481 | +// XRX200_PCE_PCTRL_2_PCLASS, /* Port-based Traffic Class */ |
||
2482 | +// XRX200_PCE_PCTRL_3_VIO, /* PCE Port ControlRegister 3 */ |
||
2483 | +// XRX200_PCE_PCTRL_3_EDIR, /* Egress Redirection Mode */ |
||
2484 | +// XRX200_PCE_PCTRL_3_RXDMIR, /* Receive Mirroring Enable for dropped frames */ |
||
2485 | +// XRX200_PCE_PCTRL_3_RXVMIR, /* Receive Mirroring Enable for valid frames */ |
||
2486 | +// XRX200_PCE_PCTRL_3_TXMIR, /* Transmit Mirroring Enable */ |
||
2487 | +// XRX200_PCE_PCTRL_3_VIO_7, /* Violation Type 7 Mirroring Enable */ |
||
2488 | +// XRX200_PCE_PCTRL_3_VIO_6, /* Violation Type 6 Mirroring Enable */ |
||
2489 | +// XRX200_PCE_PCTRL_3_VIO_5, /* Violation Type 5 Mirroring Enable */ |
||
2490 | +// XRX200_PCE_PCTRL_3_VIO_4, /* Violation Type 4 Mirroring Enable */ |
||
2491 | +// XRX200_PCE_PCTRL_3_VIO_3, /* Violation Type 3 Mirroring Enable */ |
||
2492 | +// XRX200_PCE_PCTRL_3_VIO_2, /* Violation Type 2 Mirroring Enable */ |
||
2493 | +// XRX200_PCE_PCTRL_3_VIO_1, /* Violation Type 1 Mirroring Enable */ |
||
2494 | +// XRX200_PCE_PCTRL_3_VIO_0, /* Violation Type 0 Mirroring Enable */ |
||
2495 | +// XRX200_WOL_CTRL, /* Wake-on-LAN ControlRegister */ |
||
2496 | +// XRX200_WOL_CTRL_PORT, /* WoL Enable */ |
||
2497 | +// XRX200_PCE_VCTRL, /* PCE VLAN ControlRegister */ |
||
2498 | + XRX200_PCE_VCTRL_VSR, /* VLAN Security Rule */ |
||
2499 | + XRX200_PCE_VCTRL_VEMR, /* VLAN Egress Member Violation Rule */ |
||
2500 | + XRX200_PCE_VCTRL_VIMR, /* VLAN Ingress Member Violation Rule */ |
||
2501 | + XRX200_PCE_VCTRL_VINR, /* VLAN Ingress Tag Rule */ |
||
2502 | + XRX200_PCE_VCTRL_UVR, /* Unknown VLAN Rule */ |
||
2503 | +// XRX200_PCE_DEFPVID, /* PCE Default PortVID Register */ |
||
2504 | + XRX200_PCE_DEFPVID_PVID, /* Default Port VID Index */ |
||
2505 | +// XRX200_PCE_PSTAT, /* PCE Port StatusRegister */ |
||
2506 | +// XRX200_PCE_PSTAT_LRNCNT, /* Learning Count */ |
||
2507 | +// XRX200_PCE_PIER, /* Parser and ClassificationEngine Port Interrupt Enable Register */ |
||
2508 | +// XRX200_PCE_PIER_CLDRP, /* Classification Drop Interrupt Enable */ |
||
2509 | +// XRX200_PCE_PIER_PTDRP, /* Port Drop Interrupt Enable */ |
||
2510 | +// XRX200_PCE_PIER_VLAN, /* VLAN Violation Interrupt Enable */ |
||
2511 | +// XRX200_PCE_PIER_WOL, /* Wake-on-LAN Interrupt Enable */ |
||
2512 | +// XRX200_PCE_PIER_LOCK, /* Port Limit Alert Interrupt Enable */ |
||
2513 | +// XRX200_PCE_PIER_LIM, /* Port Lock Alert Interrupt Enable */ |
||
2514 | +// XRX200_PCE_PISR, /* Parser and ClassificationEngine Port Interrupt Status Register */ |
||
2515 | +// XRX200_PCE_PISR_CLDRP, /* Classification Drop Interrupt */ |
||
2516 | +// XRX200_PCE_PISR_PTDRP, /* Port Drop Interrupt */ |
||
2517 | +// XRX200_PCE_PISR_VLAN, /* VLAN Violation Interrupt */ |
||
2518 | +// XRX200_PCE_PISR_WOL, /* Wake-on-LAN Interrupt */ |
||
2519 | +// XRX200_PCE_PISR_LOCK, /* Port Lock Alert Interrupt */ |
||
2520 | +// XRX200_PCE_PISR_LIMIT, /* Port Limitation Alert Interrupt */ |
||
2521 | +// XRX200_PCE_TCM_CTRL, /* Three-colorMarker Control Register */ |
||
2522 | +// XRX200_PCE_TCM_CTRL_TCMEN, /* Three-color Marker metering instance enable */ |
||
2523 | +// XRX200_PCE_TCM_STAT, /* Three-colorMarker Status Register */ |
||
2524 | +// XRX200_PCE_TCM_STAT_AL1, /* Three-color Marker Alert 1 Status */ |
||
2525 | +// XRX200_PCE_TCM_STAT_AL0, /* Three-color Marker Alert 0 Status */ |
||
2526 | +// XRX200_PCE_TCM_CBS, /* Three-color MarkerCommitted Burst Size Register */ |
||
2527 | +// XRX200_PCE_TCM_CBS_CBS, /* Committed Burst Size */ |
||
2528 | +// XRX200_PCE_TCM_EBS, /* Three-color MarkerExcess Burst Size Register */ |
||
2529 | +// XRX200_PCE_TCM_EBS_EBS, /* Excess Burst Size */ |
||
2530 | +// XRX200_PCE_TCM_IBS, /* Three-color MarkerInstantaneous Burst Size Register */ |
||
2531 | +// XRX200_PCE_TCM_IBS_IBS, /* Instantaneous Burst Size */ |
||
2532 | +// XRX200_PCE_TCM_CIR_MANT, /* Three-colorMarker Constant Information Rate Mantissa Register */ |
||
2533 | +// XRX200_PCE_TCM_CIR_MANT_MANT, /* Rate Counter Mantissa */ |
||
2534 | +// XRX200_PCE_TCM_CIR_EXP, /* Three-colorMarker Constant Information Rate Exponent Register */ |
||
2535 | +// XRX200_PCE_TCM_CIR_EXP_EXP, /* Rate Counter Exponent */ |
||
2536 | +// XRX200_MAC_TEST, /* MAC Test Register */ |
||
2537 | +// XRX200_MAC_TEST_JTP, /* Jitter Test Pattern */ |
||
2538 | +// XRX200_MAC_PFAD_CFG, /* MAC Pause FrameSource Address Configuration Register */ |
||
2539 | +// XRX200_MAC_PFAD_CFG_SAMOD, /* Source Address Mode */ |
||
2540 | +// XRX200_MAC_PFSA_0, /* Pause Frame SourceAddress Part 0 */ |
||
2541 | +// XRX200_MAC_PFSA_0_PFAD, /* Pause Frame Source Address Part 0 */ |
||
2542 | +// XRX200_MAC_PFSA_1, /* Pause Frame SourceAddress Part 1 */ |
||
2543 | +// XRX200_MAC_PFSA_1_PFAD, /* Pause Frame Source Address Part 1 */ |
||
2544 | +// XRX200_MAC_PFSA_2, /* Pause Frame SourceAddress Part 2 */ |
||
2545 | +// XRX200_MAC_PFSA_2_PFAD, /* Pause Frame Source Address Part 2 */ |
||
2546 | +// XRX200_MAC_FLEN, /* MAC Frame Length Register */ |
||
2547 | +// XRX200_MAC_FLEN_LEN, /* Maximum Frame Length */ |
||
2548 | +// XRX200_MAC_VLAN_ETYPE_0, /* MAC VLAN EthertypeRegister 0 */ |
||
2549 | +// XRX200_MAC_VLAN_ETYPE_0_OUTER, /* Ethertype */ |
||
2550 | +// XRX200_MAC_VLAN_ETYPE_1, /* MAC VLAN EthertypeRegister 1 */ |
||
2551 | +// XRX200_MAC_VLAN_ETYPE_1_INNER, /* Ethertype */ |
||
2552 | +// XRX200_MAC_IER, /* MAC Interrupt EnableRegister */ |
||
2553 | +// XRX200_MAC_IER_MACIEN, /* MAC Interrupt Enable */ |
||
2554 | +// XRX200_MAC_ISR, /* MAC Interrupt StatusRegister */ |
||
2555 | +// XRX200_MAC_ISR_MACINT, /* MAC Interrupt */ |
||
2556 | +// XRX200_MAC_PSTAT, /* MAC Port Status Register */ |
||
2557 | +// XRX200_MAC_PSTAT_PACT, /* PHY Active Status */ |
||
2558 | + XRX200_MAC_PSTAT_GBIT, /* Gigabit Speed Status */ |
||
2559 | + XRX200_MAC_PSTAT_MBIT, /* Megabit Speed Status */ |
||
2560 | + XRX200_MAC_PSTAT_FDUP, /* Full Duplex Status */ |
||
2561 | +// XRX200_MAC_PSTAT_RXPAU, /* Receive Pause Status */ |
||
2562 | +// XRX200_MAC_PSTAT_TXPAU, /* Transmit Pause Status */ |
||
2563 | +// XRX200_MAC_PSTAT_RXPAUEN, /* Receive Pause Enable Status */ |
||
2564 | +// XRX200_MAC_PSTAT_TXPAUEN, /* Transmit Pause Enable Status */ |
||
2565 | + XRX200_MAC_PSTAT_LSTAT, /* Link Status */ |
||
2566 | +// XRX200_MAC_PSTAT_CRS, /* Carrier Sense Status */ |
||
2567 | +// XRX200_MAC_PSTAT_TXLPI, /* Transmit Low-power Idle Status */ |
||
2568 | +// XRX200_MAC_PSTAT_RXLPI, /* Receive Low-power Idle Status */ |
||
2569 | +// XRX200_MAC_PISR, /* MAC Interrupt Status Register */ |
||
2570 | +// XRX200_MAC_PISR_PACT, /* PHY Active Status */ |
||
2571 | +// XRX200_MAC_PISR_SPEED, /* Megabit Speed Status */ |
||
2572 | +// XRX200_MAC_PISR_FDUP, /* Full Duplex Status */ |
||
2573 | +// XRX200_MAC_PISR_RXPAUEN, /* Receive Pause Enable Status */ |
||
2574 | +// XRX200_MAC_PISR_TXPAUEN, /* Transmit Pause Enable Status */ |
||
2575 | +// XRX200_MAC_PISR_LPIOFF, /* Receive Low-power Idle Mode is left */ |
||
2576 | +// XRX200_MAC_PISR_LPION, /* Receive Low-power Idle Mode is entered */ |
||
2577 | +// XRX200_MAC_PISR_JAM, /* Jam Status Detected */ |
||
2578 | +// XRX200_MAC_PISR_TOOSHORT, /* Too Short Frame Error Detected */ |
||
2579 | +// XRX200_MAC_PISR_TOOLONG, /* Too Long Frame Error Detected */ |
||
2580 | +// XRX200_MAC_PISR_LENERR, /* Length Mismatch Error Detected */ |
||
2581 | +// XRX200_MAC_PISR_FCSERR, /* Frame Checksum Error Detected */ |
||
2582 | +// XRX200_MAC_PISR_TXPAUSE, /* Pause Frame Transmitted */ |
||
2583 | +// XRX200_MAC_PISR_RXPAUSE, /* Pause Frame Received */ |
||
2584 | +// XRX200_MAC_PIER, /* MAC Interrupt Enable Register */ |
||
2585 | +// XRX200_MAC_PIER_PACT, /* PHY Active Status */ |
||
2586 | +// XRX200_MAC_PIER_SPEED, /* Megabit Speed Status */ |
||
2587 | +// XRX200_MAC_PIER_FDUP, /* Full Duplex Status */ |
||
2588 | +// XRX200_MAC_PIER_RXPAUEN, /* Receive Pause Enable Status */ |
||
2589 | +// XRX200_MAC_PIER_TXPAUEN, /* Transmit Pause Enable Status */ |
||
2590 | +// XRX200_MAC_PIER_LPIOFF, /* Low-power Idle Off Interrupt Mask */ |
||
2591 | +// XRX200_MAC_PIER_LPION, /* Low-power Idle On Interrupt Mask */ |
||
2592 | +// XRX200_MAC_PIER_JAM, /* Jam Status Interrupt Mask */ |
||
2593 | +// XRX200_MAC_PIER_TOOSHORT, /* Too Short Frame Error Interrupt Mask */ |
||
2594 | +// XRX200_MAC_PIER_TOOLONG, /* Too Long Frame Error Interrupt Mask */ |
||
2595 | +// XRX200_MAC_PIER_LENERR, /* Length Mismatch Error Interrupt Mask */ |
||
2596 | +// XRX200_MAC_PIER_FCSERR, /* Frame Checksum Error Interrupt Mask */ |
||
2597 | +// XRX200_MAC_PIER_TXPAUSE, /* Transmit Pause Frame Interrupt Mask */ |
||
2598 | +// XRX200_MAC_PIER_RXPAUSE, /* Receive Pause Frame Interrupt Mask */ |
||
2599 | +// XRX200_MAC_CTRL_0, /* MAC Control Register0 */ |
||
2600 | +// XRX200_MAC_CTRL_0_LCOL, /* Late Collision Control */ |
||
2601 | +// XRX200_MAC_CTRL_0_BM, /* Burst Mode Control */ |
||
2602 | +// XRX200_MAC_CTRL_0_APADEN, /* Automatic VLAN Padding Enable */ |
||
2603 | +// XRX200_MAC_CTRL_0_VPAD2EN, /* Stacked VLAN Padding Enable */ |
||
2604 | +// XRX200_MAC_CTRL_0_VPADEN, /* VLAN Padding Enable */ |
||
2605 | +// XRX200_MAC_CTRL_0_PADEN, /* Padding Enable */ |
||
2606 | +// XRX200_MAC_CTRL_0_FCS, /* Transmit FCS Control */ |
||
2607 | + XRX200_MAC_CTRL_0_FCON, /* Flow Control Mode */ |
||
2608 | +// XRX200_MAC_CTRL_0_FDUP, /* Full Duplex Control */ |
||
2609 | +// XRX200_MAC_CTRL_0_GMII, /* GMII/MII interface mode selection */ |
||
2610 | +// XRX200_MAC_CTRL_1, /* MAC Control Register1 */ |
||
2611 | +// XRX200_MAC_CTRL_1_SHORTPRE, /* Short Preamble Control */ |
||
2612 | +// XRX200_MAC_CTRL_1_IPG, /* Minimum Inter Packet Gap Size */ |
||
2613 | +// XRX200_MAC_CTRL_2, /* MAC Control Register2 */ |
||
2614 | +// XRX200_MAC_CTRL_2_MLEN, /* Maximum Untagged Frame Length */ |
||
2615 | +// XRX200_MAC_CTRL_2_LCHKL, /* Frame Length Check Long Enable */ |
||
2616 | +// XRX200_MAC_CTRL_2_LCHKS, /* Frame Length Check Short Enable */ |
||
2617 | +// XRX200_MAC_CTRL_3, /* MAC Control Register3 */ |
||
2618 | +// XRX200_MAC_CTRL_3_RCNT, /* Retry Count */ |
||
2619 | +// XRX200_MAC_CTRL_4, /* MAC Control Register4 */ |
||
2620 | +// XRX200_MAC_CTRL_4_LPIEN, /* LPI Mode Enable */ |
||
2621 | +// XRX200_MAC_CTRL_4_WAIT, /* LPI Wait Time */ |
||
2622 | +// XRX200_MAC_CTRL_5_PJPS, /* MAC Control Register5 */ |
||
2623 | +// XRX200_MAC_CTRL_5_PJPS_NOBP, /* Prolonged Jam pattern size during no-backpressure state */ |
||
2624 | +// XRX200_MAC_CTRL_5_PJPS_BP, /* Prolonged Jam pattern size during backpressure state */ |
||
2625 | +// XRX200_MAC_CTRL_6_XBUF, /* Transmit and ReceiveBuffer Control Register */ |
||
2626 | +// XRX200_MAC_CTRL_6_RBUF_DLY_WP, /* Delay */ |
||
2627 | +// XRX200_MAC_CTRL_6_RBUF_INIT, /* Receive Buffer Initialization */ |
||
2628 | +// XRX200_MAC_CTRL_6_RBUF_BYPASS, /* Bypass the Receive Buffer */ |
||
2629 | +// XRX200_MAC_CTRL_6_XBUF_DLY_WP, /* Delay */ |
||
2630 | +// XRX200_MAC_CTRL_6_XBUF_INIT, /* Initialize the Transmit Buffer */ |
||
2631 | +// XRX200_MAC_CTRL_6_XBUF_BYPASS, /* Bypass the Transmit Buffer */ |
||
2632 | +// XRX200_MAC_BUFST_XBUF, /* MAC Receive and TransmitBuffer Status Register */ |
||
2633 | +// XRX200_MAC_BUFST_RBUF_UFL, /* Receive Buffer Underflow Indicator */ |
||
2634 | +// XRX200_MAC_BUFST_RBUF_OFL, /* Receive Buffer Overflow Indicator */ |
||
2635 | +// XRX200_MAC_BUFST_XBUF_UFL, /* Transmit Buffer Underflow Indicator */ |
||
2636 | +// XRX200_MAC_BUFST_XBUF_OFL, /* Transmit Buffer Overflow Indicator */ |
||
2637 | +// XRX200_MAC_TESTEN, /* MAC Test Enable Register */ |
||
2638 | +// XRX200_MAC_TESTEN_JTEN, /* Jitter Test Enable */ |
||
2639 | +// XRX200_MAC_TESTEN_TXER, /* Transmit Error Insertion */ |
||
2640 | +// XRX200_MAC_TESTEN_LOOP, /* MAC Loopback Enable */ |
||
2641 | +// XRX200_FDMA_CTRL, /* Ethernet Switch FetchDMA Control Register */ |
||
2642 | +// XRX200_FDMA_CTRL_LPI_THRESHOLD, /* Low Power Idle Threshold */ |
||
2643 | +// XRX200_FDMA_CTRL_LPI_MODE, /* Low Power Idle Mode */ |
||
2644 | +// XRX200_FDMA_CTRL_EGSTAG, /* Egress Special Tag Size */ |
||
2645 | +// XRX200_FDMA_CTRL_IGSTAG, /* Ingress Special Tag Size */ |
||
2646 | +// XRX200_FDMA_CTRL_EXCOL, /* Excessive Collision Handling */ |
||
2647 | +// XRX200_FDMA_STETYPE, /* Special Tag EthertypeControl Register */ |
||
2648 | +// XRX200_FDMA_STETYPE_ETYPE, /* Special Tag Ethertype */ |
||
2649 | +// XRX200_FDMA_VTETYPE, /* VLAN Tag EthertypeControl Register */ |
||
2650 | +// XRX200_FDMA_VTETYPE_ETYPE, /* VLAN Tag Ethertype */ |
||
2651 | +// XRX200_FDMA_STAT_0, /* FDMA Status Register0 */ |
||
2652 | +// XRX200_FDMA_STAT_0_FSMS, /* FSM states status */ |
||
2653 | +// XRX200_FDMA_IER, /* Fetch DMA Global InterruptEnable Register */ |
||
2654 | +// XRX200_FDMA_IER_PCKD, /* Packet Drop Interrupt Enable */ |
||
2655 | +// XRX200_FDMA_IER_PCKR, /* Packet Ready Interrupt Enable */ |
||
2656 | +// XRX200_FDMA_IER_PCKT, /* Packet Sent Interrupt Enable */ |
||
2657 | +// XRX200_FDMA_ISR, /* Fetch DMA Global InterruptStatus Register */ |
||
2658 | +// XRX200_FDMA_ISR_PCKTD, /* Packet Drop */ |
||
2659 | +// XRX200_FDMA_ISR_PCKR, /* Packet is Ready for Transmission */ |
||
2660 | +// XRX200_FDMA_ISR_PCKT, /* Packet Sent Event */ |
||
2661 | +// XRX200_FDMA_PCTRL, /* Ethernet SwitchFetch DMA Port Control Register */ |
||
2662 | +// XRX200_FDMA_PCTRL_VLANMOD, /* VLAN Modification Enable */ |
||
2663 | +// XRX200_FDMA_PCTRL_DSCPRM, /* DSCP Re-marking Enable */ |
||
2664 | +// XRX200_FDMA_PCTRL_STEN, /* Special Tag Insertion Enable */ |
||
2665 | +// XRX200_FDMA_PCTRL_EN, /* FDMA Port Enable */ |
||
2666 | +// XRX200_FDMA_PRIO, /* Ethernet SwitchFetch DMA Port Priority Register */ |
||
2667 | +// XRX200_FDMA_PRIO_PRIO, /* FDMA PRIO */ |
||
2668 | +// XRX200_FDMA_PSTAT0, /* Ethernet SwitchFetch DMA Port Status Register 0 */ |
||
2669 | +// XRX200_FDMA_PSTAT0_PKT_AVAIL, /* Port Egress Packet Available */ |
||
2670 | +// XRX200_FDMA_PSTAT0_POK, /* Port Status OK */ |
||
2671 | +// XRX200_FDMA_PSTAT0_PSEG, /* Port Egress Segment Count */ |
||
2672 | +// XRX200_FDMA_PSTAT1_HDR, /* Ethernet SwitchFetch DMA Port Status Register 1 */ |
||
2673 | +// XRX200_FDMA_PSTAT1_HDR_PTR, /* Header Pointer */ |
||
2674 | +// XRX200_FDMA_TSTAMP0, /* Egress TimeStamp Register 0 */ |
||
2675 | +// XRX200_FDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ |
||
2676 | +// XRX200_FDMA_TSTAMP1, /* Egress TimeStamp Register 1 */ |
||
2677 | +// XRX200_FDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ |
||
2678 | +// XRX200_SDMA_CTRL, /* Ethernet Switch StoreDMA Control Register */ |
||
2679 | +// XRX200_SDMA_CTRL_TSTEN, /* Time Stamp Enable */ |
||
2680 | +// XRX200_SDMA_FCTHR1, /* SDMA Flow Control Threshold1 Register */ |
||
2681 | +// XRX200_SDMA_FCTHR1_THR1, /* Threshold 1 */ |
||
2682 | +// XRX200_SDMA_FCTHR2, /* SDMA Flow Control Threshold2 Register */ |
||
2683 | +// XRX200_SDMA_FCTHR2_THR2, /* Threshold 2 */ |
||
2684 | +// XRX200_SDMA_FCTHR3, /* SDMA Flow Control Threshold3 Register */ |
||
2685 | +// XRX200_SDMA_FCTHR3_THR3, /* Threshold 3 */ |
||
2686 | +// XRX200_SDMA_FCTHR4, /* SDMA Flow Control Threshold4 Register */ |
||
2687 | +// XRX200_SDMA_FCTHR4_THR4, /* Threshold 4 */ |
||
2688 | +// XRX200_SDMA_FCTHR5, /* SDMA Flow Control Threshold5 Register */ |
||
2689 | +// XRX200_SDMA_FCTHR5_THR5, /* Threshold 5 */ |
||
2690 | +// XRX200_SDMA_FCTHR6, /* SDMA Flow Control Threshold6 Register */ |
||
2691 | +// XRX200_SDMA_FCTHR6_THR6, /* Threshold 6 */ |
||
2692 | +// XRX200_SDMA_FCTHR7, /* SDMA Flow Control Threshold7 Register */ |
||
2693 | +// XRX200_SDMA_FCTHR7_THR7, /* Threshold 7 */ |
||
2694 | +// XRX200_SDMA_STAT_0, /* SDMA Status Register0 */ |
||
2695 | +// XRX200_SDMA_STAT_0_BPS_FILL, /* Back Pressure Status */ |
||
2696 | +// XRX200_SDMA_STAT_0_BPS_PNT, /* Back Pressure Status */ |
||
2697 | +// XRX200_SDMA_STAT_0_DROP, /* Back Pressure Status */ |
||
2698 | +// XRX200_SDMA_STAT_1, /* SDMA Status Register1 */ |
||
2699 | +// XRX200_SDMA_STAT_1_FILL, /* Buffer Filling Level */ |
||
2700 | +// XRX200_SDMA_STAT_2, /* SDMA Status Register2 */ |
||
2701 | +// XRX200_SDMA_STAT_2_FSMS, /* FSM states status */ |
||
2702 | +// XRX200_SDMA_IER, /* SDMA Interrupt Enable Register */ |
||
2703 | +// XRX200_SDMA_IER_BPEX, /* Buffer Pointers Exceeded */ |
||
2704 | +// XRX200_SDMA_IER_BFULL, /* Buffer Full */ |
||
2705 | +// XRX200_SDMA_IER_FERR, /* Frame Error */ |
||
2706 | +// XRX200_SDMA_IER_FRX, /* Frame Received Successfully */ |
||
2707 | +// XRX200_SDMA_ISR, /* SDMA Interrupt Status Register */ |
||
2708 | +// XRX200_SDMA_ISR_BPEX, /* Packet Descriptors Exceeded */ |
||
2709 | +// XRX200_SDMA_ISR_BFULL, /* Buffer Full */ |
||
2710 | +// XRX200_SDMA_ISR_FERR, /* Frame Error */ |
||
2711 | +// XRX200_SDMA_ISR_FRX, /* Frame Received Successfully */ |
||
2712 | +// XRX200_SDMA_PCTRL, /* Ethernet SwitchStore DMA Port Control Register */ |
||
2713 | +// XRX200_SDMA_PCTRL_DTHR, /* Drop Threshold Selection */ |
||
2714 | +// XRX200_SDMA_PCTRL_PTHR, /* Pause Threshold Selection */ |
||
2715 | +// XRX200_SDMA_PCTRL_PHYEFWD, /* Forward PHY Error Frames */ |
||
2716 | +// XRX200_SDMA_PCTRL_ALGFWD, /* Forward Alignment Error Frames */ |
||
2717 | +// XRX200_SDMA_PCTRL_LENFWD, /* Forward Length Errored Frames */ |
||
2718 | +// XRX200_SDMA_PCTRL_OSFWD, /* Forward Oversized Frames */ |
||
2719 | +// XRX200_SDMA_PCTRL_USFWD, /* Forward Undersized Frames */ |
||
2720 | +// XRX200_SDMA_PCTRL_FCSIGN, /* Ignore FCS Errors */ |
||
2721 | +// XRX200_SDMA_PCTRL_FCSFWD, /* Forward FCS Errored Frames */ |
||
2722 | +// XRX200_SDMA_PCTRL_PAUFWD, /* Pause Frame Forwarding */ |
||
2723 | +// XRX200_SDMA_PCTRL_MFCEN, /* Metering Flow Control Enable */ |
||
2724 | +// XRX200_SDMA_PCTRL_FCEN, /* Flow Control Enable */ |
||
2725 | +// XRX200_SDMA_PCTRL_PEN, /* Port Enable */ |
||
2726 | +// XRX200_SDMA_PRIO, /* Ethernet SwitchStore DMA Port Priority Register */ |
||
2727 | +// XRX200_SDMA_PRIO_PRIO, /* SDMA PRIO */ |
||
2728 | +// XRX200_SDMA_PSTAT0_HDR, /* Ethernet SwitchStore DMA Port Status Register 0 */ |
||
2729 | +// XRX200_SDMA_PSTAT0_HDR_PTR, /* Port Ingress Queue Header Pointer */ |
||
2730 | +// XRX200_SDMA_PSTAT1, /* Ethernet SwitchStore DMA Port Status Register 1 */ |
||
2731 | +// XRX200_SDMA_PSTAT1_PPKT, /* Port Ingress Packet Count */ |
||
2732 | +// XRX200_SDMA_TSTAMP0, /* Ingress TimeStamp Register 0 */ |
||
2733 | +// XRX200_SDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ |
||
2734 | +// XRX200_SDMA_TSTAMP1, /* Ingress TimeStamp Register 1 */ |
||
2735 | +// XRX200_SDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ |
||
2736 | +}; |
||
2737 | + |
||
2738 | + |
||
2739 | +struct xrx200sw_reg { |
||
2740 | + int offset; |
||
2741 | + int shift; |
||
2742 | + int size; |
||
2743 | + int mult; |
||
2744 | +} xrx200sw_reg[] = { |
||
2745 | +// offeset shift size mult |
||
2746 | +// {0x0000, 0, 16, 0x00}, /* XRX200_ETHSW_SWRES Ethernet Switch ResetControl Register */ |
||
2747 | +// {0x0000, 1, 1, 0x00}, /* XRX200_ETHSW_SWRES_R1 Hardware Reset */ |
||
2748 | +// {0x0000, 0, 1, 0x00}, /* XRX200_ETHSW_SWRES_R0 Register Configuration */ |
||
2749 | +// {0x0004, 0, 16, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT Ethernet Switch Clock ControlRegister */ |
||
2750 | +// {0x0004, 12, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_SLEEP Exponent to put system into sleep */ |
||
2751 | +// {0x0004, 8, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_WAKE Exponent to wake up system */ |
||
2752 | +// {0x0004, 7, 1, 0x00}, /* XRX200_ETHSW_CLK_CLK2_EN CLK2 Input for MAC */ |
||
2753 | +// {0x0004, 6, 1, 0x00}, /* XRX200_ETHSW_CLK_EXT_DIV_EN External Clock Divider Enable */ |
||
2754 | +// {0x0004, 5, 1, 0x00}, /* XRX200_ETHSW_CLK_RAM_DBG_EN Clock Gating Enable */ |
||
2755 | +// {0x0004, 4, 1, 0x00}, /* XRX200_ETHSW_CLK_REG_GAT_EN Clock Gating Enable */ |
||
2756 | +// {0x0004, 3, 1, 0x00}, /* XRX200_ETHSW_CLK_GAT_EN Clock Gating Enable */ |
||
2757 | +// {0x0004, 2, 1, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT_EN Clock Gating Enable */ |
||
2758 | +// {0x0008, 0, 16, 0x00}, /* XRX200_ETHSW_DBG_STEP Ethernet Switch Debug ControlRegister */ |
||
2759 | +// {0x0008, 12, 4, 0x00}, /* XRX200_ETHSW_DBG_CLK_SEL Trigger Enable */ |
||
2760 | +// {0x0008, 11, 1, 0x00}, /* XRX200_ETHSW_DBG_MON_EN Monitoring Enable */ |
||
2761 | +// {0x0008, 9, 2, 0x00}, /* XRX200_ETHSW_DBG_TRIG_EN Trigger Enable */ |
||
2762 | +// {0x0008, 8, 1, 0x00}, /* XRX200_ETHSW_DBG_MODE Debug Mode */ |
||
2763 | +// {0x0008, 0, 8, 0x00}, /* XRX200_ETHSW_DBG_STEP_TIME Clock Step Size */ |
||
2764 | +// {0x000C, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_MODE Ethernet Switch SharedSegment Buffer Mode Register */ |
||
2765 | +// {0x000C, 2, 4, 0x00}, /* XRX200_ETHSW_SSB_MODE_ADDE Memory Address */ |
||
2766 | +// {0x000C, 0, 2, 0x00}, /* XRX200_ETHSW_SSB_MODE_MODE Memory Access Mode */ |
||
2767 | +// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR Ethernet Switch SharedSegment Buffer Address Register */ |
||
2768 | +// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR_ADDE Memory Address */ |
||
2769 | +// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA Ethernet Switch SharedSegment Buffer Data Register */ |
||
2770 | +// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA_DATA Data Value */ |
||
2771 | +// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0 Ethernet Switch CapabilityRegister 0 */ |
||
2772 | +// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0_SPEED Clock frequency */ |
||
2773 | +// {0x001C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_1 Ethernet Switch CapabilityRegister 1 */ |
||
2774 | +// {0x001C, 15, 1, 0x00}, /* XRX200_ETHSW_CAP_1_GMAC MAC operation mode */ |
||
2775 | +// {0x001C, 8, 7, 0x00}, /* XRX200_ETHSW_CAP_1_QUEUE Number of queues */ |
||
2776 | +// {0x001C, 4, 4, 0x00}, /* XRX200_ETHSW_CAP_1_VPORTS Number of virtual ports */ |
||
2777 | +// {0x001C, 0, 4, 0x00}, /* XRX200_ETHSW_CAP_1_PPORTS Number of physical ports */ |
||
2778 | +// {0x0020, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_2 Ethernet Switch CapabilityRegister 2 */ |
||
2779 | +// {0x0020, 0, 11, 0x00}, /* XRX200_ETHSW_CAP_2_PACKETS Number of packets */ |
||
2780 | +// {0x0024, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_3 Ethernet Switch CapabilityRegister 3 */ |
||
2781 | +// {0x0024, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_3_METERS Number of traffic meters */ |
||
2782 | +// {0x0024, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_3_SHAPERS Number of traffic shapers */ |
||
2783 | +// {0x0028, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_4 Ethernet Switch CapabilityRegister 4 */ |
||
2784 | +// {0x0028, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_4_PPPOE PPPoE table size */ |
||
2785 | +// {0x0028, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_4_VLAN Active VLAN table size */ |
||
2786 | +// {0x002C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_5 Ethernet Switch CapabilityRegister 5 */ |
||
2787 | +// {0x002C, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_5_IPPLEN IP packet length table size */ |
||
2788 | +// {0x002C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_5_PROT Protocol table size */ |
||
2789 | +// {0x0030, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_6 Ethernet Switch CapabilityRegister 6 */ |
||
2790 | +// {0x0030, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_6_MACDASA MAC DA/SA table size */ |
||
2791 | +// {0x0030, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_6_APPL Application table size */ |
||
2792 | +// {0x0034, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_7 Ethernet Switch CapabilityRegister 7 */ |
||
2793 | +// {0x0034, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAM IP DA/SA MSB table size */ |
||
2794 | +// {0x0034, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAL IP DA/SA LSB table size */ |
||
2795 | +// {0x0038, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_8 Ethernet Switch CapabilityRegister 8 */ |
||
2796 | +// {0x0038, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_8_MCAST Multicast table size */ |
||
2797 | +// {0x003C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_9 Ethernet Switch CapabilityRegister 9 */ |
||
2798 | +// {0x003C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_9_FLAGG Flow Aggregation table size */ |
||
2799 | +// {0x0040, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_10 Ethernet Switch CapabilityRegister 10 */ |
||
2800 | +// {0x0040, 0, 13, 0x00}, /* XRX200_ETHSW_CAP_10_MACBT MAC bridging table size */ |
||
2801 | +// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11 Ethernet Switch CapabilityRegister 11 */ |
||
2802 | +// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11_BSIZEL Packet buffer size (lower part, in byte) */ |
||
2803 | +// {0x0048, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_12 Ethernet Switch CapabilityRegister 12 */ |
||
2804 | +// {0x0048, 0, 3, 0x00}, /* XRX200_ETHSW_CAP_12_BSIZEH Packet buffer size (higher part, in byte) */ |
||
2805 | +// {0x004C, 0, 16, 0x00}, /* XRX200_ETHSW_VERSION_REV Ethernet Switch VersionRegister */ |
||
2806 | +// {0x004C, 8, 8, 0x00}, /* XRX200_ETHSW_VERSION_MOD_ID Module Identification */ |
||
2807 | +// {0x004C, 0, 8, 0x00}, /* XRX200_ETHSW_VERSION_REV_ID Hardware Revision Identification */ |
||
2808 | +// {0x0050, 0, 16, 0x00}, /* XRX200_ETHSW_IER Interrupt Enable Register */ |
||
2809 | +// {0x0050, 4, 1, 0x00}, /* XRX200_ETHSW_IER_FDMAIE Fetch DMA Interrupt Enable */ |
||
2810 | +// {0x0050, 3, 1, 0x00}, /* XRX200_ETHSW_IER_SDMAIE Store DMA Interrupt Enable */ |
||
2811 | +// {0x0050, 2, 1, 0x00}, /* XRX200_ETHSW_IER_MACIE Ethernet MAC Interrupt Enable */ |
||
2812 | +// {0x0050, 1, 1, 0x00}, /* XRX200_ETHSW_IER_PCEIE Parser and Classification Engine Interrupt Enable */ |
||
2813 | +// {0x0050, 0, 1, 0x00}, /* XRX200_ETHSW_IER_BMIE Buffer Manager Interrupt Enable */ |
||
2814 | +// {0x0054, 0, 16, 0x00}, /* XRX200_ETHSW_ISR Interrupt Status Register */ |
||
2815 | +// {0x0054, 4, 1, 0x00}, /* XRX200_ETHSW_ISR_FDMAINT Fetch DMA Interrupt */ |
||
2816 | +// {0x0054, 3, 1, 0x00}, /* XRX200_ETHSW_ISR_SDMAINT Store DMA Interrupt */ |
||
2817 | +// {0x0054, 2, 1, 0x00}, /* XRX200_ETHSW_ISR_MACINT Ethernet MAC Interrupt */ |
||
2818 | +// {0x0054, 1, 1, 0x00}, /* XRX200_ETHSW_ISR_PCEINT Parser and Classification Engine Interrupt */ |
||
2819 | +// {0x0054, 0, 1, 0x00}, /* XRX200_ETHSW_ISR_BMINT Buffer Manager Interrupt */ |
||
2820 | +// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0 Ethernet Switch SpareCells 0 */ |
||
2821 | +// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0_SPARE SPARE0 */ |
||
2822 | +// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1 Ethernet Switch SpareCells 1 */ |
||
2823 | +// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1_SPARE SPARE1 */ |
||
2824 | +// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2 Ethernet Switch SpareCells 2 */ |
||
2825 | +// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2_SPARE SPARE2 */ |
||
2826 | +// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3 Ethernet Switch SpareCells 3 */ |
||
2827 | +// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3_SPARE SPARE3 */ |
||
2828 | +// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4 Ethernet Switch SpareCells 4 */ |
||
2829 | +// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4_SPARE SPARE4 */ |
||
2830 | +// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5 Ethernet Switch SpareCells 5 */ |
||
2831 | +// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5_SPARE SPARE5 */ |
||
2832 | +// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6 Ethernet Switch SpareCells 6 */ |
||
2833 | +// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6_SPARE SPARE6 */ |
||
2834 | +// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7 Ethernet Switch SpareCells 7 */ |
||
2835 | +// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7_SPARE SPARE7 */ |
||
2836 | +// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8 Ethernet Switch SpareCells 8 */ |
||
2837 | +// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8_SPARE SPARE8 */ |
||
2838 | +// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9 Ethernet Switch SpareCells 9 */ |
||
2839 | +// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9_SPARE SPARE9 */ |
||
2840 | +// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10 Ethernet Switch SpareCells 10 */ |
||
2841 | +// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10_SPARE SPARE10 */ |
||
2842 | +// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11 Ethernet Switch SpareCells 11 */ |
||
2843 | +// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11_SPARE SPARE11 */ |
||
2844 | +// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12 Ethernet Switch SpareCells 12 */ |
||
2845 | +// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12_SPARE SPARE12 */ |
||
2846 | +// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13 Ethernet Switch SpareCells 13 */ |
||
2847 | +// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13_SPARE SPARE13 */ |
||
2848 | +// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14 Ethernet Switch SpareCells 14 */ |
||
2849 | +// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14_SPARE SPARE14 */ |
||
2850 | +// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15 Ethernet Switch SpareCells 15 */ |
||
2851 | +// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15_SPARE SPARE15 */ |
||
2852 | +// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3 RAM Value Register 3 */ |
||
2853 | +// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3_VAL3 Data value [15:0] */ |
||
2854 | +// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2 RAM Value Register 2 */ |
||
2855 | +// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2_VAL2 Data value [15:0] */ |
||
2856 | +// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1 RAM Value Register 1 */ |
||
2857 | +// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1_VAL1 Data value [15:0] */ |
||
2858 | +// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0 RAM Value Register 0 */ |
||
2859 | +// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0_VAL0 Data value [15:0] */ |
||
2860 | +// {0x0110, 0, 16, 0x00}, /* XRX200_BM_RAM_ADDR RAM Address Register */ |
||
2861 | +// {0x0110, 0, 11, 0x00}, /* XRX200_BM_RAM_ADDR_ADDR RAM Address */ |
||
2862 | +// {0x0114, 0, 16, 0x00}, /* XRX200_BM_RAM_CTRL RAM Access Control Register */ |
||
2863 | +// {0x0114, 15, 1, 0x00}, /* XRX200_BM_RAM_CTRL_BAS Access Busy/Access Start */ |
||
2864 | +// {0x0114, 5, 1, 0x00}, /* XRX200_BM_RAM_CTRL_OPMOD Lookup Table Access Operation Mode */ |
||
2865 | +// {0x0114, 0, 5, 0x00}, /* XRX200_BM_RAM_CTRL_ADDR Address for RAM selection */ |
||
2866 | +// {0x0118, 0, 16, 0x00}, /* XRX200_BM_FSQM_GCTRL Free Segment Queue ManagerGlobal Control Register */ |
||
2867 | +// {0x0118, 0, 10, 0x00}, /* XRX200_BM_FSQM_GCTRL_SEGNUM Maximum Segment Number */ |
||
2868 | +// {0x011C, 0, 16, 0x00}, /* XRX200_BM_CONS_SEG Number of Consumed SegmentsRegister */ |
||
2869 | +// {0x011C, 0, 10, 0x00}, /* XRX200_BM_CONS_SEG_FSEG Number of Consumed Segments */ |
||
2870 | +// {0x0120, 0, 16, 0x00}, /* XRX200_BM_CONS_PKT Number of Consumed PacketPointers Register */ |
||
2871 | +// {0x0120, 0, 11, 0x00}, /* XRX200_BM_CONS_PKT_FQP Number of Consumed Packet Pointers */ |
||
2872 | +// {0x0124, 0, 16, 0x00}, /* XRX200_BM_GCTRL_F Buffer Manager Global ControlRegister 0 */ |
||
2873 | +// {0x0124, 13, 1, 0x00}, /* XRX200_BM_GCTRL_BM_STA Buffer Manager Initialization Status Bit */ |
||
2874 | +// {0x0124, 12, 1, 0x00}, /* XRX200_BM_GCTRL_SAT RMON Counter Update Mode */ |
||
2875 | +// {0x0124, 11, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RBC Freeze RMON RX Bad Byte 64 Bit Counter */ |
||
2876 | +// {0x0124, 10, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RGC Freeze RMON RX Good Byte 64 Bit Counter */ |
||
2877 | +// {0x0124, 9, 1, 0x00}, /* XRX200_BM_GCTRL_FR_TGC Freeze RMON TX Good Byte 64 Bit Counter */ |
||
2878 | +// {0x0124, 8, 1, 0x00}, /* XRX200_BM_GCTRL_I_FIN RAM initialization finished */ |
||
2879 | +// {0x0124, 7, 1, 0x00}, /* XRX200_BM_GCTRL_CX_INI PQM Context RAM initialization */ |
||
2880 | +// {0x0124, 6, 1, 0x00}, /* XRX200_BM_GCTRL_FP_INI FPQM RAM initialization */ |
||
2881 | +// {0x0124, 5, 1, 0x00}, /* XRX200_BM_GCTRL_FS_INI FSQM RAM initialization */ |
||
2882 | +// {0x0124, 4, 1, 0x00}, /* XRX200_BM_GCTRL_R_SRES Software Reset for RMON */ |
||
2883 | +// {0x0124, 3, 1, 0x00}, /* XRX200_BM_GCTRL_S_SRES Software Reset for Scheduler */ |
||
2884 | +// {0x0124, 2, 1, 0x00}, /* XRX200_BM_GCTRL_A_SRES Software Reset for AVG */ |
||
2885 | +// {0x0124, 1, 1, 0x00}, /* XRX200_BM_GCTRL_P_SRES Software Reset for PQM */ |
||
2886 | +// {0x0124, 0, 1, 0x00}, /* XRX200_BM_GCTRL_F_SRES Software Reset for FSQM */ |
||
2887 | +// {0x0128, 0, 16, 0x00}, /* XRX200_BM_QUEUE_GCTRL Queue Manager GlobalControl Register 0 */ |
||
2888 | + {0x0128, 10, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_GL_MOD WRED Mode Signal */ |
||
2889 | +// {0x0128, 7, 3, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQUI Average Queue Update Interval */ |
||
2890 | +// {0x0128, 3, 4, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQWF Average Queue Weight Factor */ |
||
2891 | +// {0x0128, 2, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_QAVGEN Queue Average Calculation Enable */ |
||
2892 | +// {0x0128, 0, 2, 0x00}, /* XRX200_BM_QUEUE_GCTRL_DPROB Drop Probability Profile */ |
||
2893 | +// {0x012C, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_0 WRED Red Threshold Register0 */ |
||
2894 | +// {0x012C, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_0_MINTH Minimum Threshold */ |
||
2895 | +// {0x0130, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_1 WRED Red Threshold Register1 */ |
||
2896 | +// {0x0130, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_1_MAXTH Maximum Threshold */ |
||
2897 | +// {0x0134, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_0 WRED Yellow ThresholdRegister 0 */ |
||
2898 | +// {0x0134, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_0_MINTH Minimum Threshold */ |
||
2899 | +// {0x0138, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_1 WRED Yellow ThresholdRegister 1 */ |
||
2900 | +// {0x0138, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_1_MAXTH Maximum Threshold */ |
||
2901 | +// {0x013C, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_0 WRED Green ThresholdRegister 0 */ |
||
2902 | +// {0x013C, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_0_MINTH Minimum Threshold */ |
||
2903 | +// {0x0140, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_1 WRED Green ThresholdRegister 1 */ |
||
2904 | +// {0x0140, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_1_MAXTH Maximum Threshold */ |
||
2905 | +// {0x0144, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_0_THR Drop Threshold ConfigurationRegister 0 */ |
||
2906 | +// {0x0144, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_0_THR_FQ Threshold for frames marked red */ |
||
2907 | +// {0x0148, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_1_THY Drop Threshold ConfigurationRegister 1 */ |
||
2908 | +// {0x0148, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_1_THY_FQ Threshold for frames marked yellow */ |
||
2909 | +// {0x014C, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_2_THG Drop Threshold ConfigurationRegister 2 */ |
||
2910 | +// {0x014C, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_2_THG_FQ Threshold for frames marked green */ |
||
2911 | +// {0x0150, 0, 16, 0x00}, /* XRX200_BM_IER Buffer Manager Global InterruptEnable Register */ |
||
2912 | +// {0x0150, 7, 1, 0x00}, /* XRX200_BM_IER_CNT4 Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ |
||
2913 | +// {0x0150, 6, 1, 0x00}, /* XRX200_BM_IER_CNT3 Counter Group 3 (RMON-PQM) Interrupt Enable */ |
||
2914 | +// {0x0150, 5, 1, 0x00}, /* XRX200_BM_IER_CNT2 Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ |
||
2915 | +// {0x0150, 4, 1, 0x00}, /* XRX200_BM_IER_CNT1 Counter Group 1 (RMON-QFETCH) Interrupt Enable */ |
||
2916 | +// {0x0150, 3, 1, 0x00}, /* XRX200_BM_IER_CNT0 Counter Group 0 (RMON-QSTOR) Interrupt Enable */ |
||
2917 | +// {0x0150, 2, 1, 0x00}, /* XRX200_BM_IER_DEQ PQM dequeue Interrupt Enable */ |
||
2918 | +// {0x0150, 1, 1, 0x00}, /* XRX200_BM_IER_ENQ PQM Enqueue Interrupt Enable */ |
||
2919 | +// {0x0150, 0, 1, 0x00}, /* XRX200_BM_IER_FSQM Buffer Empty Interrupt Enable */ |
||
2920 | +// {0x0154, 0, 16, 0x00}, /* XRX200_BM_ISR Buffer Manager Global InterruptStatus Register */ |
||
2921 | +// {0x0154, 7, 1, 0x00}, /* XRX200_BM_ISR_CNT4 Counter Group 4 Interrupt */ |
||
2922 | +// {0x0154, 6, 1, 0x00}, /* XRX200_BM_ISR_CNT3 Counter Group 3 Interrupt */ |
||
2923 | +// {0x0154, 5, 1, 0x00}, /* XRX200_BM_ISR_CNT2 Counter Group 2 Interrupt */ |
||
2924 | +// {0x0154, 4, 1, 0x00}, /* XRX200_BM_ISR_CNT1 Counter Group 1 Interrupt */ |
||
2925 | +// {0x0154, 3, 1, 0x00}, /* XRX200_BM_ISR_CNT0 Counter Group 0 Interrupt */ |
||
2926 | +// {0x0154, 2, 1, 0x00}, /* XRX200_BM_ISR_DEQ PQM dequeue Interrupt Enable */ |
||
2927 | +// {0x0154, 1, 1, 0x00}, /* XRX200_BM_ISR_ENQ PQM Enqueue Interrupt */ |
||
2928 | +// {0x0154, 0, 1, 0x00}, /* XRX200_BM_ISR_FSQM Buffer Empty Interrupt */ |
||
2929 | +// {0x0158, 0, 16, 0x00}, /* XRX200_BM_CISEL Buffer Manager RMON CounterInterrupt Select Register */ |
||
2930 | +// {0x0158, 0, 3, 0x00}, /* XRX200_BM_CISEL_PORT Port Number */ |
||
2931 | +// {0x015C, 0, 16, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG Debug Control Register */ |
||
2932 | +// {0x015C, 0, 8, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG_SEL Select Signal for Debug Multiplexer */ |
||
2933 | +// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG Debug Value Register */ |
||
2934 | +// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG_DAT Debug Data Value */ |
||
2935 | +// {0x0200, 0, 16, 0x08}, /* XRX200_BM_PCFG Buffer Manager PortConfiguration Register */ |
||
2936 | +// {0x0200, 0, 1, 0x08}, /* XRX200_BM_PCFG_CNTEN RMON Counter Enable */ |
||
2937 | +// {0x0204, 0, 16, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1 Buffer ManagerRMON Control Register */ |
||
2938 | +// {0x0204, 1, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM2_RES Software Reset for RMON RAM2 */ |
||
2939 | +// {0x0204, 0, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1_RES Software Reset for RMON RAM1 */ |
||
2940 | +// {0x0400, 0, 16, 0x08}, /* XRX200_PQM_DP Packet Queue ManagerDrop Probability Register */ |
||
2941 | +// {0x0400, 0, 2, 0x08}, /* XRX200_PQM_DP_DPROB Drop Probability Profile */ |
||
2942 | +// {0x0404, 0, 16, 0x08}, /* XRX200_PQM_RS Packet Queue ManagerRate Shaper Assignment Register */ |
||
2943 | +// {0x0404, 15, 1, 0x08}, /* XRX200_PQM_RS_EN2 Rate Shaper 2 Enable */ |
||
2944 | +// {0x0404, 8, 6, 0x08}, /* XRX200_PQM_RS_RS2 Rate Shaper 2 */ |
||
2945 | +// {0x0404, 7, 1, 0x08}, /* XRX200_PQM_RS_EN1 Rate Shaper 1 Enable */ |
||
2946 | +// {0x0404, 0, 6, 0x08}, /* XRX200_PQM_RS_RS1 Rate Shaper 1 */ |
||
2947 | +// {0x0500, 0, 16, 0x14}, /* XRX200_RS_CTRL Rate Shaper ControlRegister */ |
||
2948 | +// {0x0500, 0, 1, 0x14}, /* XRX200_RS_CTRL_RSEN Rate Shaper Enable */ |
||
2949 | +// {0x0504, 0, 16, 0x14}, /* XRX200_RS_CBS Rate Shaper CommittedBurst Size Register */ |
||
2950 | +// {0x0504, 0, 10, 0x14}, /* XRX200_RS_CBS_CBS Committed Burst Size */ |
||
2951 | +// {0x0508, 0, 16, 0x14}, /* XRX200_RS_IBS Rate Shaper InstantaneousBurst Size Register */ |
||
2952 | +// {0x0508, 0, 2, 0x14}, /* XRX200_RS_IBS_IBS Instantaneous Burst Size */ |
||
2953 | +// {0x050C, 0, 16, 0x14}, /* XRX200_RS_CIR_EXP Rate Shaper RateExponent Register */ |
||
2954 | +// {0x050C, 0, 4, 0x14}, /* XRX200_RS_CIR_EXP_EXP Exponent */ |
||
2955 | +// {0x0510, 0, 16, 0x14}, /* XRX200_RS_CIR_MANT Rate Shaper RateMantissa Register */ |
||
2956 | +// {0x0510, 0, 10, 0x14}, /* XRX200_RS_CIR_MANT_MANT Mantissa */ |
||
2957 | + {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7 Table Key Data 7 */ |
||
2958 | +// {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7_KEY7 Key Value[15:0] */ |
||
2959 | + {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6 Table Key Data 6 */ |
||
2960 | +// {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6_KEY6 Key Value[15:0] */ |
||
2961 | + {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5 Table Key Data 5 */ |
||
2962 | +// {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5_KEY5 Key Value[15:0] */ |
||
2963 | + {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4 Table Key Data 4 */ |
||
2964 | +// {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4_KEY4 Key Value[15:0] */ |
||
2965 | + {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3 Table Key Data 3 */ |
||
2966 | +// {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3_KEY3 Key Value[15:0] */ |
||
2967 | + {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2 Table Key Data 2 */ |
||
2968 | +// {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2_KEY2 Key Value[15:0] */ |
||
2969 | + {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1 Table Key Data 1 */ |
||
2970 | +// {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1_KEY1 Key Value[31:16] */ |
||
2971 | + {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0 Table Key Data 0 */ |
||
2972 | +// {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0_KEY0 Key Value[15:0] */ |
||
2973 | + {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0 Table Mask Write Register0 */ |
||
2974 | +// {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0_MASK0 Mask Pattern [15:0] */ |
||
2975 | + {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4 Table Value Register4 */ |
||
2976 | +// {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4_VAL4 Data value [15:0] */ |
||
2977 | + {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3 Table Value Register3 */ |
||
2978 | +// {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3_VAL3 Data value [15:0] */ |
||
2979 | + {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2 Table Value Register2 */ |
||
2980 | +// {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2_VAL2 Data value [15:0] */ |
||
2981 | + {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1 Table Value Register1 */ |
||
2982 | +// {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1_VAL1 Data value [15:0] */ |
||
2983 | + {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0 Table Value Register0 */ |
||
2984 | +// {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0_VAL0 Data value [15:0] */ |
||
2985 | +// {0x1138, 0, 16, 0x00}, /* XRX200_PCE_TBL_ADDR Table Entry AddressRegister */ |
||
2986 | + {0x1138, 0, 11, 0x00}, /* XRX200_PCE_TBL_ADDR_ADDR Table Address */ |
||
2987 | +// {0x113C, 0, 16, 0x00}, /* XRX200_PCE_TBL_CTRL Table Access ControlRegister */ |
||
2988 | + {0x113C, 15, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_BAS Access Busy/Access Start */ |
||
2989 | + {0x113C, 13, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_TYPE Lookup Entry Type */ |
||
2990 | + {0x113C, 12, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_VLD Lookup Entry Valid */ |
||
2991 | + {0x113C, 7, 4, 0x00}, /* XRX200_PCE_TBL_CTRL_GMAP Group Map */ |
||
2992 | + {0x113C, 5, 2, 0x00}, /* XRX200_PCE_TBL_CTRL_OPMOD Lookup Table Access Operation Mode */ |
||
2993 | + {0x113C, 0, 5, 0x00}, /* XRX200_PCE_TBL_CTRL_ADDR Lookup Table Address */ |
||
2994 | +// {0x1140, 0, 16, 0x00}, /* XRX200_PCE_TBL_STAT Table General StatusRegister */ |
||
2995 | +// {0x1140, 2, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TBUSY Table Access Busy */ |
||
2996 | +// {0x1140, 1, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TEMPT Table Empty */ |
||
2997 | +// {0x1140, 0, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TFUL Table Full */ |
||
2998 | +// {0x1144, 0, 16, 0x00}, /* XRX200_PCE_AGE_0 Aging Counter ConfigurationRegister 0 */ |
||
2999 | +// {0x1144, 0, 4, 0x00}, /* XRX200_PCE_AGE_0_EXP Aging Counter Exponent Value */ |
||
3000 | +// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1 Aging Counter ConfigurationRegister 1 */ |
||
3001 | +// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1_MANT Aging Counter Mantissa Value */ |
||
3002 | +// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1 Port Map Register 1 */ |
||
3003 | +// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1_MPMAP Monitoring Port Map */ |
||
3004 | +// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2 Port Map Register 2 */ |
||
3005 | +// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2_DMCPMAP Default Multicast Port Map */ |
||
3006 | +// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3 Port Map Register 3 */ |
||
3007 | +// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3_UUCMAP Default Unknown Unicast Port Map */ |
||
3008 | +// {0x1158, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_0 PCE Global Control Register0 */ |
||
3009 | +// {0x1158, 15, 1, 0x00}, /* XRX200_PCE_GCTRL_0_IGMP IGMP Mode Selection */ |
||
3010 | + {0x1158, 14, 1, 0x00}, /* XRX200_PCE_GCTRL_0_VLAN VLAN-aware Switching */ |
||
3011 | +// {0x1158, 13, 1, 0x00}, /* XRX200_PCE_GCTRL_0_NOPM No Port Map Forwarding */ |
||
3012 | +// {0x1158, 12, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONUC Unknown Unicast Storm Control */ |
||
3013 | +// {0x1158, 11, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMC Multicast Storm Control */ |
||
3014 | +// {0x1158, 10, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONBC Broadcast Storm Control */ |
||
3015 | +// {0x1158, 8, 2, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMOD Storm Control Mode */ |
||
3016 | +// {0x1158, 4, 4, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMET Storm Control Metering Instance */ |
||
3017 | +// {0x1158, 3, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MC_VALID Access Request */ |
||
3018 | +// {0x1158, 2, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLCKMOD Port Lock Mode */ |
||
3019 | +// {0x1158, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLIMMOD MAC Address Learning Limitation Mode */ |
||
3020 | +// {0x1158, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MTFL MAC Table Flushing */ |
||
3021 | +// {0x115C, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_1 PCE Global Control Register1 */ |
||
3022 | +// {0x115C, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_1_PCE_DIS PCE Disable after currently processed packet */ |
||
3023 | +// {0x115C, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_1_LRNMOD MAC Address Learning Mode */ |
||
3024 | +// {0x1160, 0, 16, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL Three-color MarkerGlobal Control Register */ |
||
3025 | +// {0x1160, 6, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPRED Re-marking Drop Precedence Red Encoding */ |
||
3026 | +// {0x1160, 3, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPYEL Re-marking Drop Precedence Yellow Encoding */ |
||
3027 | +// {0x1160, 0, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPGRN Re-marking Drop Precedence Green Encoding */ |
||
3028 | +// {0x1164, 0, 16, 0x00}, /* XRX200_PCE_IGMP_CTRL IGMP Control Register */ |
||
3029 | +// {0x1164, 15, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FAGEEN Force Aging of Table Entries Enable */ |
||
3030 | +// {0x1164, 14, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FLEAVE Fast Leave Enable */ |
||
3031 | +// {0x1164, 13, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRTEN Default Maximum Response Time Enable */ |
||
3032 | +// {0x1164, 12, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_JASUP Join Aggregation Suppression Enable */ |
||
3033 | +// {0x1164, 11, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_REPSUP Report Suppression Enable */ |
||
3034 | +// {0x1164, 10, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_SRPEN Snooping of Router Port Enable */ |
||
3035 | +// {0x1164, 8, 2, 0x00}, /* XRX200_PCE_IGMP_CTRL_ROB Robustness Variable */ |
||
3036 | +// {0x1164, 0, 8, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRT IGMP Default Maximum Response Time */ |
||
3037 | +// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM IGMP Default RouterPort Map Register */ |
||
3038 | +// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM_DRPM IGMP Default Router Port Map */ |
||
3039 | +// {0x116C, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_0 IGMP Aging Register0 */ |
||
3040 | +// {0x116C, 3, 8, 0x00}, /* XRX200_PCE_IGMP_AGE_0_MANT IGMP Group Aging Time Mantissa */ |
||
3041 | +// {0x116C, 0, 3, 0x00}, /* XRX200_PCE_IGMP_AGE_0_EXP IGMP Group Aging Time Exponent */ |
||
3042 | +// {0x1170, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_1 IGMP Aging Register1 */ |
||
3043 | +// {0x1170, 0, 12, 0x00}, /* XRX200_PCE_IGMP_AGE_1_MANT IGMP Router Port Aging Time Mantissa */ |
||
3044 | +// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT IGMP Status Register */ |
||
3045 | +// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT_IGPM IGMP Port Map */ |
||
3046 | +// {0x1178, 0, 16, 0x00}, /* XRX200_WOL_GLB_CTRL Wake-on-LAN ControlRegister */ |
||
3047 | +// {0x1178, 0, 1, 0x00}, /* XRX200_WOL_GLB_CTRL_PASSEN WoL Password Enable */ |
||
3048 | +// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0 Wake-on-LAN DestinationAddress Register 0 */ |
||
3049 | +// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0_DA0 WoL Destination Address [15:0] */ |
||
3050 | +// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1 Wake-on-LAN DestinationAddress Register 1 */ |
||
3051 | +// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1_DA1 WoL Destination Address [31:16] */ |
||
3052 | +// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2 Wake-on-LAN DestinationAddress Register 2 */ |
||
3053 | +// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2_DA2 WoL Destination Address [47:32] */ |
||
3054 | +// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0 Wake-on-LAN Password Register0 */ |
||
3055 | +// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0_PW0 WoL Password [15:0] */ |
||
3056 | +// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1 Wake-on-LAN Password Register1 */ |
||
3057 | +// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1_PW1 WoL Password [31:16] */ |
||
3058 | +// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2 Wake-on-LAN Password Register2 */ |
||
3059 | +// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2_PW2 WoL Password [47:32] */ |
||
3060 | +// {0x1194, 0, 16, 0x00}, /* XRX200_PCE_IER_0_PINT Parser and ClassificationEngine Global Interrupt Enable Register 0 */ |
||
3061 | +// {0x1194, 15, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_15 Port Interrupt Enable */ |
||
3062 | +// {0x1194, 14, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_14 Port Interrupt Enable */ |
||
3063 | +// {0x1194, 13, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_13 Port Interrupt Enable */ |
||
3064 | +// {0x1194, 12, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_12 Port Interrupt Enable */ |
||
3065 | +// {0x1194, 11, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_11 Port Interrupt Enable */ |
||
3066 | +// {0x1194, 10, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_10 Port Interrupt Enable */ |
||
3067 | +// {0x1194, 9, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_9 Port Interrupt Enable */ |
||
3068 | +// {0x1194, 8, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_8 Port Interrupt Enable */ |
||
3069 | +// {0x1194, 7, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_7 Port Interrupt Enable */ |
||
3070 | +// {0x1194, 6, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_6 Port Interrupt Enable */ |
||
3071 | +// {0x1194, 5, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_5 Port Interrupt Enable */ |
||
3072 | +// {0x1194, 4, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_4 Port Interrupt Enable */ |
||
3073 | +// {0x1194, 3, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_3 Port Interrupt Enable */ |
||
3074 | +// {0x1194, 2, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_2 Port Interrupt Enable */ |
||
3075 | +// {0x1194, 1, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_1 Port Interrupt Enable */ |
||
3076 | +// {0x1194, 0, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_0 Port Interrupt Enable */ |
||
3077 | +// {0x1198, 0, 16, 0x00}, /* XRX200_PCE_IER_1 Parser and ClassificationEngine Global Interrupt Enable Register 1 */ |
||
3078 | +// {0x1198, 6, 1, 0x00}, /* XRX200_PCE_IER_1_FLOWINT Traffic Flow Table Interrupt Rule matched Interrupt Enable */ |
||
3079 | +// {0x1198, 5, 1, 0x00}, /* XRX200_PCE_IER_1_CPH2 Classification Phase 2 Ready Interrupt Enable */ |
||
3080 | +// {0x1198, 4, 1, 0x00}, /* XRX200_PCE_IER_1_CPH1 Classification Phase 1 Ready Interrupt Enable */ |
||
3081 | +// {0x1198, 3, 1, 0x00}, /* XRX200_PCE_IER_1_CPH0 Classification Phase 0 Ready Interrupt Enable */ |
||
3082 | +// {0x1198, 2, 1, 0x00}, /* XRX200_PCE_IER_1_PRDY Parser Ready Interrupt Enable */ |
||
3083 | +// {0x1198, 1, 1, 0x00}, /* XRX200_PCE_IER_1_IGTF IGMP Table Full Interrupt Enable */ |
||
3084 | +// {0x1198, 0, 1, 0x00}, /* XRX200_PCE_IER_1_MTF MAC Table Full Interrupt Enable */ |
||
3085 | +// {0x119C, 0, 16, 0x00}, /* XRX200_PCE_ISR_0_PINT Parser and ClassificationEngine Global Interrupt Status Register 0 */ |
||
3086 | +// {0x119C, 15, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_15 Port Interrupt */ |
||
3087 | +// {0x119C, 14, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_14 Port Interrupt */ |
||
3088 | +// {0x119C, 13, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_13 Port Interrupt */ |
||
3089 | +// {0x119C, 12, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_12 Port Interrupt */ |
||
3090 | +// {0x119C, 11, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_11 Port Interrupt */ |
||
3091 | +// {0x119C, 10, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_10 Port Interrupt */ |
||
3092 | +// {0x119C, 9, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_9 Port Interrupt */ |
||
3093 | +// {0x119C, 8, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_8 Port Interrupt */ |
||
3094 | +// {0x119C, 7, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_7 Port Interrupt */ |
||
3095 | +// {0x119C, 6, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_6 Port Interrupt */ |
||
3096 | +// {0x119C, 5, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_5 Port Interrupt */ |
||
3097 | +// {0x119C, 4, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_4 Port Interrupt */ |
||
3098 | +// {0x119C, 3, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_3 Port Interrupt */ |
||
3099 | +// {0x119C, 2, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_2 Port Interrupt */ |
||
3100 | +// {0x119C, 1, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_1 Port Interrupt */ |
||
3101 | +// {0x119C, 0, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_0 Port Interrupt */ |
||
3102 | +// {0x11A0, 0, 16, 0x00}, /* XRX200_PCE_ISR_1 Parser and ClassificationEngine Global Interrupt Status Register 1 */ |
||
3103 | +// {0x11A0, 6, 1, 0x00}, /* XRX200_PCE_ISR_1_FLOWINT Traffic Flow Table Interrupt Rule matched */ |
||
3104 | +// {0x11A0, 5, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH2 Classification Phase 2 Ready Interrupt */ |
||
3105 | +// {0x11A0, 4, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH1 Classification Phase 1 Ready Interrupt */ |
||
3106 | +// {0x11A0, 3, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH0 Classification Phase 0 Ready Interrupt */ |
||
3107 | +// {0x11A0, 2, 1, 0x00}, /* XRX200_PCE_ISR_1_PRDY Parser Ready Interrupt */ |
||
3108 | +// {0x11A0, 1, 1, 0x00}, /* XRX200_PCE_ISR_1_IGTF IGMP Table Full Interrupt */ |
||
3109 | +// {0x11A0, 0, 1, 0x00}, /* XRX200_PCE_ISR_1_MTF MAC Table Full Interrupt */ |
||
3110 | +// {0x11A4, 0, 16, 0x00}, /* XRX200_PARSER_STAT_FIFO Parser Status Register */ |
||
3111 | +// {0x11A4, 8, 8, 0x00}, /* XRX200_PARSER_STAT_FSM_DAT_CNT Parser FSM Data Counter */ |
||
3112 | +// {0x11A4, 5, 3, 0x00}, /* XRX200_PARSER_STAT_FSM_STATE Parser FSM State */ |
||
3113 | +// {0x11A4, 4, 1, 0x00}, /* XRX200_PARSER_STAT_PKT_ERR Packet error detected */ |
||
3114 | +// {0x11A4, 3, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_FIN Parser FSM finished */ |
||
3115 | +// {0x11A4, 2, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_START Parser FSM start */ |
||
3116 | +// {0x11A4, 1, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_RDY Parser FIFO ready for read. */ |
||
3117 | +// {0x11A4, 0, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_FULL Parser */ |
||
3118 | +// {0x1200, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_0 PCE Port ControlRegister 0 */ |
||
3119 | +// {0x1200, 13, 1, 0x28}, /* XRX200_PCE_PCTRL_0_MCST Multicast Forwarding Mode Selection */ |
||
3120 | +// {0x1200, 12, 1, 0x28}, /* XRX200_PCE_PCTRL_0_EGSTEN Table-based Egress Special Tag Enable */ |
||
3121 | +// {0x1200, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_0_IGSTEN Ingress Special Tag Enable */ |
||
3122 | +// {0x1200, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PCPEN PCP Remarking Mode */ |
||
3123 | +// {0x1200, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CLPEN Class Remarking Mode */ |
||
3124 | +// {0x1200, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_0_DPEN Drop Precedence Remarking Mode */ |
||
3125 | +// {0x1200, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CMOD Three-color Marker Color Mode */ |
||
3126 | +// {0x1200, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_0_VREP VLAN Replacement Mode */ |
||
3127 | + {0x1200, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_0_TVM Transparent VLAN Mode */ |
||
3128 | +// {0x1200, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PLOCK Port Locking Enable */ |
||
3129 | +// {0x1200, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_0_AGEDIS Aging Disable */ |
||
3130 | +// {0x1200, 0, 3, 0x28}, /* XRX200_PCE_PCTRL_0_PSTATE Port State */ |
||
3131 | +// {0x1204, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_1 PCE Port ControlRegister 1 */ |
||
3132 | +// {0x1204, 0, 8, 0x28}, /* XRX200_PCE_PCTRL_1_LRNLIM MAC Address Learning Limit */ |
||
3133 | +// {0x1208, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_2 PCE Port ControlRegister 2 */ |
||
3134 | +// {0x1208, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_2_DSCPMOD DSCP Mode Selection */ |
||
3135 | +// {0x1208, 5, 2, 0x28}, /* XRX200_PCE_PCTRL_2_DSCP Enable DSCP to select the Class of Service */ |
||
3136 | +// {0x1208, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_2_PCP Enable VLAN PCP to select the Class of Service */ |
||
3137 | +// {0x1208, 0, 4, 0x28}, /* XRX200_PCE_PCTRL_2_PCLASS Port-based Traffic Class */ |
||
3138 | +// {0x120C, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_3_VIO PCE Port ControlRegister 3 */ |
||
3139 | +// {0x120C, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_3_EDIR Egress Redirection Mode */ |
||
3140 | +// {0x120C, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXDMIR Receive Mirroring Enable for dropped frames */ |
||
3141 | +// {0x120C, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXVMIR Receive Mirroring Enable for valid frames */ |
||
3142 | +// {0x120C, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_3_TXMIR Transmit Mirroring Enable */ |
||
3143 | +// {0x120C, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_7 Violation Type 7 Mirroring Enable */ |
||
3144 | +// {0x120C, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_6 Violation Type 6 Mirroring Enable */ |
||
3145 | +// {0x120C, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_5 Violation Type 5 Mirroring Enable */ |
||
3146 | +// {0x120C, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_4 Violation Type 4 Mirroring Enable */ |
||
3147 | +// {0x120C, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_3 Violation Type 3 Mirroring Enable */ |
||
3148 | +// {0x120C, 2, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_2 Violation Type 2 Mirroring Enable */ |
||
3149 | +// {0x120C, 1, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_1 Violation Type 1 Mirroring Enable */ |
||
3150 | +// {0x120C, 0, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_0 Violation Type 0 Mirroring Enable */ |
||
3151 | +// {0x1210, 0, 16, 0x28}, /* XRX200_WOL_CTRL Wake-on-LAN ControlRegister */ |
||
3152 | +// {0x1210, 0, 1, 0x28}, /* XRX200_WOL_CTRL_PORT WoL Enable */ |
||
3153 | +// {0x1214, 0, 16, 0x28}, /* XRX200_PCE_VCTRL PCE VLAN ControlRegister */ |
||
3154 | + {0x1214, 5, 1, 0x28}, /* XRX200_PCE_VCTRL_VSR VLAN Security Rule */ |
||
3155 | + {0x1214, 4, 1, 0x28}, /* XRX200_PCE_VCTRL_VEMR VLAN Egress Member Violation Rule */ |
||
3156 | + {0x1214, 3, 1, 0x28}, /* XRX200_PCE_VCTRL_VIMR VLAN Ingress Member Violation Rule */ |
||
3157 | + {0x1214, 1, 2, 0x28}, /* XRX200_PCE_VCTRL_VINR VLAN Ingress Tag Rule */ |
||
3158 | + {0x1214, 0, 1, 0x28}, /* XRX200_PCE_VCTRL_UVR Unknown VLAN Rule */ |
||
3159 | +// {0x1218, 0, 16, 0x28}, /* XRX200_PCE_DEFPVID PCE Default PortVID Register */ |
||
3160 | + {0x1218, 0, 6, 0x28}, /* XRX200_PCE_DEFPVID_PVID Default Port VID Index */ |
||
3161 | +// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT PCE Port StatusRegister */ |
||
3162 | +// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT_LRNCNT Learning Count */ |
||
3163 | +// {0x1220, 0, 16, 0x28}, /* XRX200_PCE_PIER Parser and ClassificationEngine Port Interrupt Enable Register */ |
||
3164 | +// {0x1220, 5, 1, 0x28}, /* XRX200_PCE_PIER_CLDRP Classification Drop Interrupt Enable */ |
||
3165 | +// {0x1220, 4, 1, 0x28}, /* XRX200_PCE_PIER_PTDRP Port Drop Interrupt Enable */ |
||
3166 | +// {0x1220, 3, 1, 0x28}, /* XRX200_PCE_PIER_VLAN VLAN Violation Interrupt Enable */ |
||
3167 | +// {0x1220, 2, 1, 0x28}, /* XRX200_PCE_PIER_WOL Wake-on-LAN Interrupt Enable */ |
||
3168 | +// {0x1220, 1, 1, 0x28}, /* XRX200_PCE_PIER_LOCK Port Limit Alert Interrupt Enable */ |
||
3169 | +// {0x1220, 0, 1, 0x28}, /* XRX200_PCE_PIER_LIM Port Lock Alert Interrupt Enable */ |
||
3170 | +// {0x1224, 0, 16, 0x28}, /* XRX200_PCE_PISR Parser and ClassificationEngine Port Interrupt Status Register */ |
||
3171 | +// {0x1224, 5, 1, 0x28}, /* XRX200_PCE_PISR_CLDRP Classification Drop Interrupt */ |
||
3172 | +// {0x1224, 4, 1, 0x28}, /* XRX200_PCE_PISR_PTDRP Port Drop Interrupt */ |
||
3173 | +// {0x1224, 3, 1, 0x28}, /* XRX200_PCE_PISR_VLAN VLAN Violation Interrupt */ |
||
3174 | +// {0x1224, 2, 1, 0x28}, /* XRX200_PCE_PISR_WOL Wake-on-LAN Interrupt */ |
||
3175 | +// {0x1224, 1, 1, 0x28}, /* XRX200_PCE_PISR_LOCK Port Lock Alert Interrupt */ |
||
3176 | +// {0x1224, 0, 1, 0x28}, /* XRX200_PCE_PISR_LIMIT Port Limitation Alert Interrupt */ |
||
3177 | +// {0x1600, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CTRL Three-colorMarker Control Register */ |
||
3178 | +// {0x1600, 0, 1, 0x1c}, /* XRX200_PCE_TCM_CTRL_TCMEN Three-color Marker metering instance enable */ |
||
3179 | +// {0x1604, 0, 16, 0x1c}, /* XRX200_PCE_TCM_STAT Three-colorMarker Status Register */ |
||
3180 | +// {0x1604, 1, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL1 Three-color Marker Alert 1 Status */ |
||
3181 | +// {0x1604, 0, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL0 Three-color Marker Alert 0 Status */ |
||
3182 | +// {0x1608, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CBS Three-color MarkerCommitted Burst Size Register */ |
||
3183 | +// {0x1608, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CBS_CBS Committed Burst Size */ |
||
3184 | +// {0x160C, 0, 16, 0x1c}, /* XRX200_PCE_TCM_EBS Three-color MarkerExcess Burst Size Register */ |
||
3185 | +// {0x160C, 0, 10, 0x1c}, /* XRX200_PCE_TCM_EBS_EBS Excess Burst Size */ |
||
3186 | +// {0x1610, 0, 16, 0x1c}, /* XRX200_PCE_TCM_IBS Three-color MarkerInstantaneous Burst Size Register */ |
||
3187 | +// {0x1610, 0, 2, 0x1c}, /* XRX200_PCE_TCM_IBS_IBS Instantaneous Burst Size */ |
||
3188 | +// {0x1614, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT Three-colorMarker Constant Information Rate Mantissa Register */ |
||
3189 | +// {0x1614, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT_MANT Rate Counter Mantissa */ |
||
3190 | +// {0x1618, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP Three-colorMarker Constant Information Rate Exponent Register */ |
||
3191 | +// {0x1618, 0, 4, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP_EXP Rate Counter Exponent */ |
||
3192 | +// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST MAC Test Register */ |
||
3193 | +// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST_JTP Jitter Test Pattern */ |
||
3194 | +// {0x2304, 0, 16, 0x00}, /* XRX200_MAC_PFAD_CFG MAC Pause FrameSource Address Configuration Register */ |
||
3195 | +// {0x2304, 0, 1, 0x00}, /* XRX200_MAC_PFAD_CFG_SAMOD Source Address Mode */ |
||
3196 | +// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0 Pause Frame SourceAddress Part 0 */ |
||
3197 | +// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0_PFAD Pause Frame Source Address Part 0 */ |
||
3198 | +// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1 Pause Frame SourceAddress Part 1 */ |
||
3199 | +// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1_PFAD Pause Frame Source Address Part 1 */ |
||
3200 | +// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2 Pause Frame SourceAddress Part 2 */ |
||
3201 | +// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2_PFAD Pause Frame Source Address Part 2 */ |
||
3202 | +// {0x2314, 0, 16, 0x00}, /* XRX200_MAC_FLEN MAC Frame Length Register */ |
||
3203 | +// {0x2314, 0, 14, 0x00}, /* XRX200_MAC_FLEN_LEN Maximum Frame Length */ |
||
3204 | +// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0 MAC VLAN EthertypeRegister 0 */ |
||
3205 | +// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0_OUTER Ethertype */ |
||
3206 | +// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1 MAC VLAN EthertypeRegister 1 */ |
||
3207 | +// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1_INNER Ethertype */ |
||
3208 | +// {0x2320, 0, 16, 0x00}, /* XRX200_MAC_IER MAC Interrupt EnableRegister */ |
||
3209 | +// {0x2320, 0, 8, 0x00}, /* XRX200_MAC_IER_MACIEN MAC Interrupt Enable */ |
||
3210 | +// {0x2324, 0, 16, 0x00}, /* XRX200_MAC_ISR MAC Interrupt StatusRegister */ |
||
3211 | +// {0x2324, 0, 8, 0x00}, /* XRX200_MAC_ISR_MACINT MAC Interrupt */ |
||
3212 | +// {0x2400, 0, 16, 0x30}, /* XRX200_MAC_PSTAT MAC Port Status Register */ |
||
3213 | +// {0x2400, 11, 1, 0x30}, /* XRX200_MAC_PSTAT_PACT PHY Active Status */ |
||
3214 | + {0x2400, 10, 1, 0x30}, /* XRX200_MAC_PSTAT_GBIT Gigabit Speed Status */ |
||
3215 | + {0x2400, 9, 1, 0x30}, /* XRX200_MAC_PSTAT_MBIT Megabit Speed Status */ |
||
3216 | + {0x2400, 8, 1, 0x30}, /* XRX200_MAC_PSTAT_FDUP Full Duplex Status */ |
||
3217 | +// {0x2400, 7, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAU Receive Pause Status */ |
||
3218 | +// {0x2400, 6, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAU Transmit Pause Status */ |
||
3219 | +// {0x2400, 5, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAUEN Receive Pause Enable Status */ |
||
3220 | +// {0x2400, 4, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAUEN Transmit Pause Enable Status */ |
||
3221 | + {0x2400, 3, 1, 0x30}, /* XRX200_MAC_PSTAT_LSTAT Link Status */ |
||
3222 | +// {0x2400, 2, 1, 0x30}, /* XRX200_MAC_PSTAT_CRS Carrier Sense Status */ |
||
3223 | +// {0x2400, 1, 1, 0x30}, /* XRX200_MAC_PSTAT_TXLPI Transmit Low-power Idle Status */ |
||
3224 | +// {0x2400, 0, 1, 0x30}, /* XRX200_MAC_PSTAT_RXLPI Receive Low-power Idle Status */ |
||
3225 | +// {0x2404, 0, 16, 0x30}, /* XRX200_MAC_PISR MAC Interrupt Status Register */ |
||
3226 | +// {0x2404, 13, 1, 0x30}, /* XRX200_MAC_PISR_PACT PHY Active Status */ |
||
3227 | +// {0x2404, 12, 1, 0x30}, /* XRX200_MAC_PISR_SPEED Megabit Speed Status */ |
||
3228 | +// {0x2404, 11, 1, 0x30}, /* XRX200_MAC_PISR_FDUP Full Duplex Status */ |
||
3229 | +// {0x2404, 10, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUEN Receive Pause Enable Status */ |
||
3230 | +// {0x2404, 9, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUEN Transmit Pause Enable Status */ |
||
3231 | +// {0x2404, 8, 1, 0x30}, /* XRX200_MAC_PISR_LPIOFF Receive Low-power Idle Mode is left */ |
||
3232 | +// {0x2404, 7, 1, 0x30}, /* XRX200_MAC_PISR_LPION Receive Low-power Idle Mode is entered */ |
||
3233 | +// {0x2404, 6, 1, 0x30}, /* XRX200_MAC_PISR_JAM Jam Status Detected */ |
||
3234 | +// {0x2404, 5, 1, 0x30}, /* XRX200_MAC_PISR_TOOSHORT Too Short Frame Error Detected */ |
||
3235 | +// {0x2404, 4, 1, 0x30}, /* XRX200_MAC_PISR_TOOLONG Too Long Frame Error Detected */ |
||
3236 | +// {0x2404, 3, 1, 0x30}, /* XRX200_MAC_PISR_LENERR Length Mismatch Error Detected */ |
||
3237 | +// {0x2404, 2, 1, 0x30}, /* XRX200_MAC_PISR_FCSERR Frame Checksum Error Detected */ |
||
3238 | +// {0x2404, 1, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUSE Pause Frame Transmitted */ |
||
3239 | +// {0x2404, 0, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUSE Pause Frame Received */ |
||
3240 | +// {0x2408, 0, 16, 0x30}, /* XRX200_MAC_PIER MAC Interrupt Enable Register */ |
||
3241 | +// {0x2408, 13, 1, 0x30}, /* XRX200_MAC_PIER_PACT PHY Active Status */ |
||
3242 | +// {0x2408, 12, 1, 0x30}, /* XRX200_MAC_PIER_SPEED Megabit Speed Status */ |
||
3243 | +// {0x2408, 11, 1, 0x30}, /* XRX200_MAC_PIER_FDUP Full Duplex Status */ |
||
3244 | +// {0x2408, 10, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUEN Receive Pause Enable Status */ |
||
3245 | +// {0x2408, 9, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUEN Transmit Pause Enable Status */ |
||
3246 | +// {0x2408, 8, 1, 0x30}, /* XRX200_MAC_PIER_LPIOFF Low-power Idle Off Interrupt Mask */ |
||
3247 | +// {0x2408, 7, 1, 0x30}, /* XRX200_MAC_PIER_LPION Low-power Idle On Interrupt Mask */ |
||
3248 | +// {0x2408, 6, 1, 0x30}, /* XRX200_MAC_PIER_JAM Jam Status Interrupt Mask */ |
||
3249 | +// {0x2408, 5, 1, 0x30}, /* XRX200_MAC_PIER_TOOSHORT Too Short Frame Error Interrupt Mask */ |
||
3250 | +// {0x2408, 4, 1, 0x30}, /* XRX200_MAC_PIER_TOOLONG Too Long Frame Error Interrupt Mask */ |
||
3251 | +// {0x2408, 3, 1, 0x30}, /* XRX200_MAC_PIER_LENERR Length Mismatch Error Interrupt Mask */ |
||
3252 | +// {0x2408, 2, 1, 0x30}, /* XRX200_MAC_PIER_FCSERR Frame Checksum Error Interrupt Mask */ |
||
3253 | +// {0x2408, 1, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUSE Transmit Pause Frame Interrupt Mask */ |
||
3254 | +// {0x2408, 0, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUSE Receive Pause Frame Interrupt Mask */ |
||
3255 | +// {0x240C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_0 MAC Control Register0 */ |
||
3256 | +// {0x240C, 13, 2, 0x30}, /* XRX200_MAC_CTRL_0_LCOL Late Collision Control */ |
||
3257 | +// {0x240C, 12, 1, 0x30}, /* XRX200_MAC_CTRL_0_BM Burst Mode Control */ |
||
3258 | +// {0x240C, 11, 1, 0x30}, /* XRX200_MAC_CTRL_0_APADEN Automatic VLAN Padding Enable */ |
||
3259 | +// {0x240C, 10, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPAD2EN Stacked VLAN Padding Enable */ |
||
3260 | +// {0x240C, 9, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPADEN VLAN Padding Enable */ |
||
3261 | +// {0x240C, 8, 1, 0x30}, /* XRX200_MAC_CTRL_0_PADEN Padding Enable */ |
||
3262 | +// {0x240C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_0_FCS Transmit FCS Control */ |
||
3263 | + {0x240C, 4, 3, 0x30}, /* XRX200_MAC_CTRL_0_FCON Flow Control Mode */ |
||
3264 | +// {0x240C, 2, 2, 0x30}, /* XRX200_MAC_CTRL_0_FDUP Full Duplex Control */ |
||
3265 | +// {0x240C, 0, 2, 0x30}, /* XRX200_MAC_CTRL_0_GMII GMII/MII interface mode selection */ |
||
3266 | +// {0x2410, 0, 16, 0x30}, /* XRX200_MAC_CTRL_1 MAC Control Register1 */ |
||
3267 | +// {0x2410, 8, 1, 0x30}, /* XRX200_MAC_CTRL_1_SHORTPRE Short Preamble Control */ |
||
3268 | +// {0x2410, 0, 4, 0x30}, /* XRX200_MAC_CTRL_1_IPG Minimum Inter Packet Gap Size */ |
||
3269 | +// {0x2414, 0, 16, 0x30}, /* XRX200_MAC_CTRL_2 MAC Control Register2 */ |
||
3270 | +// {0x2414, 3, 1, 0x30}, /* XRX200_MAC_CTRL_2_MLEN Maximum Untagged Frame Length */ |
||
3271 | +// {0x2414, 2, 1, 0x30}, /* XRX200_MAC_CTRL_2_LCHKL Frame Length Check Long Enable */ |
||
3272 | +// {0x2414, 0, 2, 0x30}, /* XRX200_MAC_CTRL_2_LCHKS Frame Length Check Short Enable */ |
||
3273 | +// {0x2418, 0, 16, 0x30}, /* XRX200_MAC_CTRL_3 MAC Control Register3 */ |
||
3274 | +// {0x2418, 0, 4, 0x30}, /* XRX200_MAC_CTRL_3_RCNT Retry Count */ |
||
3275 | +// {0x241C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_4 MAC Control Register4 */ |
||
3276 | +// {0x241C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_4_LPIEN LPI Mode Enable */ |
||
3277 | +// {0x241C, 0, 7, 0x30}, /* XRX200_MAC_CTRL_4_WAIT LPI Wait Time */ |
||
3278 | +// {0x2420, 0, 16, 0x30}, /* XRX200_MAC_CTRL_5_PJPS MAC Control Register5 */ |
||
3279 | +// {0x2420, 1, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_NOBP Prolonged Jam pattern size during no-backpressure state */ |
||
3280 | +// {0x2420, 0, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_BP Prolonged Jam pattern size during backpressure state */ |
||
3281 | +// {0x2424, 0, 16, 0x30}, /* XRX200_MAC_CTRL_6_XBUF Transmit and ReceiveBuffer Control Register */ |
||
3282 | +// {0x2424, 9, 3, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_DLY_WP Delay */ |
||
3283 | +// {0x2424, 8, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_INIT Receive Buffer Initialization */ |
||
3284 | +// {0x2424, 6, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_BYPASS Bypass the Receive Buffer */ |
||
3285 | +// {0x2424, 3, 3, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_DLY_WP Delay */ |
||
3286 | +// {0x2424, 2, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_INIT Initialize the Transmit Buffer */ |
||
3287 | +// {0x2424, 0, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_BYPASS Bypass the Transmit Buffer */ |
||
3288 | +// {0x2428, 0, 16, 0x30}, /* XRX200_MAC_BUFST_XBUF MAC Receive and TransmitBuffer Status Register */ |
||
3289 | +// {0x2428, 3, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_UFL Receive Buffer Underflow Indicator */ |
||
3290 | +// {0x2428, 2, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_OFL Receive Buffer Overflow Indicator */ |
||
3291 | +// {0x2428, 1, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_UFL Transmit Buffer Underflow Indicator */ |
||
3292 | +// {0x2428, 0, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_OFL Transmit Buffer Overflow Indicator */ |
||
3293 | +// {0x242C, 0, 16, 0x30}, /* XRX200_MAC_TESTEN MAC Test Enable Register */ |
||
3294 | +// {0x242C, 2, 1, 0x30}, /* XRX200_MAC_TESTEN_JTEN Jitter Test Enable */ |
||
3295 | +// {0x242C, 1, 1, 0x30}, /* XRX200_MAC_TESTEN_TXER Transmit Error Insertion */ |
||
3296 | +// {0x242C, 0, 1, 0x30}, /* XRX200_MAC_TESTEN_LOOP MAC Loopback Enable */ |
||
3297 | +// {0x2900, 0, 16, 0x00}, /* XRX200_FDMA_CTRL Ethernet Switch FetchDMA Control Register */ |
||
3298 | +// {0x2900, 7, 5, 0x00}, /* XRX200_FDMA_CTRL_LPI_THRESHOLD Low Power Idle Threshold */ |
||
3299 | +// {0x2900, 4, 3, 0x00}, /* XRX200_FDMA_CTRL_LPI_MODE Low Power Idle Mode */ |
||
3300 | +// {0x2900, 2, 2, 0x00}, /* XRX200_FDMA_CTRL_EGSTAG Egress Special Tag Size */ |
||
3301 | +// {0x2900, 1, 1, 0x00}, /* XRX200_FDMA_CTRL_IGSTAG Ingress Special Tag Size */ |
||
3302 | +// {0x2900, 0, 1, 0x00}, /* XRX200_FDMA_CTRL_EXCOL Excessive Collision Handling */ |
||
3303 | +// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE Special Tag EthertypeControl Register */ |
||
3304 | +// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE_ETYPE Special Tag Ethertype */ |
||
3305 | +// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE VLAN Tag EthertypeControl Register */ |
||
3306 | +// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE_ETYPE VLAN Tag Ethertype */ |
||
3307 | +// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0 FDMA Status Register0 */ |
||
3308 | +// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0_FSMS FSM states status */ |
||
3309 | +// {0x2910, 0, 16, 0x00}, /* XRX200_FDMA_IER Fetch DMA Global InterruptEnable Register */ |
||
3310 | +// {0x2910, 14, 1, 0x00}, /* XRX200_FDMA_IER_PCKD Packet Drop Interrupt Enable */ |
||
3311 | +// {0x2910, 13, 1, 0x00}, /* XRX200_FDMA_IER_PCKR Packet Ready Interrupt Enable */ |
||
3312 | +// {0x2910, 0, 8, 0x00}, /* XRX200_FDMA_IER_PCKT Packet Sent Interrupt Enable */ |
||
3313 | +// {0x2914, 0, 16, 0x00}, /* XRX200_FDMA_ISR Fetch DMA Global InterruptStatus Register */ |
||
3314 | +// {0x2914, 14, 1, 0x00}, /* XRX200_FDMA_ISR_PCKTD Packet Drop */ |
||
3315 | +// {0x2914, 13, 1, 0x00}, /* XRX200_FDMA_ISR_PCKR Packet is Ready for Transmission */ |
||
3316 | +// {0x2914, 0, 8, 0x00}, /* XRX200_FDMA_ISR_PCKT Packet Sent Event */ |
||
3317 | +// {0x2A00, 0, 16, 0x18}, /* XRX200_FDMA_PCTRL Ethernet SwitchFetch DMA Port Control Register */ |
||
3318 | +// {0x2A00, 3, 2, 0x18}, /* XRX200_FDMA_PCTRL_VLANMOD VLAN Modification Enable */ |
||
3319 | +// {0x2A00, 2, 1, 0x18}, /* XRX200_FDMA_PCTRL_DSCPRM DSCP Re-marking Enable */ |
||
3320 | +// {0x2A00, 1, 1, 0x18}, /* XRX200_FDMA_PCTRL_STEN Special Tag Insertion Enable */ |
||
3321 | +// {0x2A00, 0, 1, 0x18}, /* XRX200_FDMA_PCTRL_EN FDMA Port Enable */ |
||
3322 | +// {0x2A04, 0, 16, 0x18}, /* XRX200_FDMA_PRIO Ethernet SwitchFetch DMA Port Priority Register */ |
||
3323 | +// {0x2A04, 0, 2, 0x18}, /* XRX200_FDMA_PRIO_PRIO FDMA PRIO */ |
||
3324 | +// {0x2A08, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT0 Ethernet SwitchFetch DMA Port Status Register 0 */ |
||
3325 | +// {0x2A08, 15, 1, 0x18}, /* XRX200_FDMA_PSTAT0_PKT_AVAIL Port Egress Packet Available */ |
||
3326 | +// {0x2A08, 14, 1, 0x18}, /* XRX200_FDMA_PSTAT0_POK Port Status OK */ |
||
3327 | +// {0x2A08, 0, 6, 0x18}, /* XRX200_FDMA_PSTAT0_PSEG Port Egress Segment Count */ |
||
3328 | +// {0x2A0C, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT1_HDR Ethernet SwitchFetch DMA Port Status Register 1 */ |
||
3329 | +// {0x2A0C, 0, 10, 0x18}, /* XRX200_FDMA_PSTAT1_HDR_PTR Header Pointer */ |
||
3330 | +// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0 Egress TimeStamp Register 0 */ |
||
3331 | +// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0_TSTL Time Stamp [15:0] */ |
||
3332 | +// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1 Egress TimeStamp Register 1 */ |
||
3333 | +// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1_TSTH Time Stamp [31:16] */ |
||
3334 | +// {0x2D00, 0, 16, 0x00}, /* XRX200_SDMA_CTRL Ethernet Switch StoreDMA Control Register */ |
||
3335 | +// {0x2D00, 0, 1, 0x00}, /* XRX200_SDMA_CTRL_TSTEN Time Stamp Enable */ |
||
3336 | +// {0x2D04, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR1 SDMA Flow Control Threshold1 Register */ |
||
3337 | +// {0x2D04, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR1_THR1 Threshold 1 */ |
||
3338 | +// {0x2D08, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR2 SDMA Flow Control Threshold2 Register */ |
||
3339 | +// {0x2D08, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR2_THR2 Threshold 2 */ |
||
3340 | +// {0x2D0C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR3 SDMA Flow Control Threshold3 Register */ |
||
3341 | +// {0x2D0C, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR3_THR3 Threshold 3 */ |
||
3342 | +// {0x2D10, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR4 SDMA Flow Control Threshold4 Register */ |
||
3343 | +// {0x2D10, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR4_THR4 Threshold 4 */ |
||
3344 | +// {0x2D14, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR5 SDMA Flow Control Threshold5 Register */ |
||
3345 | +// {0x2D14, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR5_THR5 Threshold 5 */ |
||
3346 | +// {0x2D18, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR6 SDMA Flow Control Threshold6 Register */ |
||
3347 | +// {0x2D18, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR6_THR6 Threshold 6 */ |
||
3348 | +// {0x2D1C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR7 SDMA Flow Control Threshold7 Register */ |
||
3349 | +// {0x2D1C, 0, 11, 0x00}, /* XRX200_SDMA_FCTHR7_THR7 Threshold 7 */ |
||
3350 | +// {0x2D20, 0, 16, 0x00}, /* XRX200_SDMA_STAT_0 SDMA Status Register0 */ |
||
3351 | +// {0x2D20, 4, 3, 0x00}, /* XRX200_SDMA_STAT_0_BPS_FILL Back Pressure Status */ |
||
3352 | +// {0x2D20, 2, 2, 0x00}, /* XRX200_SDMA_STAT_0_BPS_PNT Back Pressure Status */ |
||
3353 | +// {0x2D20, 0, 2, 0x00}, /* XRX200_SDMA_STAT_0_DROP Back Pressure Status */ |
||
3354 | +// {0x2D24, 0, 16, 0x00}, /* XRX200_SDMA_STAT_1 SDMA Status Register1 */ |
||
3355 | +// {0x2D24, 0, 10, 0x00}, /* XRX200_SDMA_STAT_1_FILL Buffer Filling Level */ |
||
3356 | +// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2 SDMA Status Register2 */ |
||
3357 | +// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2_FSMS FSM states status */ |
||
3358 | +// {0x2D2C, 0, 16, 0x00}, /* XRX200_SDMA_IER SDMA Interrupt Enable Register */ |
||
3359 | +// {0x2D2C, 15, 1, 0x00}, /* XRX200_SDMA_IER_BPEX Buffer Pointers Exceeded */ |
||
3360 | +// {0x2D2C, 14, 1, 0x00}, /* XRX200_SDMA_IER_BFULL Buffer Full */ |
||
3361 | +// {0x2D2C, 13, 1, 0x00}, /* XRX200_SDMA_IER_FERR Frame Error */ |
||
3362 | +// {0x2D2C, 0, 8, 0x00}, /* XRX200_SDMA_IER_FRX Frame Received Successfully */ |
||
3363 | +// {0x2D30, 0, 16, 0x00}, /* XRX200_SDMA_ISR SDMA Interrupt Status Register */ |
||
3364 | +// {0x2D30, 15, 1, 0x00}, /* XRX200_SDMA_ISR_BPEX Packet Descriptors Exceeded */ |
||
3365 | +// {0x2D30, 14, 1, 0x00}, /* XRX200_SDMA_ISR_BFULL Buffer Full */ |
||
3366 | +// {0x2D30, 13, 1, 0x00}, /* XRX200_SDMA_ISR_FERR Frame Error */ |
||
3367 | +// {0x2D30, 0, 8, 0x00}, /* XRX200_SDMA_ISR_FRX Frame Received Successfully */ |
||
3368 | +// {0x2F00, 0, 16, 0x18}, /* XRX200_SDMA_PCTRL Ethernet SwitchStore DMA Port Control Register */ |
||
3369 | +// {0x2F00, 13, 2, 0x18}, /* XRX200_SDMA_PCTRL_DTHR Drop Threshold Selection */ |
||
3370 | +// {0x2F00, 11, 2, 0x18}, /* XRX200_SDMA_PCTRL_PTHR Pause Threshold Selection */ |
||
3371 | +// {0x2F00, 10, 1, 0x18}, /* XRX200_SDMA_PCTRL_PHYEFWD Forward PHY Error Frames */ |
||
3372 | +// {0x2F00, 9, 1, 0x18}, /* XRX200_SDMA_PCTRL_ALGFWD Forward Alignment Error Frames */ |
||
3373 | +// {0x2F00, 8, 1, 0x18}, /* XRX200_SDMA_PCTRL_LENFWD Forward Length Errored Frames */ |
||
3374 | +// {0x2F00, 7, 1, 0x18}, /* XRX200_SDMA_PCTRL_OSFWD Forward Oversized Frames */ |
||
3375 | +// {0x2F00, 6, 1, 0x18}, /* XRX200_SDMA_PCTRL_USFWD Forward Undersized Frames */ |
||
3376 | +// {0x2F00, 5, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSIGN Ignore FCS Errors */ |
||
3377 | +// {0x2F00, 4, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSFWD Forward FCS Errored Frames */ |
||
3378 | +// {0x2F00, 3, 1, 0x18}, /* XRX200_SDMA_PCTRL_PAUFWD Pause Frame Forwarding */ |
||
3379 | +// {0x2F00, 2, 1, 0x18}, /* XRX200_SDMA_PCTRL_MFCEN Metering Flow Control Enable */ |
||
3380 | +// {0x2F00, 1, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCEN Flow Control Enable */ |
||
3381 | +// {0x2F00, 0, 1, 0x18}, /* XRX200_SDMA_PCTRL_PEN Port Enable */ |
||
3382 | +// {0x2F04, 0, 16, 0x18}, /* XRX200_SDMA_PRIO Ethernet SwitchStore DMA Port Priority Register */ |
||
3383 | +// {0x2F04, 0, 2, 0x18}, /* XRX200_SDMA_PRIO_PRIO SDMA PRIO */ |
||
3384 | +// {0x2F08, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT0_HDR Ethernet SwitchStore DMA Port Status Register 0 */ |
||
3385 | +// {0x2F08, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT0_HDR_PTR Port Ingress Queue Header Pointer */ |
||
3386 | +// {0x2F0C, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT1 Ethernet SwitchStore DMA Port Status Register 1 */ |
||
3387 | +// {0x2F0C, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT1_PPKT Port Ingress Packet Count */ |
||
3388 | +// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0 Ingress TimeStamp Register 0 */ |
||
3389 | +// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0_TSTL Time Stamp [15:0] */ |
||
3390 | +// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1 Ingress TimeStamp Register 1 */ |
||
3391 | +// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1_TSTH Time Stamp [31:16] */ |
||
3392 | +}; |
||
3393 | + |
||
3394 | + |