OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 |
2 | From: John Crispin <blogic@openwrt.org> |
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3 | Date: Thu, 7 Aug 2014 18:15:36 +0200 |
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4 | Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G |
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5 | |||
6 | Signed-off-by: John Crispin <blogic@openwrt.org> |
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7 | --- |
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8 | drivers/net/phy/Kconfig | 5 + |
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9 | drivers/net/phy/Makefile | 1 + |
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10 | drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ |
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11 | 3 files changed, 237 insertions(+) |
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12 | create mode 100644 drivers/net/phy/lantiq.c |
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13 | |||
14 | --- a/drivers/net/phy/intel-xway.c |
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15 | +++ b/drivers/net/phy/intel-xway.c |
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16 | @@ -152,6 +152,51 @@ |
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17 | #define PHY_ID_PHY11G_VR9 0xD565A409 |
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18 | #define PHY_ID_PHY22F_VR9 0xD565A419 |
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19 | |||
20 | +#if IS_ENABLED(CONFIG_OF_MDIO) |
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21 | +static int vr9_gphy_of_reg_init(struct phy_device *phydev) |
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22 | +{ |
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23 | + u32 tmp; |
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24 | + |
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25 | + /* store the led values if one was passed by the devicetree */ |
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26 | + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp)) |
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27 | + phy_write_mmd_indirect(phydev, XWAY_MMD_LEDCH, MDIO_MMD_VEND2, tmp); |
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28 | + |
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29 | + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp)) |
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30 | + phy_write_mmd_indirect(phydev, XWAY_MMD_LEDCL, MDIO_MMD_VEND2, tmp); |
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31 | + |
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32 | + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp)) |
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33 | + phy_write_mmd_indirect(phydev, XWAY_MMD_LED0H, MDIO_MMD_VEND2, tmp); |
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34 | + |
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35 | + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp)) |
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36 | + phy_write_mmd_indirect(phydev, XWAY_MMD_LED0L, MDIO_MMD_VEND2, tmp); |
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37 | + |
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38 | + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp)) |
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39 | + phy_write_mmd_indirect(phydev, XWAY_MMD_LED1H, MDIO_MMD_VEND2, tmp); |
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40 | + |
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41 | + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp)) |
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42 | + phy_write_mmd_indirect(phydev, XWAY_MMD_LED1L, MDIO_MMD_VEND2, tmp); |
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43 | + |
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44 | + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp)) |
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45 | + phy_write_mmd_indirect(phydev, XWAY_MMD_LED3H, MDIO_MMD_VEND2, tmp); |
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46 | + |
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47 | + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp)) |
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48 | + phy_write_mmd_indirect(phydev, XWAY_MMD_LED3L, MDIO_MMD_VEND2, tmp); |
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49 | + |
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50 | + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp)) |
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51 | + phy_write_mmd_indirect(phydev, XWAY_MMD_LED3H, MDIO_MMD_VEND2, tmp); |
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52 | + |
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53 | + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp)) |
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54 | + phy_write_mmd_indirect(phydev, XWAY_MMD_LED3L, MDIO_MMD_VEND2, tmp); |
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55 | + |
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56 | + return 0; |
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57 | +} |
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58 | +#else |
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59 | +static int vr9_gphy_of_reg_init(struct phy_device *phydev) |
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60 | +{ |
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61 | + return 0; |
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62 | +} |
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63 | +#endif /* CONFIG_OF_MDIO */ |
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64 | + |
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65 | static int xway_gphy_config_init(struct phy_device *phydev) |
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66 | { |
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67 | int err; |
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68 | @@ -190,6 +235,7 @@ static int xway_gphy_config_init(struct |
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69 | phy_write_mmd_indirect(phydev, XWAY_MMD_LED2H, MDIO_MMD_VEND2, ledxh); |
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70 | phy_write_mmd_indirect(phydev, XWAY_MMD_LED2L, MDIO_MMD_VEND2, ledxl); |
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71 | |||
72 | + vr9_gphy_of_reg_init(phydev); |
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73 | return 0; |
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74 | } |
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75 | |||
76 | --- /dev/null |
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77 | +++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt |
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78 | @@ -0,0 +1,216 @@ |
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79 | +Lanitq PHY binding |
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80 | +============================================ |
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81 | + |
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82 | +This devicetree binding controls the lantiq ethernet phys led functionality. |
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83 | + |
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84 | +Example: |
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85 | + mdio@0 { |
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86 | + #address-cells = <1>; |
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87 | + #size-cells = <0>; |
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88 | + compatible = "lantiq,xrx200-mdio"; |
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89 | + phy5: ethernet-phy@5 { |
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90 | + reg = <0x1>; |
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91 | + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; |
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92 | + }; |
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93 | + phy11: ethernet-phy@11 { |
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94 | + reg = <0x11>; |
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95 | + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; |
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96 | + lantiq,led2h = <0x00>; |
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97 | + lantiq,led2l = <0x03>; |
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98 | + }; |
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99 | + phy12: ethernet-phy@12 { |
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100 | + reg = <0x12>; |
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101 | + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; |
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102 | + lantiq,led1h = <0x00>; |
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103 | + lantiq,led1l = <0x03>; |
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104 | + }; |
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105 | + phy13: ethernet-phy@13 { |
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106 | + reg = <0x13>; |
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107 | + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; |
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108 | + lantiq,led2h = <0x00>; |
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109 | + lantiq,led2l = <0x03>; |
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110 | + }; |
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111 | + phy14: ethernet-phy@14 { |
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112 | + reg = <0x14>; |
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113 | + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; |
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114 | + lantiq,led1h = <0x00>; |
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115 | + lantiq,led1l = <0x03>; |
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116 | + }; |
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117 | + }; |
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118 | + |
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119 | +Register Description |
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120 | +============================================ |
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121 | + |
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122 | +LEDCH: |
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123 | + |
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124 | +Name Hardware Reset Value |
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125 | +LEDCH 0x00C5 |
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126 | + |
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127 | +| 15 | | | | | | | 8 | |
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128 | +========================================= |
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129 | +| RES | |
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130 | +========================================= |
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131 | + |
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132 | +| 7 | | | | | | | 0 | |
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133 | +========================================= |
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134 | +| FBF | SBF |RES | NACS | |
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135 | +========================================= |
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136 | + |
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137 | +Field Bits Type Description |
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138 | +FBF 7:6 RW Fast Blink Frequency |
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139 | + --- |
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140 | + 0x0 (00b) F02HZ 2 Hz blinking frequency |
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141 | + 0x1 (01b) F04HZ 4 Hz blinking frequency |
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142 | + 0x2 (10b) F08HZ 8 Hz blinking frequency |
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143 | + 0x3 (11b) F16HZ 16 Hz blinking frequency |
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144 | + |
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145 | +SBF 5:4 RW Slow Blink Frequency |
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146 | + --- |
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147 | + 0x0 (00b) F02HZ 2 Hz blinking frequency |
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148 | + 0x1 (01b) F04HZ 4 Hz blinking frequency |
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149 | + 0x2 (10b) F08HZ 8 Hz blinking frequency |
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150 | + 0x3 (11b) F16HZ 16 Hz blinking frequency |
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151 | + |
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152 | +NACS 2:0 RW Inverse of Scan Function |
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153 | + --- |
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154 | + 0x0 (000b) NONE No Function |
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155 | + 0x1 (001b) LINK Complex function enabled when link is up |
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156 | + 0x2 (010b) PDOWN Complex function enabled when device is powered-down |
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157 | + 0x3 (011b) EEE Complex function enabled when device is in EEE mode |
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158 | + 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running |
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159 | + 0x5 (101b) ABIST Complex function enabled when analog self-test is running |
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160 | + 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running |
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161 | + 0x7 (111b) TEST Complex function enabled when test mode is running |
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162 | + |
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163 | +LEDCL: |
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164 | + |
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165 | +Name Hardware Reset Value |
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166 | +LEDCL 0x0067 |
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167 | + |
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168 | +| 15 | | | | | | | 8 | |
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169 | +========================================= |
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170 | +| RES | |
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171 | +========================================= |
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172 | + |
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173 | +| 7 | | | | | | | 0 | |
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174 | +========================================= |
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175 | +|RES | SCAN |RES | CBLINK | |
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176 | +========================================= |
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177 | + |
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178 | +Field Bits Type Description |
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179 | +SCAN 6:4 RW Complex Scan Configuration |
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180 | + --- |
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181 | + 000 B NONE No Function |
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182 | + 001 B LINK Complex function enabled when link is up |
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183 | + 010 B PDOWN Complex function enabled when device is powered-down |
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184 | + 011 B EEE Complex function enabled when device is in EEE mode |
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185 | + 100 B ANEG Complex function enabled when auto-negotiation is running |
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186 | + 101 B ABIST Complex function enabled when analog self-test is running |
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187 | + 110 B CDIAG Complex function enabled when cable diagnostics are running |
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188 | + 111 B TEST Complex function enabled when test mode is running |
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189 | + |
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190 | +CBLINK 2:0 RW Complex Blinking Configuration |
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191 | + --- |
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192 | + 000 B NONE No Function |
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193 | + 001 B LINK Complex function enabled when link is up |
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194 | + 010 B PDOWN Complex function enabled when device is powered-down |
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195 | + 011 B EEE Complex function enabled when device is in EEE mode |
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196 | + 100 B ANEG Complex function enabled when auto-negotiation is running |
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197 | + 101 B ABIST Complex function enabled when analog self-test is running |
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198 | + 110 B CDIAG Complex function enabled when cable diagnostics are running |
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199 | + 111 B TEST Complex function enabled when test mode is running |
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200 | + |
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201 | +LEDxH: |
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202 | + |
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203 | +Name Hardware Reset Value |
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204 | +LED0H 0x0070 |
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205 | +LED1H 0x0020 |
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206 | +LED2H 0x0040 |
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207 | +LED3H 0x0040 |
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208 | + |
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209 | +| 15 | | | | | | | 8 | |
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210 | +========================================= |
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211 | +| RES | |
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212 | +========================================= |
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213 | + |
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214 | +| 7 | | | | | | | 0 | |
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215 | +========================================= |
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216 | +| CON | BLINKF | |
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217 | +========================================= |
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218 | + |
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219 | +Field Bits Type Description |
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220 | +CON 7:4 RW Constant On Configuration |
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221 | + --- |
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222 | + 0x0 (0000b) NONE LED does not light up constantly |
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223 | + 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s |
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224 | + 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s |
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225 | + 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s |
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226 | + 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s |
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227 | + 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s |
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228 | + 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s |
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229 | + 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s |
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230 | + 0x8 (1000b) PDOWN LED is on when device is powered-down |
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231 | + 0x9 (1001b) EEE LED is on when device is in EEE mode |
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232 | + 0xA (1010b) ANEG LED is on when auto-negotiation is running |
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233 | + 0xB (1011b) ABIST LED is on when analog self-test is running |
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234 | + 0xC (1100b) CDIAG LED is on when cable diagnostics are running |
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235 | + |
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236 | +BLINKF 3:0 RW Fast Blinking Configuration |
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237 | + --- |
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238 | + 0x0 (0000b) NONE No Blinking |
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239 | + 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s |
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240 | + 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s |
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241 | + 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s |
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242 | + 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s |
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243 | + 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s |
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244 | + 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s |
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245 | + 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s |
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246 | + 0x8 (1000b) PDOWN Blink when device is powered-down |
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247 | + 0x9 (1001b) EEE Blink when device is in EEE mode |
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248 | + 0xA (1010b) ANEG Blink when auto-negotiation is running |
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249 | + 0xB (1011b) ABIST Blink when analog self-test is running |
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250 | + 0xC (1100b) CDIAG Blink when cable diagnostics are running |
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251 | + |
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252 | +LEDxL: |
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253 | + |
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254 | +Name Hardware Reset Value |
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255 | +LED0L 0x0003 |
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256 | +LED1L 0x0000 |
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257 | +LED2L 0x0000 |
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258 | +LED3L 0x0020 |
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259 | + |
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260 | +| 15 | | | | | | | 8 | |
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261 | +========================================= |
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262 | +| RES | |
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263 | +========================================= |
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264 | + |
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265 | +| 7 | | | | | | | 0 | |
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266 | +========================================= |
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267 | +| BLINKS | PULSE | |
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268 | +========================================= |
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269 | + |
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270 | +Field Bits Type Description |
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271 | +BLINKS 7:4 RW Slow Blinkin Configuration |
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272 | + --- |
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273 | + 0x0 (0000b) NONE No Blinking |
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274 | + 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s |
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275 | + 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s |
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276 | + 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s |
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277 | + 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s |
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278 | + 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s |
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279 | + 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s |
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280 | + 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s |
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281 | + 0x8 (1000b) PDOWN Blink when device is powered-down |
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282 | + 0x9 (1001b) EEE Blink when device is in EEE mode |
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283 | + 0xA (1010b) ANEG Blink when auto-negotiation is running |
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284 | + 0xB (1011b) ABIST Blink when analog self-test is running |
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285 | + 0xC (1100b) CDIAG Blink when cable diagnostics are runningning |
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286 | + |
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287 | +PULSE 3:0 RW Pulsing Configuration |
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288 | + The pulse field is a mask field by which certain events can be combined |
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289 | + --- |
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290 | + 0x0 (0000b) NONE No pulsing |
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291 | + 0x1 (0001b) TXACT Transmit activity |
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292 | + 0x2 (0010b) RXACT Receive activity |
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293 | + 0x4 (0100b) COL Collision |
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294 | + 0x8 (1000b) RES Reserved |