OpenWrt – Blame information for rev 4

Subversion Repositories:
Rev:
Rev Author Line No. Line
4 office 1 --- a/arch/arm/configs/ixp4xx_defconfig
2 +++ b/arch/arm/configs/ixp4xx_defconfig
3 @@ -26,6 +26,7 @@ CONFIG_MACH_NAS100D=y
4 CONFIG_MACH_DSMG600=y
5 CONFIG_MACH_FSG=y
6 CONFIG_MACH_GTWX5715=y
7 +CONFIG_MACH_MI424WR=y
8 CONFIG_IXP4XX_QMGR=y
9 CONFIG_IXP4XX_NPE=y
10 # CONFIG_ARM_THUMB is not set
11 --- a/arch/arm/mach-ixp4xx/Kconfig
12 +++ b/arch/arm/mach-ixp4xx/Kconfig
13 @@ -258,6 +258,13 @@ config MACH_MIC256
14 Say 'Y' here if you want your kernel to support the MIC256
15 board from OMICRON electronics GmbH.
16  
17 +config MACH_MI424WR
18 + bool "Actiontec MI424WR"
19 + depends on ARCH_IXP4XX
20 + select PCI
21 + help
22 + Add support for the Actiontec MI424-WR.
23 +
24 comment "IXP4xx Options"
25  
26 config IXP4XX_INDIRECT_PCI
27 --- a/arch/arm/mach-ixp4xx/Makefile
28 +++ b/arch/arm/mach-ixp4xx/Makefile
29 @@ -25,6 +25,7 @@ obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixd
30 obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
31 obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
32 obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o
33 +obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o
34  
35 obj-y += common.o
36  
37 @@ -51,6 +52,7 @@ obj-$(CONFIG_MACH_COMPEXWP18) += compex4
38 obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
39 obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
40 obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
41 +obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o
42  
43 obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
44 obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
45 --- /dev/null
46 +++ b/arch/arm/mach-ixp4xx/mi424wr-pci.c
47 @@ -0,0 +1,70 @@
48 +/*
49 + * arch/arm/mach-ixp4xx/mi424wr-pci.c
50 + *
51 + * Actiontec MI424WR board-level PCI initialization
52 + *
53 + * Copyright (C) 2008 Jose Vasconcellos
54 + *
55 + * Maintainer: Jose Vasconcellos <jvasco@verizon.net>
56 + *
57 + * This program is free software; you can redistribute it and/or modify
58 + * it under the terms of the GNU General Public License version 2 as
59 + * published by the Free Software Foundation.
60 + *
61 + */
62 +
63 +#include <linux/kernel.h>
64 +#include <linux/pci.h>
65 +#include <linux/init.h>
66 +#include <linux/irq.h>
67 +
68 +#include <asm/mach-types.h>
69 +#include <asm/mach/pci.h>
70 +
71 +/* PCI controller GPIO to IRQ pin mappings
72 + * This information was obtained from Actiontec's GPL release.
73 + *
74 + * INTA INTB
75 + * SLOT 13 8 6
76 + * SLOT 14 7 8
77 + * SLOT 15 6 7
78 + */
79 +
80 +void __init mi424wr_pci_preinit(void)
81 +{
82 + irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
83 + irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
84 + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
85 +
86 + ixp4xx_pci_preinit();
87 +}
88 +
89 +static int __init mi424wr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
90 +{
91 + if (slot == 13)
92 + return IRQ_IXP4XX_GPIO8;
93 + if (slot == 14)
94 + return IRQ_IXP4XX_GPIO7;
95 + if (slot == 15)
96 + return IRQ_IXP4XX_GPIO6;
97 +
98 + return -1;
99 +}
100 +
101 +struct hw_pci mi424wr_pci __initdata = {
102 + .nr_controllers = 1,
103 + .preinit = mi424wr_pci_preinit,
104 + .ops = &ixp4xx_ops,
105 + .setup = ixp4xx_setup,
106 + .map_irq = mi424wr_map_irq,
107 +};
108 +
109 +int __init mi424wr_pci_init(void)
110 +{
111 + if (machine_is_mi424wr())
112 + pci_common_init(&mi424wr_pci);
113 + return 0;
114 +}
115 +
116 +subsys_initcall(mi424wr_pci_init);
117 +
118 --- /dev/null
119 +++ b/arch/arm/mach-ixp4xx/mi424wr-setup.c
120 @@ -0,0 +1,384 @@
121 +/*
122 + * arch/arm/mach-ixp4xx/mi424wr-setup.c
123 + *
124 + * Actiontec MI424-WR board setup
125 + * Copyright (c) 2008 Jose Vasconcellos
126 + *
127 + * Based on Gemtek GTWX5715 by
128 + * Copyright (C) 2004 George T. Joseph
129 + * Derived from Coyote
130 + *
131 + * This program is free software; you can redistribute it and/or
132 + * modify it under the terms of the GNU General Public License
133 + * as published by the Free Software Foundation; either version 2
134 + * of the License, or (at your option) any later version.
135 + *
136 + * This program is distributed in the hope that it will be useful,
137 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
138 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
139 + * GNU General Public License for more details.
140 + *
141 + * You should have received a copy of the GNU General Public License
142 + * along with this program; if not, write to the Free Software
143 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
144 + *
145 + */
146 +
147 +#include <linux/init.h>
148 +#include <linux/device.h>
149 +#include <linux/serial.h>
150 +#include <linux/serial_8250.h>
151 +#include <linux/types.h>
152 +#include <linux/memory.h>
153 +#include <linux/leds.h>
154 +#include <linux/spi/spi.h>
155 +#include <linux/spi/spi_gpio.h>
156 +#include <linux/dma-mapping.h>
157 +
158 +#include <asm/setup.h>
159 +#include <asm/system_info.h>
160 +#include <asm/irq.h>
161 +#include <asm/io.h>
162 +#include <asm/mach-types.h>
163 +#include <asm/mach/arch.h>
164 +#include <asm/mach/flash.h>
165 +
166 +/*
167 + * GPIO 2,3,4 and 9 are hard wired to the Micrel/Kendin KS8995M Switch
168 + * and operate as an SPI type interface. The details of the interface
169 + * are available on Kendin/Micrel's web site.
170 + */
171 +
172 +#define MI424WR_KSSPI_SELECT 9
173 +#define MI424WR_KSSPI_TXD 4
174 +#define MI424WR_KSSPI_CLOCK 2
175 +#define MI424WR_KSSPI_RXD 3
176 +
177 +/*
178 + * The "reset" button is wired to GPIO 10.
179 + * The GPIO is brought "low" when the button is pushed.
180 + */
181 +
182 +#define MI424WR_BUTTON_GPIO 10
183 +#define MI424WR_BUTTON_IRQ IRQ_IXP4XX_GPIO10
184 +
185 +#define MI424WR_MOCA_WAN_LED 11
186 +
187 +/* Latch on CS1 - taken from Actiontec's 2.4 source code
188 + *
189 + * default latch value
190 + * 0 - power alarm led (red) 0 (off)
191 + * 1 - power led (green) 0 (off)
192 + * 2 - wireless led (green) 1 (off)
193 + * 3 - no internet led (red) 0 (off)
194 + * 4 - internet ok led (green) 0 (off)
195 + * 5 - moca LAN 0 (off)
196 + * 6 - WAN alarm led (red) 0 (off)
197 + * 7 - PCI reset 1 (not reset)
198 + * 8 - IP phone 1 led (green) 1 (off)
199 + * 9 - IP phone 2 led (green) 1 (off)
200 + * 10 - VOIP ready led (green) 1 (off)
201 + * 11 - PSTN relay 1 control 0 (PSTN)
202 + * 12 - PSTN relay 1 control 0 (PSTN)
203 + * 13 - N/A
204 + * 14 - N/A
205 + * 15 - N/A
206 + */
207 +
208 +#define MI424WR_LATCH_MASK 0x04
209 +#define MI424WR_LATCH_DEFAULT 0x1f86
210 +
211 +#define MI424WR_LATCH_ALARM_LED 0x00
212 +#define MI424WR_LATCH_POWER_LED 0x01
213 +#define MI424WR_LATCH_WIRELESS_LED 0x02
214 +#define MI424WR_LATCH_INET_DOWN_LED 0x03
215 +#define MI424WR_LATCH_INET_OK_LED 0x04
216 +#define MI424WR_LATCH_MOCA_LAN_LED 0x05
217 +#define MI424WR_LATCH_WAN_ALARM_LED 0x06
218 +#define MI424WR_LATCH_PCI_RESET 0x07
219 +#define MI424WR_LATCH_PHONE1_LED 0x08
220 +#define MI424WR_LATCH_PHONE2_LED 0x09
221 +#define MI424WR_LATCH_VOIP_LED 0x10
222 +#define MI424WR_LATCH_PSTN_RELAY1 0x11
223 +#define MI424WR_LATCH_PSTN_RELAY2 0x12
224 +
225 +/* initialize CS1 to default timings, Intel style, 16-bit bus */
226 +#define MI424WR_CS1_CONFIG 0x80000002
227 +
228 +/* Define both UARTs but they are not easily accessible.
229 + */
230 +
231 +static struct resource mi424wr_uart_resources[] = {
232 + {
233 + .start = IXP4XX_UART1_BASE_PHYS,
234 + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
235 + .flags = IORESOURCE_MEM,
236 + },
237 + {
238 + .start = IXP4XX_UART2_BASE_PHYS,
239 + .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
240 + .flags = IORESOURCE_MEM,
241 + }
242 +};
243 +
244 +
245 +static struct plat_serial8250_port mi424wr_uart_platform_data[] = {
246 + {
247 + .mapbase = IXP4XX_UART1_BASE_PHYS,
248 + .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
249 + .irq = IRQ_IXP4XX_UART1,
250 + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
251 + .iotype = UPIO_MEM,
252 + .regshift = 2,
253 + .uartclk = IXP4XX_UART_XTAL,
254 + },
255 + {
256 + .mapbase = IXP4XX_UART2_BASE_PHYS,
257 + .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
258 + .irq = IRQ_IXP4XX_UART2,
259 + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
260 + .iotype = UPIO_MEM,
261 + .regshift = 2,
262 + .uartclk = IXP4XX_UART_XTAL,
263 + },
264 + { },
265 +};
266 +
267 +static struct platform_device mi424wr_uart_device = {
268 + .name = "serial8250",
269 + .id = PLAT8250_DEV_PLATFORM,
270 + .dev.platform_data = mi424wr_uart_platform_data,
271 + .num_resources = ARRAY_SIZE(mi424wr_uart_resources),
272 + .resource = mi424wr_uart_resources,
273 +};
274 +
275 +static struct flash_platform_data mi424wr_flash_data = {
276 + .map_name = "cfi_probe",
277 + .width = 2,
278 +};
279 +
280 +static struct resource mi424wr_flash_resource = {
281 + .flags = IORESOURCE_MEM,
282 +};
283 +
284 +static struct platform_device mi424wr_flash = {
285 + .name = "IXP4XX-Flash",
286 + .id = 0,
287 + .dev.platform_data = &mi424wr_flash_data,
288 + .num_resources = 1,
289 + .resource = &mi424wr_flash_resource,
290 +};
291 +
292 +static struct spi_gpio_platform_data mi424wr_spi_platform_data = {
293 + .sck = MI424WR_KSSPI_CLOCK,
294 + .mosi = MI424WR_KSSPI_TXD,
295 + .miso = MI424WR_KSSPI_RXD,
296 + .num_chipselect = 1,
297 +};
298 +
299 +static struct platform_device mi424wr_spi_device = {
300 + .name = "spi-gpio",
301 + .id = 1,
302 + .dev.platform_data = &mi424wr_spi_platform_data,
303 +};
304 +
305 +static struct spi_board_info mi424wr_spi_devices[] __initdata = {
306 + {
307 + .modalias = "spi-ks8995",
308 + .max_speed_hz = 500000,
309 + .mode = SPI_MODE_0,
310 + .bus_num = 1,
311 + .chip_select = 0,
312 + .controller_data = (void *)MI424WR_KSSPI_SELECT,
313 + }
314 +};
315 +
316 +static struct gpio_led mi424wr_gpio_led[] = {
317 + {
318 + .name = "moca-wan", /* green led */
319 + .gpio = MI424WR_MOCA_WAN_LED,
320 + .active_low = 0,
321 + }
322 +};
323 +
324 +static struct gpio_led_platform_data mi424wr_gpio_leds_data = {
325 + .num_leds = 1,
326 + .leds = mi424wr_gpio_led,
327 +};
328 +
329 +static struct platform_device mi424wr_gpio_leds = {
330 + .name = "leds-gpio",
331 + .id = -1,
332 + .dev.platform_data = &mi424wr_gpio_leds_data,
333 +};
334 +
335 +static uint16_t latch_value = MI424WR_LATCH_DEFAULT;
336 +static uint16_t __iomem *iobase;
337 +
338 +static void mi424wr_latch_set_led(u8 bit, enum led_brightness value)
339 +{
340 +
341 + if (((MI424WR_LATCH_MASK >> bit) & 1) ^ (value == LED_OFF))
342 + latch_value &= ~(0x1 << bit);
343 + else
344 + latch_value |= (0x1 << bit);
345 +
346 + __raw_writew(latch_value, iobase);
347 +
348 +}
349 +
350 +static struct latch_led mi424wr_latch_led[] = {
351 + {
352 + .name = "power-alarm",
353 + .bit = MI424WR_LATCH_ALARM_LED,
354 + },
355 + {
356 + .name = "power-ok",
357 + .bit = MI424WR_LATCH_POWER_LED,
358 + },
359 + {
360 + .name = "wireless", /* green led */
361 + .bit = MI424WR_LATCH_WIRELESS_LED,
362 + },
363 + {
364 + .name = "inet-down", /* red led */
365 + .bit = MI424WR_LATCH_INET_DOWN_LED,
366 + },
367 + {
368 + .name = "inet-up", /* green led */
369 + .bit = MI424WR_LATCH_INET_OK_LED,
370 + },
371 + {
372 + .name = "moca-lan", /* green led */
373 + .bit = MI424WR_LATCH_MOCA_LAN_LED,
374 + },
375 + {
376 + .name = "wan-alarm", /* red led */
377 + .bit = MI424WR_LATCH_WAN_ALARM_LED,
378 + }
379 +};
380 +
381 +static struct latch_led_platform_data mi424wr_latch_leds_data = {
382 + .num_leds = ARRAY_SIZE(mi424wr_latch_led),
383 + .mem = 0x51000000,
384 + .leds = mi424wr_latch_led,
385 + .set_led = mi424wr_latch_set_led,
386 +};
387 +
388 +static struct platform_device mi424wr_latch_leds = {
389 + .name = "leds-latch",
390 + .id = -1,
391 + .dev.platform_data = &mi424wr_latch_leds_data,
392 +};
393 +
394 +static struct eth_plat_info mi424wr_wan_data = {
395 + .phy = 17, /* KS8721 */
396 + .rxq = 3,
397 + .txreadyq = 20,
398 +};
399 +
400 +static struct eth_plat_info mi424wr_lan_data = {
401 + .phy = IXP4XX_ETH_PHY_MAX_ADDR,
402 + .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
403 + .rxq = 4,
404 + .txreadyq = 21,
405 +};
406 +
407 +static struct platform_device mi424wr_npe_devices[] = {
408 + {
409 + .name = "ixp4xx_eth",
410 + .id = IXP4XX_ETH_NPEC,
411 + .dev.platform_data = &mi424wr_lan_data,
412 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
413 + }, {
414 + .name = "ixp4xx_eth",
415 + .id = IXP4XX_ETH_NPEB,
416 + .dev.platform_data = &mi424wr_wan_data,
417 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
418 + }
419 +};
420 +
421 +static struct eth_plat_info mi424wr_wanD_data = {
422 + .phy = 5,
423 + .rxq = 4,
424 + .txreadyq = 21,
425 +};
426 +
427 +static struct eth_plat_info mi424wr_lanD_data = {
428 + .phy = IXP4XX_ETH_PHY_MAX_ADDR,
429 + .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
430 + .rxq = 3,
431 + .txreadyq = 20,
432 +};
433 +
434 +static struct platform_device mi424wr_npeD_devices[] = {
435 + {
436 + .name = "ixp4xx_eth",
437 + .id = IXP4XX_ETH_NPEB,
438 + .dev.platform_data = &mi424wr_lanD_data,
439 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
440 + }, {
441 + .name = "ixp4xx_eth",
442 + .id = IXP4XX_ETH_NPEC,
443 + .dev.platform_data = &mi424wr_wanD_data,
444 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
445 + }
446 +};
447 +
448 +static struct platform_device *mi424wr_devices[] __initdata = {
449 + &mi424wr_uart_device,
450 + &mi424wr_flash,
451 + &mi424wr_spi_device,
452 + &mi424wr_gpio_leds,
453 + &mi424wr_latch_leds,
454 +};
455 +
456 +static void __init mi424wr_init(void)
457 +{
458 + ixp4xx_sys_init();
459 +
460 + mi424wr_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
461 + mi424wr_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1;
462 +
463 + *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
464 + *IXP4XX_EXP_CS1 = MI424WR_CS1_CONFIG;
465 +
466 + /* configure button as input
467 + */
468 + gpio_line_config(MI424WR_BUTTON_GPIO, IXP4XX_GPIO_IN);
469 +
470 + /* Initialize LEDs and enables PCI bus.
471 + */
472 + iobase = ioremap_nocache(IXP4XX_EXP_BUS_BASE(1), 0x1000);
473 + __raw_writew(latch_value, iobase);
474 +
475 + spi_register_board_info(mi424wr_spi_devices, ARRAY_SIZE(mi424wr_spi_devices));
476 + platform_add_devices(mi424wr_devices, ARRAY_SIZE(mi424wr_devices));
477 +
478 + /* Need to figure out how to detect revD.
479 + * Look for a revision argument sent by redboot.
480 + */
481 +#define revD 4
482 + if (system_rev == revD) {
483 + platform_device_register(&mi424wr_npeD_devices[0]);
484 + platform_device_register(&mi424wr_npeD_devices[1]);
485 + } else {
486 + platform_device_register(&mi424wr_npe_devices[0]);
487 + platform_device_register(&mi424wr_npe_devices[1]);
488 + }
489 +}
490 +
491 +
492 +MACHINE_START(MI424WR, "Actiontec MI424WR")
493 + /* Maintainer: Jose Vasconcellos */
494 + .map_io = ixp4xx_map_io,
495 + .init_irq = ixp4xx_init_irq,
496 + .init_time = ixp4xx_timer_init,
497 + .atag_offset = 0x0100,
498 + .init_machine = mi424wr_init,
499 +#if defined(CONFIG_PCI)
500 + .dma_zone_size = SZ_64M,
501 +#endif
502 + .restart = ixp4xx_restart,
503 +MACHINE_END
504 +