OpenWrt – Blame information for rev 4

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Rev Author Line No. Line
4 office 1 --- a/sound/soc/Kconfig
2 +++ b/sound/soc/Kconfig
3 @@ -47,6 +47,7 @@ source "sound/soc/cirrus/Kconfig"
4 source "sound/soc/davinci/Kconfig"
5 source "sound/soc/dwc/Kconfig"
6 source "sound/soc/fsl/Kconfig"
7 +source "sound/soc/gw-avila/Kconfig"
8 source "sound/soc/jz4740/Kconfig"
9 source "sound/soc/nuc900/Kconfig"
10 source "sound/soc/omap/Kconfig"
11 --- a/sound/soc/Makefile
12 +++ b/sound/soc/Makefile
13 @@ -27,6 +27,7 @@ obj-$(CONFIG_SND_SOC) += cirrus/
14 obj-$(CONFIG_SND_SOC) += davinci/
15 obj-$(CONFIG_SND_SOC) += dwc/
16 obj-$(CONFIG_SND_SOC) += fsl/
17 +obj-$(CONFIG_SND_SOC) += gw-avila/
18 obj-$(CONFIG_SND_SOC) += jz4740/
19 obj-$(CONFIG_SND_SOC) += img/
20 obj-$(CONFIG_SND_SOC) += intel/
21 --- /dev/null
22 +++ b/sound/soc/gw-avila/Kconfig
23 @@ -0,0 +1,17 @@
24 +config SND_GW_AVILA_SOC_PCM
25 + tristate
26 +
27 +config SND_GW_AVILA_SOC_HSS
28 + tristate
29 +
30 +config SND_GW_AVILA_SOC
31 + tristate "SoC Audio for the Gateworks AVILA Family"
32 + depends on ARCH_IXP4XX && SND_SOC
33 + select SND_GW_AVILA_SOC_PCM
34 + select SND_GW_AVILA_SOC_HSS
35 + select SND_SOC_TLV320AIC3X
36 + help
37 + Say Y or M if you want to add support for codecs attached to
38 + the Gateworks HSS interface. You will also need
39 + to select the audio interfaces to support below.
40 +
41 --- /dev/null
42 +++ b/sound/soc/gw-avila/Makefile
43 @@ -0,0 +1,8 @@
44 +# Gateworks Avila HSS Platform Support
45 +snd-soc-gw-avila-objs := gw-avila.o ixp4xx_hss.o
46 +snd-soc-gw-avila-pcm-objs := gw-avila-pcm.o
47 +snd-soc-gw-avila-hss-objs := gw-avila-hss.o
48 +
49 +obj-$(CONFIG_SND_GW_AVILA_SOC) += snd-soc-gw-avila.o
50 +obj-$(CONFIG_SND_GW_AVILA_SOC_PCM) += snd-soc-gw-avila-pcm.o
51 +obj-$(CONFIG_SND_GW_AVILA_SOC_HSS) += snd-soc-gw-avila-hss.o
52 --- /dev/null
53 +++ b/sound/soc/gw-avila/gw-avila-hss.c
54 @@ -0,0 +1,103 @@
55 +/*
56 + * gw-avila-hss.c -- HSS Audio Support for Gateworks Avila
57 + *
58 + * Author: Chris Lang <clang@gateworks.com>
59 + *
60 + * This program is free software; you can redistribute it and/or modify
61 + * it under the terms of the GNU General Public License version 2 as
62 + * published by the Free Software Foundation.
63 + */
64 +
65 +#include <linux/init.h>
66 +#include <linux/module.h>
67 +#include <linux/platform_device.h>
68 +#include <linux/interrupt.h>
69 +#include <linux/wait.h>
70 +#include <linux/delay.h>
71 +
72 +#include <sound/core.h>
73 +#include <sound/pcm.h>
74 +#include <sound/ac97_codec.h>
75 +#include <sound/initval.h>
76 +#include <sound/soc.h>
77 +
78 +#include <asm/irq.h>
79 +#include <linux/mutex.h>
80 +#include <linux/gpio.h>
81 +
82 +#include "ixp4xx_hss.h"
83 +#include "gw-avila-hss.h"
84 +
85 +#define gw_avila_hss_suspend NULL
86 +#define gw_avila_hss_resume NULL
87 +
88 +struct snd_soc_dai_driver gw_avila_hss_dai = {
89 + .playback = {
90 + .channels_min = 2,
91 + .channels_max = 2,
92 + .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
93 + SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
94 + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
95 + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
96 + SNDRV_PCM_RATE_KNOT),
97 + .formats = SNDRV_PCM_FMTBIT_S16_LE, },
98 + .capture = {
99 + .channels_min = 2,
100 + .channels_max = 2,
101 + .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
102 + SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
103 + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
104 + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
105 + SNDRV_PCM_RATE_KNOT),
106 + .formats = SNDRV_PCM_FMTBIT_S16_LE, },
107 +};
108 +
109 +static const struct snd_soc_component_driver gw_avila_hss_component = {
110 + .name = "gw_avila_hss",
111 +};
112 +
113 +static int gw_avila_hss_probe(struct platform_device *pdev)
114 +{
115 + int port = (pdev->id < 2) ? 0 : 1;
116 + int channel = (pdev->id % 2);
117 +
118 + hss_handle[pdev->id] = hss_init(port, channel);
119 + if (!hss_handle[pdev->id]) {
120 + return -ENODEV;
121 + }
122 +
123 + return snd_soc_register_component(&pdev->dev, &gw_avila_hss_component,
124 + &gw_avila_hss_dai, 1);
125 +}
126 +
127 +static int gw_avila_hss_remove(struct platform_device *pdev)
128 +{
129 + snd_soc_unregister_component(&pdev->dev);
130 +
131 + return 0;
132 +}
133 +
134 +static struct platform_driver gw_avila_hss_driver = {
135 + .probe = gw_avila_hss_probe,
136 + .remove = gw_avila_hss_remove,
137 + .driver = {
138 + .name = "gw_avila_hss",
139 + .owner = THIS_MODULE,
140 + }
141 +};
142 +
143 +static int __init gw_avila_hss_init(void)
144 +{
145 + return platform_driver_register(&gw_avila_hss_driver);
146 +}
147 +module_init(gw_avila_hss_init);
148 +
149 +static void __exit gw_avila_hss_exit(void)
150 +{
151 + platform_driver_unregister(&gw_avila_hss_driver);
152 +}
153 +module_exit(gw_avila_hss_exit);
154 +
155 +MODULE_AUTHOR("Chris Lang");
156 +MODULE_DESCRIPTION("HSS Audio Driver for Gateworks Avila");
157 +MODULE_LICENSE("GPL");
158 --- /dev/null
159 +++ b/sound/soc/gw-avila/gw-avila-hss.h
160 @@ -0,0 +1,12 @@
161 +/*
162 + * Author: Chris Lang <clang@gateworks.com>
163 + *
164 + * This program is free software; you can redistribute it and/or modify
165 + * it under the terms of the GNU General Public License version 2 as
166 + * published by the Free Software Foundation.
167 + */
168 +
169 +#ifndef _GW_AVILA_HSS_H
170 +#define _GW_AVILA_HSS_H
171 +
172 +#endif
173 --- /dev/null
174 +++ b/sound/soc/gw-avila/gw-avila-pcm.c
175 @@ -0,0 +1,327 @@
176 +/*
177 + * ALSA PCM interface for the TI DAVINCI processor
178 + *
179 + * Author: Chris Lang, <clang@gateworks.com>
180 + * Copyright: (C) 2009 Gateworks Corporation
181 + *
182 + * Based On: davinci-evm.c, Author: Vladimir Barinov, <vbarinov@ru.mvista.com>
183 + *
184 + * This program is free software; you can redistribute it and/or modify
185 + * it under the terms of the GNU General Public License version 2 as
186 + * published by the Free Software Foundation.
187 + */
188 +
189 +#include <linux/module.h>
190 +#include <linux/init.h>
191 +#include <linux/platform_device.h>
192 +#include <linux/slab.h>
193 +#include <linux/dma-mapping.h>
194 +
195 +#include <sound/core.h>
196 +#include <sound/pcm.h>
197 +#include <sound/pcm_params.h>
198 +#include <sound/soc.h>
199 +
200 +#include <asm/dma.h>
201 +
202 +#include "gw-avila-pcm.h"
203 +#include "gw-avila-hss.h"
204 +#include "ixp4xx_hss.h"
205 +
206 +#define GW_AVILA_PCM_DEBUG 0
207 +#if GW_AVILA_PCM_DEBUG
208 +#define DPRINTK(x...) printk(KERN_DEBUG x)
209 +#else
210 +#define DPRINTK(x...)
211 +#endif
212 +
213 +static struct snd_pcm_hardware gw_avila_pcm_hardware = {
214 + .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
215 + SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID),
216 +/* SNDRV_PCM_INFO_PAUSE),*/
217 + .formats = (SNDRV_PCM_FMTBIT_S16_LE),
218 + .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
219 + SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
220 + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
221 + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
222 + SNDRV_PCM_RATE_KNOT),
223 + .rate_min = 8000,
224 + .rate_max = 8000,
225 + .channels_min = 2,
226 + .channels_max = 2,
227 + .buffer_bytes_max = 64 * 1024, // All of the lines below may need to be changed
228 + .period_bytes_min = 128,
229 + .period_bytes_max = 4 * 1024,
230 + .periods_min = 16,
231 + .periods_max = 32,
232 + .fifo_size = 0,
233 +};
234 +
235 +struct gw_avila_runtime_data {
236 + spinlock_t lock;
237 + int period; /* current DMA period */
238 + int master_lch; /* Master DMA channel */
239 + int slave_lch; /* Slave DMA channel */
240 + struct gw_avila_pcm_dma_params *params; /* DMA params */
241 +};
242 +
243 +static void gw_avila_dma_irq(void *data)
244 +{
245 + struct snd_pcm_substream *substream = data;
246 + snd_pcm_period_elapsed(substream);
247 +}
248 +
249 +static int gw_avila_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
250 +{
251 + struct snd_pcm_runtime *runtime = substream->runtime;
252 + struct hss_device *hdev = runtime->private_data;
253 + int ret = 0;
254 +
255 + switch (cmd) {
256 + case SNDRV_PCM_TRIGGER_START:
257 + case SNDRV_PCM_TRIGGER_RESUME:
258 + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
259 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
260 + hss_tx_start(hdev);
261 + else
262 + hss_rx_start(hdev);
263 + break;
264 + case SNDRV_PCM_TRIGGER_STOP:
265 + case SNDRV_PCM_TRIGGER_SUSPEND:
266 + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
267 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
268 + hss_tx_stop(hdev);
269 + else
270 + hss_rx_stop(hdev);
271 + break;
272 + default:
273 + ret = -EINVAL;
274 + break;
275 + }
276 + return ret;
277 +}
278 +
279 +static int gw_avila_pcm_prepare(struct snd_pcm_substream *substream)
280 +{
281 + struct snd_pcm_runtime *runtime = substream->runtime;
282 + struct hss_device *hdev = runtime->private_data;
283 +
284 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
285 + hss_set_tx_callback(hdev, gw_avila_dma_irq, substream);
286 + hss_config_tx_dma(hdev, runtime->dma_area, runtime->buffer_size, runtime->period_size);
287 + } else {
288 + hss_set_rx_callback(hdev, gw_avila_dma_irq, substream);
289 + hss_config_rx_dma(hdev, runtime->dma_area, runtime->buffer_size, runtime->period_size);
290 + }
291 +
292 + return 0;
293 +}
294 +
295 +static snd_pcm_uframes_t
296 +gw_avila_pcm_pointer(struct snd_pcm_substream *substream)
297 +{
298 + struct snd_pcm_runtime *runtime = substream->runtime;
299 + struct hss_device *hdev = runtime->private_data;
300 +
301 + unsigned int curr = 0;
302 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
303 + curr = hss_curr_offset_tx(hdev);
304 + else
305 + curr = hss_curr_offset_rx(hdev);
306 + return curr;
307 +}
308 +
309 +static int gw_avila_pcm_open(struct snd_pcm_substream *substream)
310 +{
311 + struct snd_pcm_runtime *runtime = substream->runtime;
312 + struct snd_soc_pcm_runtime *rtd = substream->private_data;
313 + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
314 +
315 + snd_soc_set_runtime_hwparams(substream, &gw_avila_pcm_hardware);
316 +
317 + if (hss_handle[cpu_dai->id] != NULL)
318 + runtime->private_data = hss_handle[cpu_dai->id];
319 + else {
320 + pr_err("hss_handle is NULL\n");
321 + return -1;
322 + }
323 +
324 + hss_chan_open(hss_handle[cpu_dai->id]);
325 +
326 + return 0;
327 +}
328 +
329 +static int gw_avila_pcm_close(struct snd_pcm_substream *substream)
330 +{
331 + struct snd_pcm_runtime *runtime = substream->runtime;
332 + struct hss_device *hdev = runtime->private_data;
333 +
334 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
335 + memset(hdev->tx_buf, 0, runtime->buffer_size);
336 + } else
337 + memset(hdev->rx_buf, 0, runtime->buffer_size);
338 +
339 + hss_chan_close(hdev);
340 +
341 + return 0;
342 +}
343 +
344 +static int gw_avila_pcm_hw_params(struct snd_pcm_substream *substream,
345 + struct snd_pcm_hw_params *hw_params)
346 +{
347 + return snd_pcm_lib_malloc_pages(substream,
348 + params_buffer_bytes(hw_params));
349 +}
350 +
351 +static int gw_avila_pcm_hw_free(struct snd_pcm_substream *substream)
352 +{
353 + struct snd_pcm_runtime *runtime = substream->runtime;
354 +
355 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
356 + memset(runtime->dma_area, 0, runtime->buffer_size);
357 +
358 + return snd_pcm_lib_free_pages(substream);
359 +}
360 +
361 +static int gw_avila_pcm_mmap(struct snd_pcm_substream *substream,
362 + struct vm_area_struct *vma)
363 +{
364 + struct snd_pcm_runtime *runtime = substream->runtime;
365 +
366 + return dma_mmap_writecombine(substream->pcm->card->dev, vma,
367 + runtime->dma_area,
368 + runtime->dma_addr,
369 + runtime->dma_bytes);
370 +}
371 +
372 +struct snd_pcm_ops gw_avila_pcm_ops = {
373 + .open = gw_avila_pcm_open,
374 + .close = gw_avila_pcm_close,
375 + .ioctl = snd_pcm_lib_ioctl,
376 + .hw_params = gw_avila_pcm_hw_params,
377 + .hw_free = gw_avila_pcm_hw_free,
378 + .prepare = gw_avila_pcm_prepare,
379 + .trigger = gw_avila_pcm_trigger,
380 + .pointer = gw_avila_pcm_pointer,
381 + .mmap = gw_avila_pcm_mmap,
382 +};
383 +
384 +static int gw_avila_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
385 +{
386 + struct snd_pcm_substream *substream = pcm->streams[stream].substream;
387 + struct snd_dma_buffer *buf = &substream->dma_buffer;
388 + size_t size = gw_avila_pcm_hardware.buffer_bytes_max;
389 +
390 + buf->dev.type = SNDRV_DMA_TYPE_DEV;
391 + buf->dev.dev = pcm->card->dev;
392 + buf->private_data = NULL;
393 +
394 + buf->area = dma_alloc_coherent(pcm->card->dev, size,
395 + &buf->addr, GFP_KERNEL);
396 +
397 + if (!buf->area) {
398 + return -ENOMEM;
399 + }
400 +
401 + memset(buf->area, 0xff, size);
402 +
403 + DPRINTK("preallocate_dma_buffer: area=%p, addr=%p, size=%d\n",
404 + (void *) buf->area, (void *) buf->addr, size);
405 +
406 + buf->bytes = size;
407 +
408 + return 0;
409 +}
410 +
411 +static void gw_avila_pcm_free(struct snd_pcm *pcm)
412 +{
413 + struct snd_pcm_substream *substream;
414 + struct snd_dma_buffer *buf;
415 + int stream;
416 +
417 + for (stream = 0; stream < 2; stream++) {
418 + substream = pcm->streams[stream].substream;
419 + if (!substream)
420 + continue;
421 +
422 + buf = &substream->dma_buffer;
423 + if (!buf->area)
424 + continue;
425 +
426 + dma_free_coherent(NULL, buf->bytes, buf->area, 0);
427 + buf->area = NULL;
428 + }
429 +}
430 +
431 +static u64 gw_avila_pcm_dmamask = 0xFFFFFFFF;
432 +
433 +static int gw_avila_pcm_new(struct snd_soc_pcm_runtime *rtd)
434 +{
435 + struct snd_card *card = rtd->card->snd_card;
436 + struct snd_pcm *pcm = rtd->pcm;
437 + struct snd_soc_dai *dai = rtd->codec_dai;
438 + int ret;
439 +
440 + if (!card->dev->dma_mask)
441 + card->dev->dma_mask = &gw_avila_pcm_dmamask;
442 + if (!card->dev->coherent_dma_mask)
443 + card->dev->coherent_dma_mask = 0xFFFFFFFF;
444 +
445 + if (dai->driver->playback.channels_min) {
446 + ret = gw_avila_pcm_preallocate_dma_buffer(pcm,
447 + SNDRV_PCM_STREAM_PLAYBACK);
448 + if (ret)
449 + return ret;
450 + }
451 +
452 + if (dai->driver->capture.channels_min) {
453 + ret = gw_avila_pcm_preallocate_dma_buffer(pcm,
454 + SNDRV_PCM_STREAM_CAPTURE);
455 + if (ret)
456 + return ret;
457 + }
458 +
459 + return 0;
460 +}
461 +
462 +struct snd_soc_platform_driver gw_avila_soc_platform = {
463 + .ops = &gw_avila_pcm_ops,
464 + .pcm_new = gw_avila_pcm_new,
465 + .pcm_free = gw_avila_pcm_free,
466 +};
467 +
468 +static int gw_avila_pcm_platform_probe(struct platform_device *pdev)
469 +{
470 + return snd_soc_register_platform(&pdev->dev, &gw_avila_soc_platform);
471 +}
472 +
473 +static int gw_avila_pcm_platform_remove(struct platform_device *pdev)
474 +{
475 + snd_soc_unregister_platform(&pdev->dev);
476 + return 0;
477 +}
478 +
479 +static struct platform_driver gw_avila_pcm_driver = {
480 + .driver = {
481 + .name = "gw_avila-audio",
482 + .owner = THIS_MODULE,
483 + },
484 + .probe = gw_avila_pcm_platform_probe,
485 + .remove = gw_avila_pcm_platform_remove,
486 +};
487 +
488 +static int __init gw_avila_soc_platform_init(void)
489 +{
490 + return platform_driver_register(&gw_avila_pcm_driver);
491 +}
492 +module_init(gw_avila_soc_platform_init);
493 +
494 +static void __exit gw_avila_soc_platform_exit(void)
495 +{
496 + platform_driver_unregister(&gw_avila_pcm_driver);
497 +}
498 +module_exit(gw_avila_soc_platform_exit);
499 +
500 +MODULE_AUTHOR("Chris Lang");
501 +MODULE_DESCRIPTION("Gateworks Avila PCM DMA module");
502 +MODULE_LICENSE("GPL");
503 --- /dev/null
504 +++ b/sound/soc/gw-avila/gw-avila-pcm.h
505 @@ -0,0 +1,32 @@
506 +/*
507 + * ALSA PCM interface for the Gateworks Avila platform
508 + *
509 + * Author: Chris Lang, <clang@gateworks.com>
510 + * Copyright: (C) 2009 Gateworks Corporation
511 + *
512 + * Based On: davinci-evm.c, Author: Vladimir Barinov, <vbarinov@ru.mvista.com>
513 + *
514 + * This program is free software; you can redistribute it and/or modify
515 + * it under the terms of the GNU General Public License version 2 as
516 + * published by the Free Software Foundation.
517 + */
518 +
519 +#ifndef _GW_AVILA_PCM_H
520 +#define _GW_AVILA_PCM_H
521 +
522 +#if 0
523 +struct gw_avila_pcm_dma_params {
524 + char *name; /* stream identifier */
525 + int channel; /* sync dma channel ID */
526 + dma_addr_t dma_addr; /* device physical address for DMA */
527 + unsigned int data_type; /* xfer data type */
528 +};
529 +
530 +struct gw_avila_snd_platform_data {
531 + int tx_dma_ch; // XXX Do we need this?
532 + int rx_dma_ch; // XXX Do we need this
533 +};
534 +extern struct snd_soc_platform gw_avila_soc_platform[];
535 +#endif
536 +
537 +#endif
538 --- /dev/null
539 +++ b/sound/soc/gw-avila/gw-avila.c
540 @@ -0,0 +1,244 @@
541 +/*
542 + * File: sound/soc/gw-avila/gw_avila.c
543 + * Author: Chris Lang <clang@gateworks.com>
544 + *
545 + * Created: Tue June 06 2008
546 + * Description: Board driver for Gateworks Avila
547 + *
548 + * Modified:
549 + * Copyright 2009 Gateworks Corporation
550 + *
551 + * Bugs: What Bugs?
552 + *
553 + * This program is free software; you can redistribute it and/or modify
554 + * it under the terms of the GNU General Public License as published by
555 + * the Free Software Foundation; either version 2 of the License, or
556 + * (at your option) any later version.
557 + *
558 + * This program is distributed in the hope that it will be useful,
559 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
560 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
561 + * GNU General Public License for more details.
562 + *
563 + * You should have received a copy of the GNU General Public License
564 + * along with this program; if not, see the file COPYING, or write
565 + * to the Free Software Foundation, Inc.,
566 + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
567 + */
568 +
569 +#include <linux/module.h>
570 +#include <linux/moduleparam.h>
571 +#include <linux/device.h>
572 +#include <asm/dma.h>
573 +#include <linux/platform_device.h>
574 +#include <sound/core.h>
575 +#include <sound/pcm.h>
576 +#include <sound/soc.h>
577 +#include <linux/slab.h>
578 +#include <linux/gpio.h>
579 +
580 +#include "ixp4xx_hss.h"
581 +#include "gw-avila-hss.h"
582 +#include "gw-avila-pcm.h"
583 +
584 +#define CODEC_FREQ 33333000
585 +
586 +static int gw_avila_board_startup(struct snd_pcm_substream *substream)
587 +{
588 + pr_debug("%s enter\n", __func__);
589 + return 0;
590 +}
591 +
592 +static int gw_avila_hw_params(struct snd_pcm_substream *substream,
593 + struct snd_pcm_hw_params *params)
594 +{
595 + struct snd_soc_pcm_runtime *rtd = substream->private_data;
596 + struct snd_soc_dai *codec_dai = rtd->codec_dai;
597 + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
598 +
599 + int ret = 0;
600 +
601 + /* set codec DAI configuration */
602 + if (cpu_dai->id % 2) {
603 + ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS);
604 + snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, 1, 32);
605 + } else {
606 + ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM);
607 + snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, 0, 32);
608 + }
609 +
610 + if (ret < 0)
611 + return ret;
612 +
613 + /* set the codec system clock */
614 + ret = snd_soc_dai_set_sysclk(codec_dai, 0, CODEC_FREQ, SND_SOC_CLOCK_OUT);
615 + if (ret < 0)
616 + return ret;
617 +
618 + return 0;
619 +}
620 +
621 +static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
622 + SND_SOC_DAPM_HP("Headphone Jack", NULL),
623 + SND_SOC_DAPM_LINE("Line Out", NULL),
624 + SND_SOC_DAPM_LINE("Line In", NULL),
625 +};
626 +
627 +static const struct snd_soc_dapm_route audio_map[] = {
628 + {"Headphone Jack", NULL, "HPLOUT"},
629 + {"Headphone Jack", NULL, "HPROUT"},
630 +
631 + /* Line Out connected to LLOUT, RLOUT */
632 + {"Line Out", NULL, "LLOUT"},
633 + {"Line Out", NULL, "RLOUT"},
634 +
635 + /* Line In connected to (LINE1L | LINE2L), (LINE1R | LINE2R) */
636 + {"LINE1L", NULL, "Line In"},
637 + {"LINE1R", NULL, "Line In"},
638 +};
639 +
640 +/* Logic for a aic3x as connected on a davinci-evm */
641 +static int avila_aic3x_init(struct snd_soc_pcm_runtime *rtd)
642 +{
643 + struct snd_soc_codec *codec = rtd->codec;
644 + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
645 +
646 + /* Add davinci-evm specific widgets */
647 + snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
648 + ARRAY_SIZE(aic3x_dapm_widgets));
649 +
650 + /* Set up davinci-evm specific audio path audio_map */
651 + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
652 +
653 + /* not connected */
654 + snd_soc_dapm_disable_pin(dapm, "MONO_LOUT");
655 + //snd_soc_dapm_disable_pin(dapm, "HPLCOM");
656 + //snd_soc_dapm_disable_pin(dapm, "HPRCOM");
657 + snd_soc_dapm_disable_pin(dapm, "MIC3L");
658 + snd_soc_dapm_disable_pin(dapm, "MIC3R");
659 + snd_soc_dapm_disable_pin(dapm, "LINE2L");
660 + snd_soc_dapm_disable_pin(dapm, "LINE2R");
661 +
662 + /* always connected */
663 + snd_soc_dapm_enable_pin(dapm, "Headphone Jack");
664 + snd_soc_dapm_enable_pin(dapm, "Line Out");
665 + snd_soc_dapm_enable_pin(dapm, "Line In");
666 +
667 + snd_soc_dapm_sync(dapm);
668 +
669 + return 0;
670 +}
671 +
672 +static struct snd_soc_ops gw_avila_board_ops = {
673 + .startup = gw_avila_board_startup,
674 + .hw_params = gw_avila_hw_params,
675 +};
676 +
677 +static struct snd_soc_dai_link gw_avila_board_dai[] = {
678 + {
679 + .name = "HSS-0",
680 + .stream_name = "HSS-0",
681 + .cpu_dai_name = "gw_avila_hss.0",
682 + .codec_dai_name = "tlv320aic3x-hifi",
683 + .codec_name = "tlv320aic3x-codec.0-001b",
684 + .platform_name = "gw_avila-audio.0",
685 + .init = avila_aic3x_init,
686 + .ops = &gw_avila_board_ops,
687 + },{
688 + .name = "HSS-1",
689 + .stream_name = "HSS-1",
690 + .cpu_dai_name = "gw_avila_hss.1",
691 + .codec_dai_name = "tlv320aic3x-hifi",
692 + .codec_name = "tlv320aic3x-codec.0-001a",
693 + .platform_name = "gw_avila-audio.1",
694 + .init = avila_aic3x_init,
695 + .ops = &gw_avila_board_ops,
696 + },{
697 + .name = "HSS-2",
698 + .stream_name = "HSS-2",
699 + .cpu_dai_name = "gw_avila_hss.2",
700 + .codec_dai_name = "tlv320aic3x-hifi",
701 + .codec_name = "tlv320aic3x-codec.0-0019",
702 + .platform_name = "gw_avila-audio.2",
703 + .init = avila_aic3x_init,
704 + .ops = &gw_avila_board_ops,
705 + },{
706 + .name = "HSS-3",
707 + .stream_name = "HSS-3",
708 + .cpu_dai_name = "gw_avila_hss.3",
709 + .codec_dai_name = "tlv320aic3x-hifi",
710 + .codec_name = "tlv320aic3x-codec.0-0018",
711 + .platform_name = "gw_avila-audio.3",
712 + .init = avila_aic3x_init,
713 + .ops = &gw_avila_board_ops,
714 + },
715 +};
716 +
717 +static struct snd_soc_card gw_avila_board[] = {
718 + {
719 + .name = "gw_avila-board.0",
720 + .owner = THIS_MODULE,
721 + .dai_link = &gw_avila_board_dai[0],
722 + .num_links = 1,
723 + },{
724 + .name = "gw_avila-board.1",
725 + .owner = THIS_MODULE,
726 + .dai_link = &gw_avila_board_dai[1],
727 + .num_links = 1,
728 + },{
729 + .name = "gw_avila-board.2",
730 + .owner = THIS_MODULE,
731 + .dai_link = &gw_avila_board_dai[2],
732 + .num_links = 1,
733 + },{
734 + .name = "gw_avila-board.3",
735 + .owner = THIS_MODULE,
736 + .dai_link = &gw_avila_board_dai[3],
737 + .num_links = 1,
738 + }
739 +};
740 +
741 +static struct platform_device *gw_avila_board_snd_device[4];
742 +
743 +static int __init gw_avila_board_init(void)
744 +{
745 + int ret;
746 + struct port *port;
747 + int i;
748 +
749 + if ((hss_port[0] = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
750 + return -ENOMEM;
751 +
752 + if ((hss_port[1] = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
753 + return -ENOMEM;
754 +
755 + for (i = 0; i < 4; i++) {
756 + gw_avila_board_snd_device[i] = platform_device_alloc("soc-audio", i);
757 + if (!gw_avila_board_snd_device[i]) {
758 + return -ENOMEM;
759 + }
760 +
761 + platform_set_drvdata(gw_avila_board_snd_device[i], &gw_avila_board[i]);
762 + ret = platform_device_add(gw_avila_board_snd_device[i]);
763 +
764 + if (ret) {
765 + platform_device_put(gw_avila_board_snd_device[i]);
766 + }
767 + }
768 + return ret;
769 +}
770 +
771 +static void __exit gw_avila_board_exit(void)
772 +{
773 + int i;
774 + for (i = 0; i < 4; i++)
775 + platform_device_unregister(gw_avila_board_snd_device[i]);
776 +}
777 +
778 +module_init(gw_avila_board_init);
779 +module_exit(gw_avila_board_exit);
780 +
781 +/* Module information */
782 +MODULE_AUTHOR("Chris Lang");
783 +MODULE_DESCRIPTION("ALSA SoC HSS Audio gw_avila board");
784 +MODULE_LICENSE("GPL");
785 --- /dev/null
786 +++ b/sound/soc/gw-avila/ixp4xx_hss.c
787 @@ -0,0 +1,902 @@
788 +/*
789 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
790 + *
791 + * Copyright (C) 2009 Chris Lang <clang@gateworks.com>
792 + *
793 + * This program is free software; you can redistribute it and/or modify it
794 + * under the terms of version 2 of the GNU General Public License
795 + * as published by the Free Software Foundation.
796 + */
797 +
798 +#include <linux/module.h>
799 +#include <linux/bitops.h>
800 +#include <linux/cdev.h>
801 +#include <linux/dma-mapping.h>
802 +#include <linux/dmapool.h>
803 +#include <linux/fs.h>
804 +#include <linux/io.h>
805 +#include <linux/kernel.h>
806 +#include <linux/platform_device.h>
807 +#include <linux/poll.h>
808 +#include <linux/slab.h>
809 +#include <linux/delay.h>
810 +
811 +#include <mach/npe.h>
812 +#include <mach/qmgr.h>
813 +
814 +#include "ixp4xx_hss.h"
815 +
816 +/*****************************************************************************
817 + * global variables
818 + ****************************************************************************/
819 +
820 +void hss_chan_read(unsigned long data);
821 +static char lock_init = 0;
822 +static spinlock_t npe_lock;
823 +static struct npe *npe;
824 +
825 +static const struct {
826 + int tx, txdone, rx, rxfree, chan;
827 +}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
828 + HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE},
829 + {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
830 + HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE},
831 +};
832 +
833 +struct port *hss_port[2];
834 +struct hss_device *hss_handle[32];
835 +EXPORT_SYMBOL(hss_handle);
836 +
837 +/*****************************************************************************
838 + * utility functions
839 + ****************************************************************************/
840 +
841 +#ifndef __ARMEB__
842 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
843 +{
844 + int i;
845 + for (i = 0; i < cnt; i++)
846 + dest[i] = swab32(src[i]);
847 +}
848 +#endif
849 +
850 +static inline unsigned int sub_offset(unsigned int a, unsigned int b,
851 + unsigned int modulo)
852 +{
853 + return (modulo /* make sure the result >= 0 */ + a - b) % modulo;
854 +}
855 +
856 +/*****************************************************************************
857 + * HSS access
858 + ****************************************************************************/
859 +
860 +static void hss_config_load(struct port *port)
861 +{
862 + struct msg msg;
863 +
864 + do {
865 + memset(&msg, 0, sizeof(msg));
866 + msg.cmd = PORT_CONFIG_LOAD;
867 + msg.hss_port = port->id;
868 + if (npe_send_message(npe, &msg, "HSS_LOAD_CONFIG"))
869 + break;
870 + if (npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG"))
871 + break;
872 +
873 + /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
874 + if (msg.cmd != PORT_CONFIG_LOAD || msg.data32)
875 + break;
876 +
877 + /* HDLC may stop working without this */
878 + npe_recv_message(npe, &msg, "FLUSH_IT");
879 + return;
880 + } while (0);
881 +
882 + printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n",
883 + port->id);
884 + BUG();
885 +}
886 +
887 +static void hss_config_set_pcr(struct port *port)
888 +{
889 + struct msg msg;
890 +
891 + do {
892 + memset(&msg, 0, sizeof(msg));
893 + msg.cmd = PORT_CONFIG_WRITE;
894 + msg.hss_port = port->id;
895 + msg.index = HSS_CONFIG_TX_PCR;
896 +#if 0
897 + msg.data32 = PCR_FRM_SYNC_RISINGEDGE | PCR_MSB_ENDIAN |
898 + PCR_TX_DATA_ENABLE | PCR_TX_UNASS_HIGH_IMP | PCR_TX_V56K_HIGH_IMP | PCR_TX_FB_HIGH_IMP;
899 +#else
900 + msg.data32 = PCR_FRM_SYNC_RISINGEDGE | PCR_MSB_ENDIAN |
901 + PCR_TX_DATA_ENABLE | PCR_TX_FB_HIGH_IMP | PCR_DCLK_EDGE_RISING;
902 +#endif
903 + if (port->frame_size % 8 == 0)
904 + msg.data32 |= PCR_SOF_NO_FBIT;
905 +
906 + if (npe_send_message(npe, &msg, "HSS_SET_TX_PCR"))
907 + break;
908 +
909 + msg.index = HSS_CONFIG_RX_PCR;
910 + msg.data32 &= ~ (PCR_DCLK_EDGE_RISING | PCR_FCLK_EDGE_RISING | PCR_TX_DATA_ENABLE);
911 +
912 + if (npe_send_message(npe, &msg, "HSS_SET_RX_PCR"))
913 + break;
914 + return;
915 + } while (0);
916 +
917 + printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id);
918 + BUG();
919 +}
920 +
921 +static void hss_config_set_core(struct port *port)
922 +{
923 + struct msg msg;
924 +
925 + memset(&msg, 0, sizeof(msg));
926 + msg.cmd = PORT_CONFIG_WRITE;
927 + msg.hss_port = port->id;
928 + msg.index = HSS_CONFIG_CORE_CR;
929 +#if 0
930 + msg.data32 = 0 | CCR_LOOPBACK |
931 + (port->id ? CCR_SECOND_HSS : 0);
932 +#else
933 + msg.data32 = 0 |
934 + (port->id ? CCR_SECOND_HSS : 0);
935 +#endif
936 + if (npe_send_message(npe, &msg, "HSS_SET_CORE_CR")) {
937 + printk(KERN_CRIT "HSS-%i: unable to set HSS core control"
938 + " register\n", port->id);
939 + BUG();
940 + }
941 +}
942 +
943 +static void hss_config_set_line(struct port *port)
944 +{
945 + struct msg msg;
946 +
947 + hss_config_set_pcr(port);
948 + hss_config_set_core(port);
949 +
950 + memset(&msg, 0, sizeof(msg));
951 + msg.cmd = PORT_CONFIG_WRITE;
952 + msg.hss_port = port->id;
953 + msg.index = HSS_CONFIG_CLOCK_CR;
954 + msg.data32 = CLK42X_SPEED_8192KHZ /* FIXME */;
955 + if (npe_send_message(npe, &msg, "HSS_SET_CLOCK_CR")) {
956 + printk(KERN_CRIT "HSS-%i: unable to set HSS clock control"
957 + " register\n", port->id);
958 + BUG();
959 + }
960 +}
961 +
962 +static void hss_config_set_rx_frame(struct port *port)
963 +{
964 + struct msg msg;
965 +
966 + memset(&msg, 0, sizeof(msg));
967 + msg.cmd = PORT_CONFIG_WRITE;
968 + msg.hss_port = port->id;
969 + msg.index = HSS_CONFIG_RX_FCR;
970 + msg.data16a = port->frame_sync_offset;
971 + msg.data16b = port->frame_size - 1;
972 + if (npe_send_message(npe, &msg, "HSS_SET_RX_FCR")) {
973 + printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size"
974 + " and offset\n", port->id);
975 + BUG();
976 + }
977 +}
978 +
979 +static void hss_config_set_frame(struct port *port)
980 +{
981 + struct msg msg;
982 +
983 + memset(&msg, 0, sizeof(msg));
984 + msg.cmd = PORT_CONFIG_WRITE;
985 + msg.hss_port = port->id;
986 + msg.index = HSS_CONFIG_TX_FCR;
987 + msg.data16a = TX_FRAME_SYNC_OFFSET;
988 + msg.data16b = port->frame_size - 1;
989 + if (npe_send_message(npe, &msg, "HSS_SET_TX_FCR")) {
990 + printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size"
991 + " and offset\n", port->id);
992 + BUG();
993 + }
994 + hss_config_set_rx_frame(port);
995 +}
996 +
997 +static void hss_config_set_lut(struct port *port)
998 +{
999 + struct msg msg;
1000 + int chan_count = 32;
1001 +
1002 + memset(&msg, 0, sizeof(msg));
1003 + msg.cmd = PORT_CONFIG_WRITE;
1004 + msg.hss_port = port->id;
1005 +
1006 + msg.index = HSS_CONFIG_TX_LUT;
1007 + msg.data32 = 0xffffffff;
1008 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1009 + msg.index += 4;
1010 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1011 + msg.data32 = 0x0;
1012 + msg.index += 4;
1013 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1014 + msg.index += 4;
1015 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1016 + msg.index += 4;
1017 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1018 + msg.index += 4;
1019 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1020 + msg.index += 4;
1021 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1022 + msg.index += 4;
1023 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1024 +
1025 + msg.index = HSS_CONFIG_RX_LUT;
1026 + msg.data32 = 0xffffffff;
1027 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1028 + msg.index += 4;
1029 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1030 + msg.data32 = 0x0;
1031 + msg.index += 4;
1032 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1033 + msg.index += 4;
1034 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1035 + msg.index += 4;
1036 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1037 + msg.index += 4;
1038 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1039 + msg.index += 4;
1040 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1041 + msg.index += 4;
1042 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1043 +
1044 + hss_config_set_frame(port);
1045 +
1046 + memset(&msg, 0, sizeof(msg));
1047 + msg.cmd = CHAN_NUM_CHANS_WRITE;
1048 + msg.hss_port = port->id;
1049 + msg.data8a = chan_count;
1050 + if (npe_send_message(npe, &msg, "CHAN_NUM_CHANS_WRITE")) {
1051 + printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n",
1052 + port->id);
1053 + BUG();
1054 + }
1055 +}
1056 +
1057 +static u32 hss_config_get_status(struct port *port)
1058 +{
1059 + struct msg msg;
1060 +
1061 + do {
1062 + memset(&msg, 0, sizeof(msg));
1063 + msg.cmd = PORT_ERROR_READ;
1064 + msg.hss_port = port->id;
1065 + if (npe_send_message(npe, &msg, "PORT_ERROR_READ"))
1066 + break;
1067 + if (npe_recv_message(npe, &msg, "PORT_ERROR_READ"))
1068 + break;
1069 +
1070 + return msg.data32;
1071 + } while (0);
1072 +
1073 + printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id);
1074 + BUG();
1075 +}
1076 +
1077 +static void hss_config_start_chan(struct port *port)
1078 +{
1079 + struct msg msg;
1080 +
1081 + port->chan_last_tx = 0;
1082 + port->chan_last_rx = 0;
1083 +
1084 + do {
1085 + memset(&msg, 0, sizeof(msg));
1086 + msg.cmd = CHAN_RX_BUF_ADDR_WRITE;
1087 + msg.hss_port = port->id;
1088 + msg.data32 = port->chan_rx_buf_phys;
1089 + if (npe_send_message(npe, &msg, "CHAN_RX_BUF_ADDR_WRITE"))
1090 + break;
1091 +
1092 + memset(&msg, 0, sizeof(msg));
1093 + msg.cmd = CHAN_TX_BUF_ADDR_WRITE;
1094 + msg.hss_port = port->id;
1095 + msg.data32 = port->chan_tx_pointers_phys;
1096 + if (npe_send_message(npe, &msg, "CHAN_TX_BUF_ADDR_WRITE"))
1097 + break;
1098 +
1099 + memset(&msg, 0, sizeof(msg));
1100 + msg.cmd = CHAN_FLOW_ENABLE;
1101 + msg.hss_port = port->id;
1102 + if (npe_send_message(npe, &msg, "CHAN_FLOW_ENABLE"))
1103 + break;
1104 + port->chan_started = 1;
1105 + return;
1106 + } while (0);
1107 +
1108 + printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n",
1109 + port->id);
1110 + BUG();
1111 +}
1112 +
1113 +static void hss_config_stop_chan(struct port *port)
1114 +{
1115 + struct msg msg;
1116 +
1117 + if (!port->chan_started)
1118 + return;
1119 +
1120 + memset(&msg, 0, sizeof(msg));
1121 + msg.cmd = CHAN_FLOW_DISABLE;
1122 + msg.hss_port = port->id;
1123 + if (npe_send_message(npe, &msg, "CHAN_FLOW_DISABLE")) {
1124 + printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n",
1125 + port->id);
1126 + BUG();
1127 + }
1128 + hss_config_get_status(port); /* make sure it's halted */
1129 + port->chan_started = 0;
1130 +}
1131 +
1132 +static int hss_config_load_firmware(struct port *port)
1133 +{
1134 + struct msg msg;
1135 +
1136 + if (port->initialized)
1137 + return 0;
1138 +
1139 + if (!npe_running(npe)) {
1140 + int err;
1141 + if ((err = npe_load_firmware(npe, "NPE-A-HSS",
1142 + port->dev)))
1143 + return err;
1144 + }
1145 +
1146 + do {
1147 + /* HSS main configuration */
1148 + hss_config_set_line(port);
1149 +
1150 + hss_config_set_frame(port);
1151 +
1152 + /* Channelized operation settings */
1153 + memset(&msg, 0, sizeof(msg));
1154 + msg.cmd = CHAN_TX_BLK_CFG_WRITE;
1155 + msg.hss_port = port->id;
1156 + msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2;
1157 + msg.data8a = msg.data8b / 4;
1158 + msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b;
1159 + msg.data8c = msg.data8d / 4;
1160 + if (npe_send_message(npe, &msg, "CHAN_TX_BLK_CFG_WRITE"))
1161 + break;
1162 +
1163 + memset(&msg, 0, sizeof(msg));
1164 + msg.cmd = CHAN_RX_BUF_CFG_WRITE;
1165 + msg.hss_port = port->id;
1166 + msg.data8a = CHAN_RX_TRIGGER / 8;
1167 + msg.data8b = CHAN_RX_FRAMES;
1168 + if (npe_send_message(npe, &msg, "CHAN_RX_BUF_CFG_WRITE"))
1169 + break;
1170 +
1171 + memset(&msg, 0, sizeof(msg));
1172 + msg.cmd = CHAN_TX_BUF_SIZE_WRITE;
1173 + msg.hss_port = port->id;
1174 + msg.data8a = CHAN_TX_LISTS;
1175 + if (npe_send_message(npe, &msg, "CHAN_TX_BUF_SIZE_WRITE"))
1176 + break;
1177 +
1178 + port->initialized = 1;
1179 + return 0;
1180 + } while (0);
1181 +
1182 + printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id);
1183 + BUG();
1184 +}
1185 +
1186 +void hss_chan_irq(void *pdev)
1187 +{
1188 + struct port *port = pdev;
1189 +
1190 + qmgr_disable_irq(queue_ids[port->id].chan);
1191 +
1192 + tasklet_hi_schedule(&port->task);
1193 +}
1194 +
1195 +
1196 +int hss_prepare_chan(struct port *port)
1197 +{
1198 + int err, i, j;
1199 + u32 *temp;
1200 + u32 temp2;
1201 + u8 *temp3;
1202 +
1203 + if (port->initialized)
1204 + return 0;
1205 +
1206 + if ((err = hss_config_load_firmware(port)))
1207 + return err;
1208 +
1209 + if ((err = qmgr_request_queue(queue_ids[port->id].chan,
1210 + CHAN_QUEUE_LEN, 0, 0, "%s:hss", "hss")))
1211 + return err;
1212 +
1213 + port->chan_tx_buf = dma_alloc_coherent(port->dev, chan_tx_buf_len(port), &port->chan_tx_buf_phys, GFP_DMA);
1214 + memset(port->chan_tx_buf, 0, chan_tx_buf_len(port));
1215 +
1216 + port->chan_tx_pointers = dma_alloc_coherent(port->dev, chan_tx_buf_len(port) / CHAN_TX_LIST_FRAMES * 4, &port->chan_tx_pointers_phys, GFP_DMA);
1217 +
1218 + temp3 = port->chan_tx_buf;
1219 + for (i = 0; i < CHAN_TX_LISTS; i++) {
1220 + for (j = 0; j < 8; j++) {
1221 + port->tx_lists[i][j] = temp3;
1222 + temp3 += CHAN_TX_LIST_FRAMES * 4;
1223 + }
1224 + }
1225 +
1226 + temp = port->chan_tx_pointers;
1227 + temp2 = port->chan_tx_buf_phys;
1228 + for (i = 0; i < CHAN_TX_LISTS; i++)
1229 + {
1230 + for (j = 0; j < 32; j++)
1231 + {
1232 + *temp = temp2;
1233 + temp2 += CHAN_TX_LIST_FRAMES;
1234 + temp++;
1235 + }
1236 + }
1237 +
1238 + port->chan_rx_buf = dma_alloc_coherent(port->dev, chan_rx_buf_len(port), &port->chan_rx_buf_phys, GFP_DMA);
1239 +
1240 + for (i = 0; i < 8; i++) {
1241 + temp3 = port->chan_rx_buf + (i * 4 * 128);
1242 + for (j = 0; j < 8; j++) {
1243 + port->rx_frames[i][j] = temp3;
1244 + temp3 += CHAN_RX_TRIGGER;
1245 + }
1246 + }
1247 +
1248 + qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY,
1249 + hss_chan_irq, port);
1250 +
1251 + return 0;
1252 +
1253 +}
1254 +
1255 +int hss_tx_start(struct hss_device *hdev)
1256 +{
1257 + unsigned long flags;
1258 + struct port *port = hdev->port;
1259 +
1260 + hdev->tx_loc = 0;
1261 + hdev->tx_frame = 0;
1262 +
1263 + set_bit((1 << hdev->id), &port->chan_tx_bitmap);
1264 +
1265 + if (!port->chan_started)
1266 + {
1267 + qmgr_enable_irq(queue_ids[port->id].chan);
1268 + spin_lock_irqsave(&npe_lock, flags);
1269 + hss_config_start_chan(port);
1270 + spin_unlock_irqrestore(&npe_lock, flags);
1271 + hss_chan_irq(port);
1272 + }
1273 +
1274 + return 0;
1275 +}
1276 +EXPORT_SYMBOL(hss_tx_start);
1277 +
1278 +int hss_rx_start(struct hss_device *hdev)
1279 +{
1280 + unsigned long flags;
1281 + struct port *port = hdev->port;
1282 +
1283 + hdev->rx_loc = 0;
1284 + hdev->rx_frame = 0;
1285 +
1286 + set_bit((1 << hdev->id), &port->chan_rx_bitmap);
1287 +
1288 + if (!port->chan_started)
1289 + {
1290 + qmgr_enable_irq(queue_ids[port->id].chan);
1291 + spin_lock_irqsave(&npe_lock, flags);
1292 + hss_config_start_chan(port);
1293 + spin_unlock_irqrestore(&npe_lock, flags);
1294 + hss_chan_irq(port);
1295 + }
1296 +
1297 + return 0;
1298 +}
1299 +EXPORT_SYMBOL(hss_rx_start);
1300 +
1301 +int hss_tx_stop(struct hss_device *hdev)
1302 +{
1303 + struct port *port = hdev->port;
1304 +
1305 + clear_bit((1 << hdev->id), &port->chan_tx_bitmap);
1306 +
1307 + return 0;
1308 +}
1309 +EXPORT_SYMBOL(hss_tx_stop);
1310 +
1311 +int hss_rx_stop(struct hss_device *hdev)
1312 +{
1313 + struct port *port = hdev->port;
1314 +
1315 + clear_bit((1 << hdev->id), &port->chan_rx_bitmap);
1316 +
1317 + return 0;
1318 +}
1319 +EXPORT_SYMBOL(hss_rx_stop);
1320 +
1321 +int hss_chan_open(struct hss_device *hdev)
1322 +{
1323 + struct port *port = hdev->port;
1324 + int i, err = 0;
1325 +
1326 + if (port->chan_open)
1327 + return 0;
1328 +
1329 + if (port->mode == MODE_HDLC) {
1330 + err = -ENOSYS;
1331 + goto out;
1332 + }
1333 +
1334 + if (port->mode == MODE_G704 && port->channels[0] == hdev->id) {
1335 + err = -EBUSY; /* channel #0 is used for G.704 signaling */
1336 + goto out;
1337 + }
1338 +
1339 + for (i = MAX_CHANNELS; i > port->frame_size / 8; i--)
1340 + if (port->channels[i - 1] == hdev->id) {
1341 + err = -ECHRNG; /* frame too short */
1342 + goto out;
1343 + }
1344 +
1345 + hdev->rx_loc = hdev->tx_loc = 0;
1346 + hdev->rx_frame = hdev->tx_frame = 0;
1347 +
1348 + //clear_bit((1 << hdev->id), &port->chan_rx_bitmap);
1349 + //clear_bit((1 << hdev->id), &port->chan_tx_bitmap);
1350 +
1351 + if (!port->initialized) {
1352 + hss_prepare_chan(port);
1353 +
1354 + hss_config_stop_chan(port);
1355 + hdev->open_count++;
1356 + port->chan_open_count++;
1357 +
1358 + hss_config_set_lut(port);
1359 + hss_config_load(port);
1360 +
1361 + }
1362 + port->chan_open = 1;
1363 +
1364 +out:
1365 + return err;
1366 +}
1367 +EXPORT_SYMBOL(hss_chan_open);
1368 +
1369 +int hss_chan_close(struct hss_device *hdev)
1370 +{
1371 + return 0;
1372 +}
1373 +EXPORT_SYMBOL(hss_chan_close);
1374 +
1375 +void hss_chan_read(unsigned long data)
1376 +{
1377 + struct port *port = (void *)data;
1378 + struct hss_device *hdev;
1379 + u8 *hw_buf, *save_buf;
1380 + u8 *buf;
1381 + u32 v;
1382 + unsigned int tx_list, rx_frame;
1383 + int i, j, channel;
1384 + u8 more_work = 0;
1385 +
1386 +/*
1387 + My Data in the hardware buffer is scattered by channels into 4 trunks
1388 + as follows for rx
1389 +
1390 + channel 0 channel 1 channel 2 channel 3
1391 +Trunk 1 = 0 -> 127 128 -> 255 256 -> 383 384 -> 512
1392 +Trunk 2 = 513 -> 639 640 -> 768 769 -> 895 896 -> 1023
1393 +Trunk 3 = 1024 -> 1151 1152 -> 1207 1208 -> 1407 1408 -> 1535
1394 +Trunk 4 = 1535 -> 1663 1664 -> 1791 1792 -> 1920 1921 -> 2047
1395 +
1396 + I will get CHAN_RX_TRIGGER worth of bytes out of each channel on each trunk
1397 + with each IRQ
1398 +
1399 + For TX Data, it is split into 8 lists with each list containing 16 bytes per
1400 + channel
1401 +
1402 +Trunk 1 = 0 -> 16 17 -> 32 33 -> 48 49 -> 64
1403 +Trunk 2 = 65 -> 80 81 -> 96 97 -> 112 113 -> 128
1404 +Trunk 3 = 129 -> 144 145 -> 160 161 -> 176 177 -> 192
1405 +Trunk 4 = 193 -> 208 209 -> 224 225 -> 240 241 -> 256
1406 +
1407 +*/
1408 +
1409 +
1410 + while ((v = qmgr_get_entry(queue_ids[port->id].chan)))
1411 + {
1412 + tx_list = (v >> 8) & 0xFF;
1413 + rx_frame = v & 0xFF;
1414 +
1415 + if (tx_list == 7)
1416 + tx_list = 0;
1417 + else
1418 + tx_list++;
1419 + for (channel = 0; channel < 8; channel++) {
1420 +
1421 + hdev = port->chan_devices[channel];
1422 + if (!hdev)
1423 + continue;
1424 +
1425 + if (test_bit(1 << channel, &port->chan_tx_bitmap)) {
1426 + buf = (u8 *)hdev->tx_buf + hdev->tx_loc;
1427 +#if 0
1428 + hw_buf = (u8 *)port->chan_tx_buf;
1429 + hw_buf += (tx_list * CHAN_TX_LIST_FRAMES * 32);
1430 + hw_buf += (4 * CHAN_TX_LIST_FRAMES * channel);
1431 + save_buf = hw_buf;
1432 +#else
1433 + save_buf = port->tx_lists[tx_list][channel];
1434 +#endif
1435 + for (i = 0; i < CHAN_TX_LIST_FRAMES; i++) {
1436 + hw_buf = save_buf + i;
1437 + for (j = 0; j < 4; j++) {
1438 + *hw_buf = *(buf++);
1439 + hw_buf += CHAN_TX_LIST_FRAMES;
1440 + }
1441 +
1442 + hdev->tx_loc += 4;
1443 + hdev->tx_frame++;
1444 + if (hdev->tx_loc >= hdev->tx_buffer_size) {
1445 + hdev->tx_loc = 0;
1446 + buf = (u8 *)hdev->tx_buf;
1447 + }
1448 + }
1449 + } else {
1450 +#if 0
1451 + hw_buf = (u8 *)port->chan_tx_buf;
1452 + hw_buf += (tx_list * CHAN_TX_LIST_FRAMES * 32);
1453 + hw_buf += (4 * CHAN_TX_LIST_FRAMES * channel);
1454 +#else
1455 + hw_buf = port->tx_lists[tx_list][channel];
1456 +#endif
1457 + memset(hw_buf, 0, 64);
1458 + }
1459 +
1460 + if (hdev->tx_frame >= hdev->tx_period_size && test_bit(1 << channel, &port->chan_tx_bitmap))
1461 + {
1462 + hdev->tx_frame %= hdev->tx_period_size;
1463 + if (hdev->tx_callback)
1464 + hdev->tx_callback(hdev->tx_data);
1465 + more_work = 1;
1466 + }
1467 +
1468 + if (test_bit(1 << channel, &port->chan_rx_bitmap)) {
1469 + buf = (u8 *)hdev->rx_buf + hdev->rx_loc;
1470 +#if 0
1471 + hw_buf = (u8 *)port->chan_rx_buf;
1472 + hw_buf += (4 * CHAN_RX_FRAMES * channel);
1473 + hw_buf += rx_frame;
1474 + save_buf = hw_buf;
1475 +#else
1476 + save_buf = port->rx_frames[channel][rx_frame >> 4];
1477 +#endif
1478 + for (i = 0; i < CHAN_RX_TRIGGER; i++) {
1479 + hw_buf = save_buf + i;
1480 + for (j = 0; j < 4; j++) {
1481 + *(buf++) = *hw_buf;
1482 + hw_buf += CHAN_RX_FRAMES;
1483 + }
1484 + hdev->rx_loc += 4;
1485 + hdev->rx_frame++;
1486 + if (hdev->rx_loc >= hdev->rx_buffer_size) {
1487 + hdev->rx_loc = 0;
1488 + buf = (u8 *)hdev->rx_buf;
1489 + }
1490 + }
1491 + }
1492 +
1493 + if (hdev->rx_frame >= hdev->rx_period_size && test_bit(1 << channel, &port->chan_rx_bitmap))
1494 + {
1495 + hdev->rx_frame %= hdev->rx_period_size;
1496 + if (hdev->rx_callback)
1497 + hdev->rx_callback(hdev->rx_data);
1498 + more_work = 1;
1499 + }
1500 + }
1501 +#if 0
1502 + if (more_work)
1503 + {
1504 + tasklet_hi_schedule(&port->task);
1505 + return;
1506 + }
1507 +#endif
1508 + }
1509 +
1510 + qmgr_enable_irq(queue_ids[port->id].chan);
1511 +
1512 + return;
1513 +
1514 +}
1515 +
1516 +struct hss_device *hss_chan_create(struct port *port, unsigned int channel)
1517 +{
1518 + struct hss_device *chan_dev;
1519 + unsigned long flags;
1520 +
1521 + chan_dev = kzalloc(sizeof(struct hss_device), GFP_KERNEL);
1522 +
1523 + spin_lock_irqsave(&npe_lock, flags);
1524 +
1525 + chan_dev->id = channel;
1526 + chan_dev->port = port;
1527 +
1528 + port->channels[channel] = channel;
1529 +
1530 + port->chan_devices[channel] = chan_dev;
1531 +
1532 + spin_unlock_irqrestore(&npe_lock, flags);
1533 +
1534 + return chan_dev;
1535 +}
1536 +
1537 +/*****************************************************************************
1538 + * initialization
1539 + ****************************************************************************/
1540 +
1541 +static struct platform_device gw_avila_hss_device_0 = {
1542 + .name = "ixp4xx_hss",
1543 + .id = 0,
1544 +};
1545 +
1546 +static struct platform_device gw_avila_hss_device_1 = {
1547 + .name = "ixp4xx_hss",
1548 + .id = 1,
1549 +};
1550 +
1551 +static struct platform_device *gw_avila_hss_port_0;
1552 +static struct platform_device *gw_avila_hss_port_1;
1553 +static u64 hss_dmamask = 0xFFFFFFFF;
1554 +
1555 +struct hss_device *hss_init(int id, int channel)
1556 +{
1557 + struct port *port = hss_port[id];
1558 + struct hss_device *hdev;
1559 + int ret;
1560 +
1561 + if (!lock_init)
1562 + {
1563 + spin_lock_init(&npe_lock);
1564 + lock_init = 1;
1565 + npe = npe_request(0);
1566 + }
1567 +
1568 + if (!port->init) {
1569 + if (id == 0) {
1570 + gw_avila_hss_port_0 = platform_device_alloc("hss-port", 0);
1571 +
1572 + platform_set_drvdata(gw_avila_hss_port_0, &gw_avila_hss_device_0);
1573 + port->dev = &gw_avila_hss_port_0->dev;
1574 +
1575 + if (!port->dev->dma_mask)
1576 + port->dev->dma_mask = &hss_dmamask;
1577 + if (!port->dev->coherent_dma_mask)
1578 + port->dev->coherent_dma_mask = 0xFFFFFFFF;
1579 +
1580 + ret = platform_device_add(gw_avila_hss_port_0);
1581 +
1582 + if (ret)
1583 + platform_device_put(gw_avila_hss_port_0);
1584 +
1585 + tasklet_init(&port->task, hss_chan_read, (unsigned long) port);
1586 + }
1587 + else
1588 + {
1589 + gw_avila_hss_port_1 = platform_device_alloc("hss-port", 1);
1590 +
1591 + platform_set_drvdata(gw_avila_hss_port_1, &gw_avila_hss_device_1);
1592 + port->dev = &gw_avila_hss_port_1->dev;
1593 +
1594 + if (!port->dev->dma_mask)
1595 + port->dev->dma_mask = &hss_dmamask;
1596 + if (!port->dev->coherent_dma_mask)
1597 + port->dev->coherent_dma_mask = 0xFFFFFFFF;
1598 +
1599 + ret = platform_device_add(gw_avila_hss_port_1);
1600 +
1601 + if (ret)
1602 + platform_device_put(gw_avila_hss_port_1);
1603 +
1604 + tasklet_init(&port->task, hss_chan_read, (unsigned long) port);
1605 + }
1606 +
1607 + port->init = 1;
1608 + port->id = id;
1609 + port->clock_type = CLOCK_EXT;
1610 + port->clock_rate = 8192000;
1611 + port->frame_size = 256; /* E1 */
1612 + port->mode = MODE_RAW;
1613 + port->next_rx_frame = 0;
1614 + memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels));
1615 + }
1616 +
1617 + hdev = hss_chan_create(port, channel);
1618 +
1619 + return hdev;
1620 +}
1621 +EXPORT_SYMBOL(hss_init);
1622 +
1623 +int hss_set_tx_callback(struct hss_device *hdev, void (*tx_callback)(void *), void *tx_data)
1624 +{
1625 + BUG_ON(tx_callback == NULL);
1626 + hdev->tx_callback = tx_callback;
1627 + hdev->tx_data = tx_data;
1628 +
1629 + return 0;
1630 +}
1631 +EXPORT_SYMBOL(hss_set_tx_callback);
1632 +
1633 +int hss_set_rx_callback(struct hss_device *hdev, void (*rx_callback)(void *), void *rx_data)
1634 +{
1635 + BUG_ON(rx_callback == NULL);
1636 + hdev->rx_callback = rx_callback;
1637 + hdev->rx_data = rx_data;
1638 +
1639 + return 0;
1640 +}
1641 +EXPORT_SYMBOL(hss_set_rx_callback);
1642 +
1643 +int hss_config_rx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size)
1644 +{
1645 + /*
1646 + * Period Size and Buffer Size are in Frames which are u32
1647 + * We convert the u32 *buf to u8 in order to make channel reads
1648 + * and rx_loc easier
1649 + */
1650 +
1651 + hdev->rx_buf = (u8 *)buf;
1652 + hdev->rx_buffer_size = buffer_size << 2;
1653 + hdev->rx_period_size = period_size;
1654 +
1655 + return 0;
1656 +}
1657 +EXPORT_SYMBOL(hss_config_rx_dma);
1658 +
1659 +int hss_config_tx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size)
1660 +{
1661 + /*
1662 + * Period Size and Buffer Size are in Frames which are u32
1663 + * We convert the u32 *buf to u8 in order to make channel reads
1664 + * and rx_loc easier
1665 + */
1666 +
1667 + hdev->tx_buf = (u8 *)buf;
1668 + hdev->tx_buffer_size = buffer_size << 2;
1669 + hdev->tx_period_size = period_size;
1670 +
1671 + return 0;
1672 +}
1673 +EXPORT_SYMBOL(hss_config_tx_dma);
1674 +
1675 +unsigned long hss_curr_offset_rx(struct hss_device *hdev)
1676 +{
1677 + return hdev->rx_loc >> 2;
1678 +}
1679 +EXPORT_SYMBOL(hss_curr_offset_rx);
1680 +
1681 +unsigned long hss_curr_offset_tx(struct hss_device *hdev)
1682 +{
1683 + return hdev->tx_loc >> 2;
1684 +}
1685 +EXPORT_SYMBOL(hss_curr_offset_tx);
1686 +
1687 +MODULE_AUTHOR("Chris Lang");
1688 +MODULE_DESCRIPTION("Intel IXP4xx HSS Audio driver");
1689 +MODULE_LICENSE("GPL v2");
1690 --- /dev/null
1691 +++ b/sound/soc/gw-avila/ixp4xx_hss.h
1692 @@ -0,0 +1,401 @@
1693 +/*
1694 + *
1695 + *
1696 + * Copyright (C) 2009 Gateworks Corporation
1697 + *
1698 + * This program is free software; you can redistribute it and/or modify it
1699 + * under the terms of version 2 of the GNU General Public License
1700 + * as published by the Free Software Foundation.
1701 + */
1702 +
1703 +#include <linux/types.h>
1704 +#include <linux/bitops.h>
1705 +#include <linux/dma-mapping.h>
1706 +#include <linux/dmapool.h>
1707 +#include <linux/fs.h>
1708 +#include <linux/io.h>
1709 +#include <linux/kernel.h>
1710 +#include <linux/platform_device.h>
1711 +#include <linux/poll.h>
1712 +#include <mach/npe.h>
1713 +#include <mach/qmgr.h>
1714 +#include <linux/interrupt.h>
1715 +
1716 +//#include <linux/hdlc.h> XXX We aren't HDLC
1717 +
1718 +#define DEBUG_QUEUES 0
1719 +#define DEBUG_DESC 0
1720 +#define DEBUG_RX 0
1721 +#define DEBUG_TX 0
1722 +#define DEBUG_PKT_BYTES 0
1723 +#define DEBUG_CLOSE 0
1724 +#define DEBUG_FRAMER 0
1725 +
1726 +#define DRV_NAME "ixp4xx_hss"
1727 +
1728 +#define PKT_EXTRA_FLAGS 0 /* orig 1 */
1729 +#define TX_FRAME_SYNC_OFFSET 0 /* channelized */
1730 +#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
1731 +#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
1732 +
1733 +#define RX_DESCS 512 /* also length of all RX queues */
1734 +#define TX_DESCS 512 /* also length of all TX queues */
1735 +
1736 +//#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
1737 +#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
1738 +#define MAX_CLOSE_WAIT 1000 /* microseconds */
1739 +#define HSS_COUNT 2
1740 +#define MIN_FRAME_SIZE 16 /* bits */
1741 +#define MAX_FRAME_SIZE 257 /* 256 bits + framing bit */
1742 +#define MAX_CHANNELS (MAX_FRAME_SIZE / 8)
1743 +#define MAX_CHAN_DEVICES 32
1744 +#define CHANNEL_HDLC 0xFE
1745 +#define CHANNEL_UNUSED 0xFF
1746 +
1747 +#define NAPI_WEIGHT 16
1748 +#define CHAN_RX_TRIGGER 16 /* 8 RX frames = 1 ms @ E1 */
1749 +#define CHAN_RX_FRAMES 128
1750 +#define CHAN_RX_TRUNKS 1
1751 +#define MAX_CHAN_RX_BAD_SYNC (CHAN_RX_TRIGGER / 2 /* pairs */ - 3)
1752 +
1753 +#define CHAN_TX_LIST_FRAMES CHAN_RX_TRIGGER /* bytes/channel per list, 16 - 48 */
1754 +#define CHAN_TX_LISTS 8
1755 +#define CHAN_TX_TRUNKS CHAN_RX_TRUNKS
1756 +#define CHAN_TX_FRAMES (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS)
1757 +
1758 +#define CHAN_QUEUE_LEN 32 /* minimum possible */
1759 +
1760 +#define chan_rx_buf_len(port) (port->frame_size / 8 * CHAN_RX_FRAMES * CHAN_RX_TRUNKS)
1761 +#define chan_tx_buf_len(port) (port->frame_size / 8 * CHAN_TX_FRAMES * CHAN_TX_TRUNKS)
1762 +
1763 +/* Queue IDs */
1764 +#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
1765 +#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
1766 +#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
1767 +#define HSS0_PKT_TX1_QUEUE 15
1768 +#define HSS0_PKT_TX2_QUEUE 16
1769 +#define HSS0_PKT_TX3_QUEUE 17
1770 +#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
1771 +#define HSS0_PKT_RXFREE1_QUEUE 19
1772 +#define HSS0_PKT_RXFREE2_QUEUE 20
1773 +#define HSS0_PKT_RXFREE3_QUEUE 21
1774 +#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
1775 +
1776 +#define HSS1_CHL_RXTRIG_QUEUE 10
1777 +#define HSS1_PKT_RX_QUEUE 0
1778 +#define HSS1_PKT_TX0_QUEUE 5
1779 +#define HSS1_PKT_TX1_QUEUE 6
1780 +#define HSS1_PKT_TX2_QUEUE 7
1781 +#define HSS1_PKT_TX3_QUEUE 8
1782 +#define HSS1_PKT_RXFREE0_QUEUE 1
1783 +#define HSS1_PKT_RXFREE1_QUEUE 2
1784 +#define HSS1_PKT_RXFREE2_QUEUE 3
1785 +#define HSS1_PKT_RXFREE3_QUEUE 4
1786 +#define HSS1_PKT_TXDONE_QUEUE 9
1787 +
1788 +#define NPE_PKT_MODE_HDLC 0
1789 +#define NPE_PKT_MODE_RAW 1
1790 +#define NPE_PKT_MODE_56KMODE 2
1791 +#define NPE_PKT_MODE_56KENDIAN_MSB 4
1792 +
1793 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
1794 +#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
1795 +#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
1796 +#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
1797 +
1798 +
1799 +/* hss_config, PCRs */
1800 +/* Frame sync sampling, default = active low */
1801 +#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
1802 +#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
1803 +#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
1804 +
1805 +/* Frame sync pin: input (default) or output generated off a given clk edge */
1806 +#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
1807 +#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
1808 +
1809 +/* Frame and data clock sampling on edge, default = falling */
1810 +#define PCR_FCLK_EDGE_RISING 0x08000000
1811 +#define PCR_DCLK_EDGE_RISING 0x04000000
1812 +
1813 +/* Clock direction, default = input */
1814 +#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
1815 +
1816 +/* Generate/Receive frame pulses, default = enabled */
1817 +#define PCR_FRM_PULSE_DISABLED 0x01000000
1818 +
1819 + /* Data rate is full (default) or half the configured clk speed */
1820 +#define PCR_HALF_CLK_RATE 0x00200000
1821 +
1822 +/* Invert data between NPE and HSS FIFOs? (default = no) */
1823 +#define PCR_DATA_POLARITY_INVERT 0x00100000
1824 +
1825 +/* TX/RX endianness, default = LSB */
1826 +#define PCR_MSB_ENDIAN 0x00080000
1827 +
1828 +/* Normal (default) / open drain mode (TX only) */
1829 +#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
1830 +
1831 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
1832 +#define PCR_SOF_NO_FBIT 0x00020000
1833 +
1834 +/* Drive data pins? */
1835 +#define PCR_TX_DATA_ENABLE 0x00010000
1836 +
1837 +/* Voice 56k type: drive the data pins low (default), high, high Z */
1838 +#define PCR_TX_V56K_HIGH 0x00002000
1839 +#define PCR_TX_V56K_HIGH_IMP 0x00004000
1840 +
1841 +/* Unassigned type: drive the data pins low (default), high, high Z */
1842 +#define PCR_TX_UNASS_HIGH 0x00000800
1843 +#define PCR_TX_UNASS_HIGH_IMP 0x00001000
1844 +
1845 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
1846 +#define PCR_TX_FB_HIGH_IMP 0x00000400
1847 +
1848 +/* 56k data endiannes - which bit unused: high (default) or low */
1849 +#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
1850 +
1851 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
1852 +#define PCR_TX_56KS_56K_DATA 0x00000100
1853 +
1854 +/* hss_config, cCR */
1855 +/* Number of packetized clients, default = 1 */
1856 +#define CCR_NPE_HFIFO_2_HDLC 0x04000000
1857 +#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
1858 +
1859 +/* default = no loopback */
1860 +#define CCR_LOOPBACK 0x02000000
1861 +
1862 +/* HSS number, default = 0 (first) */
1863 +#define CCR_SECOND_HSS 0x01000000
1864 +
1865 +
1866 +/* hss_config, clkCR: main:10, num:10, denom:12 */
1867 +#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
1868 +
1869 +#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
1870 +#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
1871 +#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
1872 +#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
1873 +#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
1874 +#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
1875 +
1876 +#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
1877 +#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
1878 +#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
1879 +#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
1880 +#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
1881 +#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
1882 +
1883 +
1884 +/* hss_config, LUT entries */
1885 +#define TDMMAP_UNASSIGNED 0
1886 +#define TDMMAP_HDLC 1 /* HDLC - packetized */
1887 +#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
1888 +#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
1889 +
1890 +/* offsets into HSS config */
1891 +#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
1892 +#define HSS_CONFIG_RX_PCR 0x04
1893 +#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
1894 +#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
1895 +#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
1896 +#define HSS_CONFIG_RX_FCR 0x14
1897 +#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
1898 +#define HSS_CONFIG_RX_LUT 0x38
1899 +
1900 +
1901 +/* NPE command codes */
1902 +/* writes the ConfigWord value to the location specified by offset */
1903 +#define PORT_CONFIG_WRITE 0x40
1904 +
1905 +/* triggers the NPE to load the contents of the configuration table */
1906 +#define PORT_CONFIG_LOAD 0x41
1907 +
1908 +/* triggers the NPE to return an HssErrorReadResponse message */
1909 +#define PORT_ERROR_READ 0x42
1910 +
1911 +/* reset NPE internal status and enable the HssChannelized operation */
1912 +#define CHAN_FLOW_ENABLE 0x43
1913 +#define CHAN_FLOW_DISABLE 0x44
1914 +#define CHAN_IDLE_PATTERN_WRITE 0x45
1915 +#define CHAN_NUM_CHANS_WRITE 0x46
1916 +#define CHAN_RX_BUF_ADDR_WRITE 0x47
1917 +#define CHAN_RX_BUF_CFG_WRITE 0x48
1918 +#define CHAN_TX_BLK_CFG_WRITE 0x49
1919 +#define CHAN_TX_BUF_ADDR_WRITE 0x4A
1920 +#define CHAN_TX_BUF_SIZE_WRITE 0x4B
1921 +#define CHAN_TSLOTSWITCH_ENABLE 0x4C
1922 +#define CHAN_TSLOTSWITCH_DISABLE 0x4D
1923 +
1924 +/* downloads the gainWord value for a timeslot switching channel associated
1925 + with bypassNum */
1926 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
1927 +
1928 +/* triggers the NPE to reset internal status and enable the HssPacketized
1929 + operation for the flow specified by pPipe */
1930 +#define PKT_PIPE_FLOW_ENABLE 0x50
1931 +#define PKT_PIPE_FLOW_DISABLE 0x51
1932 +#define PKT_NUM_PIPES_WRITE 0x52
1933 +#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
1934 +#define PKT_PIPE_HDLC_CFG_WRITE 0x54
1935 +#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
1936 +#define PKT_PIPE_RX_SIZE_WRITE 0x56
1937 +#define PKT_PIPE_MODE_WRITE 0x57
1938 +
1939 +/* HDLC packet status values - desc->status */
1940 +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
1941 +#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
1942 +#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
1943 +#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
1944 + this packet (if buf_len < pkt_len) */
1945 +#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
1946 +#define ERR_HDLC_ABORT 6 /* abort sequence received */
1947 +#define ERR_DISCONNECTING 7 /* disconnect is in progress */
1948 +
1949 +#define CLOCK_EXT 0
1950 +#define CLOCK_INT 1
1951 +
1952 +enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704};
1953 +enum rx_tx_bit {
1954 + TX_BIT = 0,
1955 + RX_BIT = 1
1956 +};
1957 +enum chan_bit {
1958 + CHAN_0 = (1 << 0),
1959 + CHAN_1 = (1 << 1),
1960 + CHAN_2 = (1 << 2),
1961 + CHAN_3 = (1 << 3),
1962 + CHAN_4 = (1 << 4),
1963 + CHAN_5 = (1 << 5),
1964 + CHAN_6 = (1 << 6),
1965 + CHAN_7 = (1 << 7),
1966 + CHAN_8 = (1 << 8),
1967 + CHAN_9 = (1 << 9),
1968 + CHAN_10 = (1 << 10),
1969 + CHAN_11 = (1 << 11),
1970 + CHAN_12 = (1 << 12),
1971 + CHAN_13 = (1 << 13),
1972 + CHAN_14 = (1 << 14),
1973 + CHAN_15 = (1 << 15)
1974 +};
1975 +
1976 +enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST };
1977 +
1978 +#ifdef __ARMEB__
1979 +typedef struct sk_buff buffer_t;
1980 +#define free_buffer dev_kfree_skb
1981 +#define free_buffer_irq dev_kfree_skb_irq
1982 +#else
1983 +typedef void buffer_t;
1984 +#define free_buffer kfree
1985 +#define free_buffer_irq kfree
1986 +#endif
1987 +
1988 +struct hss_device {
1989 + struct port *port;
1990 + unsigned int open_count, excl_open;
1991 + unsigned long tx_loc, rx_loc; /* bytes */
1992 + unsigned long tx_frame, rx_frame; /* Frames */
1993 + u8 id, chan_count;
1994 + u8 log_channels[MAX_CHANNELS];
1995 +
1996 + u8 *rx_buf;
1997 + u8 *tx_buf;
1998 +
1999 + size_t rx_buffer_size;
2000 + size_t rx_period_size;
2001 + size_t tx_buffer_size;
2002 + size_t tx_period_size;
2003 +
2004 + void (*rx_callback)(void *data);
2005 + void *rx_data;
2006 + void (*tx_callback)(void *data);
2007 + void *tx_data;
2008 + void *private_data;
2009 +};
2010 +
2011 +extern struct hss_device *hss_handle[32];
2012 +extern struct port *hss_port[2];
2013 +
2014 +struct port {
2015 + unsigned char init;
2016 +
2017 + struct device *dev;
2018 +
2019 + struct tasklet_struct task;
2020 + unsigned int id;
2021 + unsigned long chan_rx_bitmap;
2022 + unsigned long chan_tx_bitmap;
2023 + unsigned char chan_open;
2024 +
2025 + /* the following fields must be protected by npe_lock */
2026 + enum mode mode;
2027 + unsigned int clock_type, clock_rate, loopback;
2028 + unsigned int frame_size, frame_sync_offset;
2029 + unsigned int next_rx_frame;
2030 +
2031 + struct hss_device *chan_devices[MAX_CHAN_DEVICES];
2032 + u32 chan_tx_buf_phys, chan_rx_buf_phys;
2033 + u32 chan_tx_pointers_phys;
2034 + u32 *chan_tx_pointers;
2035 + u8 *chan_rx_buf;
2036 + u8 *chan_tx_buf;
2037 + u8 *tx_lists[CHAN_TX_LISTS][8];
2038 + u8 *rx_frames[8][CHAN_TX_LISTS];
2039 + unsigned int chan_open_count, hdlc_open;
2040 + unsigned int chan_started, initialized, just_set_offset;
2041 + unsigned int chan_last_rx, chan_last_tx;
2042 +
2043 + /* assigned channels, may be invalid with given frame length or mode */
2044 + u8 channels[MAX_CHANNELS];
2045 + int msg_count;
2046 +};
2047 +
2048 +/* NPE message structure */
2049 +struct msg {
2050 +#ifdef __ARMEB__
2051 + u8 cmd, unused, hss_port, index;
2052 + union {
2053 + struct { u8 data8a, data8b, data8c, data8d; };
2054 + struct { u16 data16a, data16b; };
2055 + struct { u32 data32; };
2056 + };
2057 +#else
2058 + u8 index, hss_port, unused, cmd;
2059 + union {
2060 + struct { u8 data8d, data8c, data8b, data8a; };
2061 + struct { u16 data16b, data16a; };
2062 + struct { u32 data32; };
2063 + };
2064 +#endif
2065 +};
2066 +
2067 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
2068 + (n) * sizeof(struct desc))
2069 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
2070 +
2071 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
2072 + ((n) + RX_DESCS) * sizeof(struct desc))
2073 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
2074 +
2075 +int hss_prepare_chan(struct port *port);
2076 +void hss_chan_stop(struct port *port);
2077 +
2078 +struct hss_device *hss_init(int id, int channel);
2079 +int hss_chan_open(struct hss_device *hdev);
2080 +int hss_chan_close(struct hss_device *hdev);
2081 +
2082 +int hss_set_tx_callback(struct hss_device *hdev, void (*tx_callback)(void *), void *tx_data);
2083 +int hss_set_rx_callback(struct hss_device *hdev, void (*rx_callback)(void *), void *rx_data);
2084 +int hss_tx_start(struct hss_device *hdev);
2085 +int hss_tx_stop(struct hss_device *hdev);
2086 +int hss_rx_start(struct hss_device *hdev);
2087 +int hss_rx_stop(struct hss_device *hdev);
2088 +
2089 +int hss_config_rx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size);
2090 +int hss_config_tx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size);
2091 +unsigned long hss_curr_offset_rx(struct hss_device *hdev);
2092 +unsigned long hss_curr_offset_tx(struct hss_device *hdev);
2093 +