OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 4910cfd150342ec7b038892262923c725a9c4001 Mon Sep 17 00:00:00 2001 |
2 | From: Sham Muthayyan <smuthayy@codeaurora.org> |
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3 | Date: Wed, 7 Sep 2016 16:44:28 +0530 |
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4 | Subject: PCI: qcom: Force GEN1 support |
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5 | |||
6 | Change-Id: Ica54ddb737d7b851469deab1745f54bf431bd3f0 |
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7 | Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> |
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8 | --- |
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9 | drivers/pci/host/pcie-qcom.c | 13 +++++++++++++ |
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10 | 1 file changed, 13 insertions(+) |
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11 | |||
12 | --- a/drivers/pci/dwc/pcie-qcom.c |
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13 | +++ b/drivers/pci/dwc/pcie-qcom.c |
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14 | @@ -129,6 +129,8 @@ |
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15 | #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 |
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16 | #define SLV_ADDR_SPACE_SZ 0x10000000 |
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17 | |||
18 | +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 |
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19 | + |
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20 | struct qcom_pcie_resources_2_1_0 { |
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21 | struct clk *iface_clk; |
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22 | struct clk *core_clk; |
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23 | @@ -218,6 +220,7 @@ struct qcom_pcie { |
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24 | struct phy *phy; |
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25 | struct gpio_desc *reset; |
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26 | struct qcom_pcie_ops *ops; |
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27 | + uint32_t force_gen1; |
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28 | }; |
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29 | |||
30 | #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) |
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31 | @@ -532,6 +535,11 @@ static int qcom_pcie_init_2_1_0(struct q |
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32 | |||
33 | /* wait for clock acquisition */ |
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34 | usleep_range(1000, 1500); |
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35 | + if (pcie->force_gen1) { |
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36 | + writel_relaxed((readl_relaxed( |
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37 | + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1), |
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38 | + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); |
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39 | + } |
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40 | |||
41 | |||
42 | /* Set the Max TLP size to 2K, instead of using default of 4K */ |
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43 | @@ -1382,6 +1390,8 @@ static int qcom_pcie_probe(struct platfo |
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44 | struct dw_pcie *pci; |
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45 | struct qcom_pcie *pcie; |
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46 | int ret; |
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47 | + uint32_t force_gen1 = 0; |
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48 | + struct device_node *np = pdev->dev.of_node; |
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49 | |||
50 | pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); |
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51 | if (!pcie) |
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52 | @@ -1403,6 +1413,9 @@ static int qcom_pcie_probe(struct platfo |
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53 | if (IS_ERR(pcie->reset)) |
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54 | return PTR_ERR(pcie->reset); |
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55 | |||
56 | + of_property_read_u32(np, "force_gen1", &force_gen1); |
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57 | + pcie->force_gen1 = force_gen1; |
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58 | + |
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59 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); |
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60 | pcie->parf = devm_ioremap_resource(dev, res); |
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61 | if (IS_ERR(pcie->parf)) |