OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From d27c303e828d7e42f339a459d2abfe30c51698e9 Mon Sep 17 00:00:00 2001 |
2 | From: Sham Muthayyan <smuthayy@codeaurora.org> |
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3 | Date: Tue, 26 Jul 2016 12:28:31 +0530 |
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4 | Subject: PCI: qcom: Programming the PCIE iATU for IPQ806x |
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5 | |||
6 | Resolved PCIE EP detection errors caused due to missing iATU programming. |
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7 | |||
8 | Change-Id: Ie95c0f8cb940abc0192a8a3c4e825ddba54b72fe |
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9 | Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> |
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10 | --- |
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11 | drivers/pci/host/pcie-qcom.c | 77 ++++++++++++++++++++++++++++++++++++++++++++ |
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12 | 1 file changed, 77 insertions(+) |
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13 | |||
14 | --- a/drivers/pci/dwc/pcie-qcom.c |
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15 | +++ b/drivers/pci/dwc/pcie-qcom.c |
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16 | @@ -83,6 +83,30 @@ |
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17 | #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14) |
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18 | #define PCIE_CAP_LINK1_VAL 0x2FD7F |
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19 | |||
20 | +#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) |
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21 | + |
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22 | +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818 |
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23 | +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c |
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24 | + |
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25 | +#define PCIE20_PLR_IATU_VIEWPORT 0x900 |
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26 | +#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31) |
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27 | +#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0) |
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28 | + |
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29 | +#define PCIE20_PLR_IATU_CTRL1 0x904 |
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30 | +#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0) |
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31 | +#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0) |
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32 | + |
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33 | +#define PCIE20_PLR_IATU_CTRL2 0x908 |
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34 | +#define PCIE20_PLR_IATU_ENABLE BIT(31) |
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35 | + |
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36 | +#define PCIE20_PLR_IATU_LBAR 0x90C |
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37 | +#define PCIE20_PLR_IATU_UBAR 0x910 |
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38 | +#define PCIE20_PLR_IATU_LAR 0x914 |
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39 | +#define PCIE20_PLR_IATU_LTAR 0x918 |
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40 | +#define PCIE20_PLR_IATU_UTAR 0x91c |
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41 | + |
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42 | +#define MSM_PCIE_DEV_CFG_ADDR 0x01000000 |
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43 | + |
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44 | #define PCIE20_PARF_Q2A_FLUSH 0x1AC |
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45 | |||
46 | #define PCIE20_MISC_CONTROL_1_REG 0x8BC |
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47 | @@ -251,6 +275,57 @@ static void qcom_pcie_2_1_0_ltssm_enable |
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48 | writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL); |
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49 | } |
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50 | |||
51 | +static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev) |
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52 | +{ |
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53 | + struct pcie_port *pp = &pcie->pci->pp; |
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54 | + |
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55 | + /* |
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56 | + * program and enable address translation region 0 (device config |
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57 | + * address space); region type config; |
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58 | + * axi config address range to device config address range |
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59 | + */ |
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60 | + writel(PCIE20_PLR_IATU_REGION_OUTBOUND | |
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61 | + PCIE20_PLR_IATU_REGION_INDEX(0), |
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62 | + pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT); |
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63 | + |
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64 | + writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1); |
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65 | + writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2); |
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66 | + writel(pp->cfg0_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR); |
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67 | + writel((pp->cfg0_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR); |
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68 | + writel((pp->cfg0_base + pp->cfg0_size - 1), |
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69 | + pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR); |
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70 | + writel(busdev, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR); |
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71 | + writel(0, pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR); |
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72 | +} |
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73 | + |
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74 | +static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie) |
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75 | +{ |
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76 | + struct pcie_port *pp = &pcie->pci->pp; |
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77 | + |
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78 | + /* |
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79 | + * program and enable address translation region 2 (device resource |
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80 | + * address space); region type memory; |
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81 | + * axi device bar address range to device bar address range |
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82 | + */ |
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83 | + writel(PCIE20_PLR_IATU_REGION_OUTBOUND | |
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84 | + PCIE20_PLR_IATU_REGION_INDEX(2), |
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85 | + pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT); |
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86 | + |
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87 | + writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1); |
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88 | + writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2); |
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89 | + writel(pp->mem_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR); |
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90 | + writel((pp->mem_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR); |
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91 | + writel(pp->mem_base + pp->mem_size - 1, |
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92 | + pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR); |
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93 | + writel(pp->mem_bus_addr, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR); |
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94 | + writel(upper_32_bits(pp->mem_bus_addr), |
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95 | + pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR); |
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96 | + |
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97 | + /* 256B PCIE buffer setting */ |
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98 | + writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); |
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99 | + writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); |
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100 | +} |
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101 | + |
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102 | static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) |
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103 | { |
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104 | struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; |
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105 | @@ -465,6 +540,9 @@ static int qcom_pcie_init_2_1_0(struct q |
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106 | writel(CFG_BRIDGE_SB_INIT, |
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107 | pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); |
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108 | |||
109 | + qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR); |
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110 | + qcom_pcie_prog_viewport_mem2_outbound(pcie); |
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111 | + |
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112 | return 0; |
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113 | |||
114 | err_deassert_ahb: |