OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From eddd13215d0f2b549ebc5f0e8796d5b1231f90a0 Mon Sep 17 00:00:00 2001 |
2 | From: Sham Muthayyan <smuthayy@codeaurora.org> |
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3 | Date: Tue, 19 Jul 2016 19:58:22 +0530 |
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4 | Subject: PCI: qcom: Fixed IPQ806x PCIE init changes |
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5 | |||
6 | Change-Id: Ic319b1aec27a47809284759f8fcb6a8815b7cf7e |
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7 | Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> |
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8 | --- |
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9 | drivers/pci/host/pcie-qcom.c | 62 +++++++++++++++++++++++++++++++++++++------- |
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10 | 1 file changed, 53 insertions(+), 9 deletions(-) |
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11 | |||
12 | --- a/drivers/pci/dwc/pcie-qcom.c |
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13 | +++ b/drivers/pci/dwc/pcie-qcom.c |
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14 | @@ -52,7 +52,13 @@ |
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15 | #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 |
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16 | |||
17 | #define PCIE20_PARF_PHY_CTRL 0x40 |
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18 | +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16) |
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19 | +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16) |
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20 | + |
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21 | #define PCIE20_PARF_PHY_REFCLK 0x4C |
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22 | +#define REF_SSP_EN BIT(16) |
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23 | +#define REF_USE_PAD BIT(12) |
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24 | + |
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25 | #define PCIE20_PARF_DBI_BASE_ADDR 0x168 |
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26 | #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C |
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27 | #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 |
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28 | @@ -83,6 +89,18 @@ |
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29 | #define DBI_RO_WR_EN 1 |
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30 | |||
31 | #define PERST_DELAY_US 1000 |
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32 | +/* PARF registers */ |
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33 | +#define PCIE20_PARF_PCS_DEEMPH 0x34 |
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34 | +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16) |
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35 | +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8) |
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36 | +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0) |
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37 | + |
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38 | +#define PCIE20_PARF_PCS_SWING 0x38 |
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39 | +#define PCS_SWING_TX_SWING_FULL(x) (x << 8) |
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40 | +#define PCS_SWING_TX_SWING_LOW(x) (x << 0) |
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41 | + |
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42 | +#define PCIE20_PARF_CONFIG_BITS 0x50 |
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43 | +#define PHY_RX0_EQ(x) (x << 24) |
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44 | |||
45 | #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 |
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46 | #define SLV_ADDR_SPACE_SZ 0x10000000 |
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47 | @@ -102,6 +120,7 @@ struct qcom_pcie_resources_2_1_0 { |
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48 | struct regulator *vdda; |
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49 | struct regulator *vdda_phy; |
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50 | struct regulator *vdda_refclk; |
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51 | + uint8_t phy_tx0_term_offset; |
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52 | }; |
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53 | |||
54 | struct qcom_pcie_resources_1_0_0 { |
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55 | @@ -179,6 +198,16 @@ struct qcom_pcie { |
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56 | |||
57 | #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) |
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58 | |||
59 | +static inline void |
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60 | +writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask) |
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61 | +{ |
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62 | + u32 val = readl(addr); |
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63 | + |
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64 | + val &= ~clear_mask; |
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65 | + val |= set_mask; |
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66 | + writel(val, addr); |
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67 | +} |
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68 | + |
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69 | static void qcom_ep_reset_assert(struct qcom_pcie *pcie) |
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70 | { |
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71 | gpiod_set_value_cansleep(pcie->reset, 1); |
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72 | @@ -280,6 +309,10 @@ static int qcom_pcie_get_resources_2_1_0 |
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73 | if (IS_ERR(res->ext_reset)) |
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74 | return PTR_ERR(res->ext_reset); |
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75 | |||
76 | + if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset", |
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77 | + &res->phy_tx0_term_offset)) |
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78 | + res->phy_tx0_term_offset = 0; |
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79 | + |
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80 | res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); |
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81 | return PTR_ERR_OR_ZERO(res->phy_reset); |
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82 | } |
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83 | @@ -309,7 +342,6 @@ static int qcom_pcie_init_2_1_0(struct q |
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84 | struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; |
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85 | struct dw_pcie *pci = pcie->pci; |
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86 | struct device *dev = pci->dev; |
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87 | - u32 val; |
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88 | int ret; |
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89 | |||
90 | ret = reset_control_assert(res->ahb_reset); |
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91 | @@ -378,15 +410,26 @@ static int qcom_pcie_init_2_1_0(struct q |
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92 | goto err_deassert_ahb; |
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93 | } |
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94 | |||
95 | - /* enable PCIe clocks and resets */ |
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96 | - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); |
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97 | - val &= ~BIT(0); |
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98 | - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); |
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99 | - |
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100 | - /* enable external reference clock */ |
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101 | - val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); |
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102 | - val |= BIT(16); |
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103 | - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); |
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104 | + writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); |
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105 | + |
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106 | + /* Set Tx termination offset */ |
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107 | + writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, |
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108 | + PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, |
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109 | + PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset)); |
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110 | + |
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111 | + /* PARF programming */ |
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112 | + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) | |
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113 | + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) | |
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114 | + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22), |
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115 | + pcie->parf + PCIE20_PARF_PCS_DEEMPH); |
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116 | + writel(PCS_SWING_TX_SWING_FULL(0x78) | |
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117 | + PCS_SWING_TX_SWING_LOW(0x78), |
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118 | + pcie->parf + PCIE20_PARF_PCS_SWING); |
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119 | + writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS); |
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120 | + |
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121 | + /* Enable reference clock */ |
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122 | + writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, |
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123 | + REF_USE_PAD, REF_SSP_EN); |
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124 | |||
125 | ret = reset_control_deassert(res->phy_reset); |
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126 | if (ret) { |