OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 86655aa14304ca88a8ce8847276147dbc1a83238 Mon Sep 17 00:00:00 2001 |
2 | From: Sham Muthayyan <smuthayy@codeaurora.org> |
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3 | Date: Tue, 19 Jul 2016 18:44:49 +0530 |
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4 | Subject: PCI: qcom: Fixed IPQ806x specific clocks |
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5 | |||
6 | Change-Id: I488e1bc707d6a22b37a338f41935e3922009ba5e |
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7 | Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> |
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8 | --- |
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9 | drivers/pci/host/pcie-qcom.c | 38 +++++++++++++++++++++++++++++++++----- |
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10 | 1 file changed, 33 insertions(+), 5 deletions(-) |
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11 | |||
12 | --- a/drivers/pci/dwc/pcie-qcom.c |
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13 | +++ b/drivers/pci/dwc/pcie-qcom.c |
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14 | @@ -91,6 +91,8 @@ struct qcom_pcie_resources_2_1_0 { |
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15 | struct clk *iface_clk; |
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16 | struct clk *core_clk; |
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17 | struct clk *phy_clk; |
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18 | + struct clk *aux_clk; |
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19 | + struct clk *ref_clk; |
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20 | struct reset_control *pci_reset; |
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21 | struct reset_control *axi_reset; |
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22 | struct reset_control *ahb_reset; |
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23 | @@ -249,6 +251,14 @@ static int qcom_pcie_get_resources_2_1_0 |
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24 | if (IS_ERR(res->phy_clk)) |
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25 | return PTR_ERR(res->phy_clk); |
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26 | |||
27 | + res->aux_clk = devm_clk_get(dev, "aux"); |
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28 | + if (IS_ERR(res->aux_clk)) |
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29 | + return PTR_ERR(res->aux_clk); |
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30 | + |
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31 | + res->ref_clk = devm_clk_get(dev, "ref"); |
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32 | + if (IS_ERR(res->ref_clk)) |
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33 | + return PTR_ERR(res->ref_clk); |
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34 | + |
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35 | res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); |
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36 | if (IS_ERR(res->pci_reset)) |
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37 | return PTR_ERR(res->pci_reset); |
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38 | @@ -281,6 +291,8 @@ static void qcom_pcie_deinit_2_1_0(struc |
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39 | clk_disable_unprepare(res->iface_clk); |
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40 | clk_disable_unprepare(res->core_clk); |
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41 | clk_disable_unprepare(res->phy_clk); |
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42 | + clk_disable_unprepare(res->aux_clk); |
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43 | + clk_disable_unprepare(res->ref_clk); |
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44 | regulator_disable(res->vdda); |
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45 | regulator_disable(res->vdda_phy); |
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46 | regulator_disable(res->vdda_refclk); |
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47 | @@ -324,16 +336,28 @@ static int qcom_pcie_init_2_1_0(struct q |
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48 | goto err_assert_ahb; |
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49 | } |
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50 | |||
51 | + ret = clk_prepare_enable(res->core_clk); |
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52 | + if (ret) { |
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53 | + dev_err(dev, "cannot prepare/enable core clock\n"); |
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54 | + goto err_clk_core; |
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55 | + } |
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56 | + |
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57 | ret = clk_prepare_enable(res->phy_clk); |
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58 | if (ret) { |
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59 | dev_err(dev, "cannot prepare/enable phy clock\n"); |
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60 | goto err_clk_phy; |
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61 | } |
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62 | |||
63 | - ret = clk_prepare_enable(res->core_clk); |
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64 | + ret = clk_prepare_enable(res->aux_clk); |
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65 | if (ret) { |
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66 | - dev_err(dev, "cannot prepare/enable core clock\n"); |
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67 | - goto err_clk_core; |
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68 | + dev_err(dev, "cannot prepare/enable aux clock\n"); |
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69 | + goto err_clk_aux; |
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70 | + } |
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71 | + |
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72 | + ret = clk_prepare_enable(res->ref_clk); |
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73 | + if (ret) { |
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74 | + dev_err(dev, "cannot prepare/enable ref clock\n"); |
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75 | + goto err_clk_ref; |
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76 | } |
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77 | |||
78 | ret = reset_control_deassert(res->ahb_reset); |
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79 | @@ -389,10 +413,14 @@ static int qcom_pcie_init_2_1_0(struct q |
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80 | return 0; |
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81 | |||
82 | err_deassert_ahb: |
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83 | - clk_disable_unprepare(res->core_clk); |
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84 | -err_clk_core: |
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85 | + clk_disable_unprepare(res->ref_clk); |
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86 | +err_clk_ref: |
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87 | + clk_disable_unprepare(res->aux_clk); |
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88 | +err_clk_aux: |
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89 | clk_disable_unprepare(res->phy_clk); |
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90 | err_clk_phy: |
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91 | + clk_disable_unprepare(res->core_clk); |
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92 | +err_clk_core: |
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93 | clk_disable_unprepare(res->iface_clk); |
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94 | err_assert_ahb: |
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95 | regulator_disable(res->vdda_phy); |