OpenWrt – Blame information for rev 4
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4 | office | 1 | From patchwork Fri Dec 8 09:42:22 2017 |
2 | Content-Type: text/plain; charset="utf-8" |
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3 | MIME-Version: 1.0 |
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4 | Content-Transfer-Encoding: 7bit |
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5 | Subject: [v4,04/12] clk: qcom: Add HFPLL driver |
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6 | From: Sricharan R <sricharan@codeaurora.org> |
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7 | X-Patchwork-Id: 10102079 |
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8 | Message-Id: <1512726150-7204-5-git-send-email-sricharan@codeaurora.org> |
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9 | To: mturquette@baylibre.com, sboyd@codeaurora.org, |
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10 | devicetree@vger.kernel.org, linux-pm@vger.kernel.org, |
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11 | linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, |
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12 | viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org |
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13 | Cc: sricharan@codeaurora.org |
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14 | Date: Fri, 8 Dec 2017 15:12:22 +0530 |
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15 | |||
16 | From: Stephen Boyd <sboyd@codeaurora.org> |
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17 | |||
18 | On some devices (MSM8974 for example), the HFPLLs are |
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19 | instantiated within the Krait processor subsystem as separate |
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20 | register regions. Add a driver for these PLLs so that we can |
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21 | provide HFPLL clocks for use by the system. |
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22 | |||
23 | Cc: <devicetree@vger.kernel.org> |
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24 | Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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25 | --- |
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26 | .../devicetree/bindings/clock/qcom,hfpll.txt | 40 ++++++++ |
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27 | drivers/clk/qcom/Kconfig | 8 ++ |
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28 | drivers/clk/qcom/Makefile | 1 + |
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29 | drivers/clk/qcom/hfpll.c | 106 +++++++++++++++++++++ |
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30 | 4 files changed, 155 insertions(+) |
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31 | create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt |
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32 | create mode 100644 drivers/clk/qcom/hfpll.c |
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33 | |||
34 | --- /dev/null |
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35 | +++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt |
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36 | @@ -0,0 +1,40 @@ |
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37 | +High-Frequency PLL (HFPLL) |
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38 | + |
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39 | +PROPERTIES |
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40 | + |
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41 | +- compatible: |
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42 | + Usage: required |
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43 | + Value type: <string> |
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44 | + Definition: must be "qcom,hfpll" |
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45 | + |
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46 | +- reg: |
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47 | + Usage: required |
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48 | + Value type: <prop-encoded-array> |
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49 | + Definition: address and size of HPLL registers. An optional second |
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50 | + element specifies the address and size of the alias |
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51 | + register region. |
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52 | + |
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53 | +- clock-output-names: |
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54 | + Usage: required |
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55 | + Value type: <string> |
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56 | + Definition: Name of the PLL. Typically hfpllX where X is a CPU number |
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57 | + starting at 0. Otherwise hfpll_Y where Y is more specific |
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58 | + such as "l2". |
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59 | + |
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60 | +Example: |
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61 | + |
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62 | +1) An HFPLL for the L2 cache. |
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63 | + |
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64 | + clock-controller@f9016000 { |
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65 | + compatible = "qcom,hfpll"; |
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66 | + reg = <0xf9016000 0x30>; |
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67 | + clock-output-names = "hfpll_l2"; |
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68 | + }; |
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69 | + |
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70 | +2) An HFPLL for CPU0. This HFPLL has the alias register region. |
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71 | + |
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72 | + clock-controller@f908a000 { |
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73 | + compatible = "qcom,hfpll"; |
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74 | + reg = <0xf908a000 0x30>, <0xf900a000 0x30>; |
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75 | + clock-output-names = "hfpll0"; |
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76 | + }; |
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77 | --- a/drivers/clk/qcom/Kconfig |
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78 | +++ b/drivers/clk/qcom/Kconfig |
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79 | @@ -196,3 +196,11 @@ config MSM_MMCC_8996 |
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80 | Support for the multimedia clock controller on msm8996 devices. |
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81 | Say Y if you want to support multimedia devices such as display, |
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82 | graphics, video encode/decode, camera, etc. |
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83 | + |
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84 | +config QCOM_HFPLL |
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85 | + tristate "High-Frequency PLL (HFPLL) Clock Controller" |
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86 | + depends on COMMON_CLK_QCOM |
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87 | + help |
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88 | + Support for the high-frequency PLLs present on Qualcomm devices. |
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89 | + Say Y if you want to support CPU frequency scaling on devices |
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90 | + such as MSM8974, APQ8084, etc. |
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91 | --- a/drivers/clk/qcom/Makefile |
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92 | +++ b/drivers/clk/qcom/Makefile |
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93 | @@ -35,3 +35,4 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8 |
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94 | obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o |
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95 | obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o |
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96 | obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o |
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97 | +obj-$(CONFIG_QCOM_HFPLL) += hfpll.o |
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98 | --- /dev/null |
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99 | +++ b/drivers/clk/qcom/hfpll.c |
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100 | @@ -0,0 +1,106 @@ |
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101 | +/* |
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102 | + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
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103 | + * |
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104 | + * This program is free software; you can redistribute it and/or modify |
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105 | + * it under the terms of the GNU General Public License version 2 and |
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106 | + * only version 2 as published by the Free Software Foundation. |
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107 | + * |
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108 | + * This program is distributed in the hope that it will be useful, |
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109 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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110 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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111 | + * GNU General Public License for more details. |
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112 | + */ |
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113 | + |
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114 | +#include <linux/kernel.h> |
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115 | +#include <linux/init.h> |
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116 | +#include <linux/module.h> |
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117 | +#include <linux/platform_device.h> |
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118 | +#include <linux/of.h> |
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119 | +#include <linux/clk.h> |
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120 | +#include <linux/clk-provider.h> |
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121 | +#include <linux/regmap.h> |
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122 | + |
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123 | +#include "clk-regmap.h" |
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124 | +#include "clk-hfpll.h" |
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125 | + |
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126 | +static const struct hfpll_data hdata = { |
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127 | + .mode_reg = 0x00, |
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128 | + .l_reg = 0x04, |
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129 | + .m_reg = 0x08, |
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130 | + .n_reg = 0x0c, |
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131 | + .user_reg = 0x10, |
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132 | + .config_reg = 0x14, |
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133 | + .config_val = 0x430405d, |
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134 | + .status_reg = 0x1c, |
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135 | + .lock_bit = 16, |
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136 | + |
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137 | + .user_val = 0x8, |
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138 | + .user_vco_mask = 0x100000, |
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139 | + .low_vco_max_rate = 1248000000, |
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140 | + .min_rate = 537600000UL, |
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141 | + .max_rate = 2900000000UL, |
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142 | +}; |
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143 | + |
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144 | +static const struct of_device_id qcom_hfpll_match_table[] = { |
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145 | + { .compatible = "qcom,hfpll" }, |
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146 | + { } |
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147 | +}; |
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148 | +MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table); |
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149 | + |
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150 | +static const struct regmap_config hfpll_regmap_config = { |
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151 | + .reg_bits = 32, |
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152 | + .reg_stride = 4, |
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153 | + .val_bits = 32, |
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154 | + .max_register = 0x30, |
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155 | + .fast_io = true, |
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156 | +}; |
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157 | + |
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158 | +static int qcom_hfpll_probe(struct platform_device *pdev) |
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159 | +{ |
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160 | + struct resource *res; |
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161 | + struct device *dev = &pdev->dev; |
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162 | + void __iomem *base; |
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163 | + struct regmap *regmap; |
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164 | + struct clk_hfpll *h; |
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165 | + struct clk_init_data init = { |
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166 | + .parent_names = (const char *[]){ "xo" }, |
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167 | + .num_parents = 1, |
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168 | + .ops = &clk_ops_hfpll, |
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169 | + }; |
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170 | + |
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171 | + h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL); |
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172 | + if (!h) |
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173 | + return -ENOMEM; |
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174 | + |
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175 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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176 | + base = devm_ioremap_resource(dev, res); |
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177 | + if (IS_ERR(base)) |
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178 | + return PTR_ERR(base); |
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179 | + |
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180 | + regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config); |
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181 | + if (IS_ERR(regmap)) |
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182 | + return PTR_ERR(regmap); |
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183 | + |
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184 | + if (of_property_read_string_index(dev->of_node, "clock-output-names", |
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185 | + 0, &init.name)) |
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186 | + return -ENODEV; |
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187 | + |
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188 | + h->d = &hdata; |
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189 | + h->clkr.hw.init = &init; |
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190 | + spin_lock_init(&h->lock); |
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191 | + |
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192 | + return devm_clk_register_regmap(&pdev->dev, &h->clkr); |
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193 | +} |
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194 | + |
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195 | +static struct platform_driver qcom_hfpll_driver = { |
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196 | + .probe = qcom_hfpll_probe, |
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197 | + .driver = { |
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198 | + .name = "qcom-hfpll", |
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199 | + .of_match_table = qcom_hfpll_match_table, |
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200 | + }, |
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201 | +}; |
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202 | +module_platform_driver(qcom_hfpll_driver); |
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203 | + |
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204 | +MODULE_DESCRIPTION("QCOM HFPLL Clock Driver"); |
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205 | +MODULE_LICENSE("GPL v2"); |
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206 | +MODULE_ALIAS("platform:qcom-hfpll"); |