OpenWrt – Blame information for rev 4

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Rev Author Line No. Line
4 office 1 From b9004f4fd23e4c614d71c972f3a9311665480e29 Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Thu, 9 Mar 2017 08:19:18 +0100
4 Subject: [PATCH 32/69] phy: add qcom dwc3 phy
5  
6 Signed-off-by: Andy Gross <agross@codeaurora.org>
7 ---
8 drivers/phy/Kconfig | 12 +
9 drivers/phy/Makefile | 1 +
10 drivers/phy/phy-qcom-dwc3.c | 575 ++++++++++++++++++++++++++++++++++++++++++++
11 3 files changed, 588 insertions(+)
12 create mode 100644 drivers/phy/phy-qcom-dwc3.c
13  
14 --- a/drivers/phy/qualcomm/Kconfig
15 +++ b/drivers/phy/qualcomm/Kconfig
16 @@ -56,3 +56,15 @@ config PHY_QCOM_USB_HSIC
17 select GENERIC_PHY
18 help
19 Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
20 +
21 +config PHY_QCOM_DWC3
22 + tristate "QCOM DWC3 USB PHY support"
23 + depends on ARCH_QCOM
24 + depends on HAS_IOMEM
25 + depends on OF
26 + select GENERIC_PHY
27 + help
28 + This option enables support for the Synopsis PHYs present inside the
29 + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS
30 + PHY controllers.
31 +
32 --- a/drivers/phy/qualcomm/Makefile
33 +++ b/drivers/phy/qualcomm/Makefile
34 @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-
35 obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
36 obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
37 obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
38 +obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o
39 --- /dev/null
40 +++ b/drivers/phy/qualcomm/phy-qcom-dwc3.c
41 @@ -0,0 +1,575 @@
42 +/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved.
43 + *
44 + * This program is free software; you can redistribute it and/or modify
45 + * it under the terms of the GNU General Public License version 2 and
46 + * only version 2 as published by the Free Software Foundation.
47 + *
48 +* This program is distributed in the hope that it will be useful,
49 +* but WITHOUT ANY WARRANTY; without even the implied warranty of
50 +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
51 +* GNU General Public License for more details.
52 +*/
53 +
54 +#include <linux/clk.h>
55 +#include <linux/err.h>
56 +#include <linux/io.h>
57 +#include <linux/module.h>
58 +#include <linux/of.h>
59 +#include <linux/phy/phy.h>
60 +#include <linux/platform_device.h>
61 +#include <linux/delay.h>
62 +
63 +/**
64 + * USB QSCRATCH Hardware registers
65 + */
66 +#define QSCRATCH_GENERAL_CFG (0x08)
67 +#define HSUSB_PHY_CTRL_REG (0x10)
68 +
69 +/* PHY_CTRL_REG */
70 +#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
71 +#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
72 +#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
73 +#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
74 +#define HSUSB_CTRL_USE_CLKCORE BIT(18)
75 +#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
76 +#define HSUSB_CTRL_COMMONONN BIT(11)
77 +#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
78 +#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
79 +#define HSUSB_CTRL_CLAMP_EN BIT(7)
80 +#define HSUSB_CTRL_RETENABLEN BIT(1)
81 +#define HSUSB_CTRL_POR BIT(0)
82 +
83 +/* QSCRATCH_GENERAL_CFG */
84 +#define HSUSB_GCFG_XHCI_REV BIT(2)
85 +
86 +/**
87 + * USB QSCRATCH Hardware registers
88 + */
89 +#define SSUSB_PHY_CTRL_REG (0x00)
90 +#define SSUSB_PHY_PARAM_CTRL_1 (0x04)
91 +#define SSUSB_PHY_PARAM_CTRL_2 (0x08)
92 +#define CR_PROTOCOL_DATA_IN_REG (0x0c)
93 +#define CR_PROTOCOL_DATA_OUT_REG (0x10)
94 +#define CR_PROTOCOL_CAP_ADDR_REG (0x14)
95 +#define CR_PROTOCOL_CAP_DATA_REG (0x18)
96 +#define CR_PROTOCOL_READ_REG (0x1c)
97 +#define CR_PROTOCOL_WRITE_REG (0x20)
98 +
99 +/* PHY_CTRL_REG */
100 +#define SSUSB_CTRL_REF_USE_PAD BIT(28)
101 +#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
102 +#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
103 +#define SSUSB_CTRL_SS_PHY_EN BIT(8)
104 +#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
105 +
106 +/* SSPHY control registers */
107 +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane)
108 +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane)
109 +
110 +/* SSPHY SoC version specific values */
111 +#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */
112 +#define SSPHY_TX_DEEMPH_3_5DB 23 /* Override value for transmit
113 + preemphasis */
114 +#define SSPHY_MPLL_VALUE 0 /* Override value for mpll */
115 +
116 +/* QSCRATCH PHY_PARAM_CTRL1 fields */
117 +#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK 0x07f00000u
118 +#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK 0x000fc000u
119 +#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK 0x00003f00u
120 +#define PHY_PARAM_CTRL1_LOS_BIAS_MASK 0x000000f8u
121 +
122 +#define PHY_PARAM_CTRL1_MASK \
123 + (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \
124 + PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \
125 + PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
126 + PHY_PARAM_CTRL1_LOS_BIAS_MASK)
127 +
128 +#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \
129 + (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
130 +#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \
131 + (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
132 +#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \
133 + (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
134 +#define PHY_PARAM_CTRL1_LOS_BIAS(x) \
135 + (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
136 +
137 +/* RX OVRD IN HI bits */
138 +#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
139 +#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
140 +#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
141 +#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700
142 +#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8
143 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
144 +#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
145 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
146 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018
147 +#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
148 +#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003
149 +
150 +/* TX OVRD DRV LO register bits */
151 +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F
152 +#define TX_OVRD_DRV_LO_PREEMPH_MASK 0x3F80
153 +#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7
154 +#define TX_OVRD_DRV_LO_EN BIT(14)
155 +
156 +/* SS CAP register bits */
157 +#define SS_CR_CAP_ADDR_REG BIT(0)
158 +#define SS_CR_CAP_DATA_REG BIT(0)
159 +#define SS_CR_READ_REG BIT(0)
160 +#define SS_CR_WRITE_REG BIT(0)
161 +
162 +struct qcom_dwc3_usb_phy {
163 + void __iomem *base;
164 + struct device *dev;
165 + struct clk *xo_clk;
166 + struct clk *ref_clk;
167 + u32 rx_eq;
168 + u32 tx_deamp_3_5db;
169 + u32 mpll;
170 +};
171 +
172 +struct qcom_dwc3_phy_drvdata {
173 + struct phy_ops ops;
174 + u32 clk_rate;
175 +};
176 +
177 +/**
178 + * Write register and read back masked value to confirm it is written
179 + *
180 + * @base - QCOM DWC3 PHY base virtual address.
181 + * @offset - register offset.
182 + * @mask - register bitmask specifying what should be updated
183 + * @val - value to write.
184 + */
185 +static inline void qcom_dwc3_phy_write_readback(
186 + struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
187 + const u32 mask, u32 val)
188 +{
189 + u32 write_val, tmp = readl(phy_dwc3->base + offset);
190 +
191 + tmp &= ~mask; /* retain other bits */
192 + write_val = tmp | val;
193 +
194 + writel(write_val, phy_dwc3->base + offset);
195 +
196 + /* Read back to see if val was written */
197 + tmp = readl(phy_dwc3->base + offset);
198 + tmp &= mask; /* clear other bits */
199 +
200 + if (tmp != val)
201 + dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n",
202 + val, offset);
203 +}
204 +
205 +static int wait_for_latch(void __iomem *addr)
206 +{
207 + u32 retry = 10;
208 +
209 + while (true) {
210 + if (!readl(addr))
211 + break;
212 +
213 + if (--retry == 0)
214 + return -ETIMEDOUT;
215 +
216 + usleep_range(10, 20);
217 + }
218 +
219 + return 0;
220 +}
221 +
222 +/**
223 + * Write SSPHY register
224 + *
225 + * @base - QCOM DWC3 PHY base virtual address.
226 + * @addr - SSPHY address to write.
227 + * @val - value to write.
228 + */
229 +static int qcom_dwc3_ss_write_phycreg(struct qcom_dwc3_usb_phy *phy_dwc3,
230 + u32 addr, u32 val)
231 +{
232 + int ret;
233 +
234 + writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
235 + writel(SS_CR_CAP_ADDR_REG, phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
236 +
237 + ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
238 + if (ret)
239 + goto err_wait;
240 +
241 + writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
242 + writel(SS_CR_CAP_DATA_REG, phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
243 +
244 + ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
245 + if (ret)
246 + goto err_wait;
247 +
248 + writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
249 +
250 + ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
251 +
252 +err_wait:
253 + if (ret)
254 + dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
255 + return ret;
256 +}
257 +
258 +/**
259 + * Read SSPHY register.
260 + *
261 + * @base - QCOM DWC3 PHY base virtual address.
262 + * @addr - SSPHY address to read.
263 + */
264 +static int qcom_dwc3_ss_read_phycreg(void __iomem *base, u32 addr, u32 *val)
265 +{
266 + int ret;
267 +
268 + writel(addr, base + CR_PROTOCOL_DATA_IN_REG);
269 + writel(SS_CR_CAP_ADDR_REG, base + CR_PROTOCOL_CAP_ADDR_REG);
270 +
271 + ret = wait_for_latch(base + CR_PROTOCOL_CAP_ADDR_REG);
272 + if (ret)
273 + goto err_wait;
274 +
275 + /*
276 + * Due to hardware bug, first read of SSPHY register might be
277 + * incorrect. Hence as workaround, SW should perform SSPHY register
278 + * read twice, but use only second read and ignore first read.
279 + */
280 + writel(SS_CR_READ_REG, base + CR_PROTOCOL_READ_REG);
281 +
282 + ret = wait_for_latch(base + CR_PROTOCOL_READ_REG);
283 + if (ret)
284 + goto err_wait;
285 +
286 + /* throwaway read */
287 + readl(base + CR_PROTOCOL_DATA_OUT_REG);
288 +
289 + writel(SS_CR_READ_REG, base + CR_PROTOCOL_READ_REG);
290 +
291 + ret = wait_for_latch(base + CR_PROTOCOL_READ_REG);
292 + if (ret)
293 + goto err_wait;
294 +
295 + *val = readl(base + CR_PROTOCOL_DATA_OUT_REG);
296 +
297 +err_wait:
298 + return ret;
299 +}
300 +
301 +static int qcom_dwc3_hs_phy_init(struct phy *phy)
302 +{
303 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
304 + int ret;
305 + u32 val;
306 +
307 + ret = clk_prepare_enable(phy_dwc3->xo_clk);
308 + if (ret)
309 + return ret;
310 +
311 + ret = clk_prepare_enable(phy_dwc3->ref_clk);
312 + if (ret) {
313 + clk_disable_unprepare(phy_dwc3->xo_clk);
314 + return ret;
315 + }
316 +
317 + /*
318 + * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
319 + * enable clamping, and disable RETENTION (power-on default is ENABLED)
320 + */
321 + val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
322 + HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
323 + HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
324 + HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
325 + HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
326 +
327 + /* use core clock if external reference is not present */
328 + if (!phy_dwc3->xo_clk)
329 + val |= HSUSB_CTRL_USE_CLKCORE;
330 +
331 + writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
332 + usleep_range(2000, 2200);
333 +
334 + /* Disable (bypass) VBUS and ID filters */
335 + writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
336 +
337 + return 0;
338 +}
339 +
340 +static int qcom_dwc3_hs_phy_exit(struct phy *phy)
341 +{
342 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
343 +
344 + clk_disable_unprepare(phy_dwc3->ref_clk);
345 + clk_disable_unprepare(phy_dwc3->xo_clk);
346 +
347 + return 0;
348 +}
349 +
350 +static int qcom_dwc3_ss_phy_init(struct phy *phy)
351 +{
352 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
353 + int ret;
354 + u32 data = 0;
355 +
356 + ret = clk_prepare_enable(phy_dwc3->xo_clk);
357 + if (ret)
358 + return ret;
359 +
360 + ret = clk_prepare_enable(phy_dwc3->ref_clk);
361 + if (ret) {
362 + clk_disable_unprepare(phy_dwc3->xo_clk);
363 + return ret;
364 + }
365 +
366 + /* reset phy */
367 + data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
368 + writel(data | SSUSB_CTRL_SS_PHY_RESET,
369 + phy_dwc3->base + SSUSB_PHY_CTRL_REG);
370 + usleep_range(2000, 2200);
371 + writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
372 +
373 + /* clear REF_PAD if we don't have XO clk */
374 + if (!phy_dwc3->xo_clk)
375 + data &= ~SSUSB_CTRL_REF_USE_PAD;
376 + else
377 + data |= SSUSB_CTRL_REF_USE_PAD;
378 +
379 + writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
380 +
381 + /* wait for ref clk to become stable, this can take up to 30ms */
382 + msleep(30);
383 +
384 + data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
385 + writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
386 +
387 + /*
388 + * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
389 + * in HS mode instead of SS mode. Workaround it by asserting
390 + * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
391 + */
392 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x102D, &data);
393 + if (ret)
394 + goto err_phy_trans;
395 +
396 + data |= (1 << 7);
397 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x102D, data);
398 + if (ret)
399 + goto err_phy_trans;
400 +
401 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x1010, &data);
402 + if (ret)
403 + goto err_phy_trans;
404 +
405 + data &= ~0xff0;
406 + data |= 0x20;
407 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x1010, data);
408 + if (ret)
409 + goto err_phy_trans;
410 +
411 + /*
412 + * Fix RX Equalization setting as follows
413 + * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
414 + * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
415 + * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
416 + * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
417 + */
418 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
419 + SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
420 + if (ret)
421 + goto err_phy_trans;
422 +
423 + data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
424 + data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
425 + data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
426 + data |= phy_dwc3->rx_eq << RX_OVRD_IN_HI_RX_EQ_SHIFT;
427 + data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
428 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
429 + SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
430 + if (ret)
431 + goto err_phy_trans;
432 +
433 + /*
434 + * Set EQ and TX launch amplitudes as follows
435 + * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
436 + * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
437 + * LANE0.TX_OVRD_DRV_LO.EN set to 1.
438 + */
439 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
440 + SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
441 + if (ret)
442 + goto err_phy_trans;
443 +
444 + data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
445 + data |= phy_dwc3->tx_deamp_3_5db << TX_OVRD_DRV_LO_PREEMPH_SHIFT;
446 + data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
447 + data |= 0x6E;
448 + data |= TX_OVRD_DRV_LO_EN;
449 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
450 + SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
451 + if (ret)
452 + goto err_phy_trans;
453 +
454 + qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x30, phy_dwc3->mpll);
455 +
456 + /*
457 + * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
458 + * TX_FULL_SWING [26:20] amplitude to 110
459 + * TX_DEEMPH_6DB [19:14] to 32
460 + * TX_DEEMPH_3_5DB [13:8] set based on SoC version
461 + * LOS_BIAS [7:3] to 9
462 + */
463 + data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
464 +
465 + data &= ~PHY_PARAM_CTRL1_MASK;
466 +
467 + data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
468 + PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
469 + PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
470 + PHY_PARAM_CTRL1_LOS_BIAS(0x9);
471 +
472 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
473 + PHY_PARAM_CTRL1_MASK, data);
474 +
475 +err_phy_trans:
476 + return ret;
477 +}
478 +
479 +static int qcom_dwc3_ss_phy_exit(struct phy *phy)
480 +{
481 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
482 +
483 + /* Sequence to put SSPHY in low power state:
484 + * 1. Clear REF_PHY_EN in PHY_CTRL_REG
485 + * 2. Clear REF_USE_PAD in PHY_CTRL_REG
486 + * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
487 + */
488 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
489 + SSUSB_CTRL_SS_PHY_EN, 0x0);
490 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
491 + SSUSB_CTRL_REF_USE_PAD, 0x0);
492 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
493 + SSUSB_CTRL_TEST_POWERDOWN, 0x0);
494 +
495 + clk_disable_unprepare(phy_dwc3->ref_clk);
496 + clk_disable_unprepare(phy_dwc3->xo_clk);
497 +
498 + return 0;
499 +}
500 +
501 +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_hs_drvdata = {
502 + .ops = {
503 + .init = qcom_dwc3_hs_phy_init,
504 + .exit = qcom_dwc3_hs_phy_exit,
505 + .owner = THIS_MODULE,
506 + },
507 + .clk_rate = 60000000,
508 +};
509 +
510 +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_ss_drvdata = {
511 + .ops = {
512 + .init = qcom_dwc3_ss_phy_init,
513 + .exit = qcom_dwc3_ss_phy_exit,
514 + .owner = THIS_MODULE,
515 + },
516 + .clk_rate = 125000000,
517 +};
518 +
519 +static const struct of_device_id qcom_dwc3_phy_table[] = {
520 + { .compatible = "qcom,dwc3-hs-usb-phy", .data = &qcom_dwc3_hs_drvdata },
521 + { .compatible = "qcom,dwc3-ss-usb-phy", .data = &qcom_dwc3_ss_drvdata },
522 + { /* Sentinel */ }
523 +};
524 +MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table);
525 +
526 +static int qcom_dwc3_phy_probe(struct platform_device *pdev)
527 +{
528 + struct qcom_dwc3_usb_phy *phy_dwc3;
529 + struct phy_provider *phy_provider;
530 + struct phy *generic_phy;
531 + struct resource *res;
532 + const struct of_device_id *match;
533 + const struct qcom_dwc3_phy_drvdata *data;
534 + struct device_node *np;
535 +
536 + phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
537 + if (!phy_dwc3)
538 + return -ENOMEM;
539 +
540 + match = of_match_node(qcom_dwc3_phy_table, pdev->dev.of_node);
541 + data = match->data;
542 +
543 + phy_dwc3->dev = &pdev->dev;
544 +
545 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
546 + phy_dwc3->base = devm_ioremap_resource(phy_dwc3->dev, res);
547 + if (IS_ERR(phy_dwc3->base))
548 + return PTR_ERR(phy_dwc3->base);
549 +
550 + phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
551 + if (IS_ERR(phy_dwc3->ref_clk)) {
552 + dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
553 + return PTR_ERR(phy_dwc3->ref_clk);
554 + }
555 +
556 + clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
557 +
558 + phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
559 + if (IS_ERR(phy_dwc3->xo_clk)) {
560 + dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
561 + phy_dwc3->xo_clk = NULL;
562 + }
563 +
564 + /* Parse device node to probe HSIO settings */
565 + np = of_node_get(pdev->dev.of_node);
566 + if (!of_compat_cmp(match->compatible, "qcom,dwc3-ss-usb-phy",
567 + strlen(match->compatible))) {
568 +
569 + if (of_property_read_u32(np, "rx_eq", &phy_dwc3->rx_eq) ||
570 + of_property_read_u32(np, "tx_deamp_3_5db",
571 + &phy_dwc3->tx_deamp_3_5db) ||
572 + of_property_read_u32(np, "mpll", &phy_dwc3->mpll)) {
573 +
574 + dev_err(phy_dwc3->dev, "cannot get HSIO settings from device node, using default values\n");
575 +
576 + /* Default HSIO settings */
577 + phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
578 + phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
579 + phy_dwc3->mpll = SSPHY_MPLL_VALUE;
580 + }
581 + }
582 +
583 + generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node,
584 + &data->ops);
585 +
586 + if (IS_ERR(generic_phy))
587 + return PTR_ERR(generic_phy);
588 +
589 + phy_set_drvdata(generic_phy, phy_dwc3);
590 + platform_set_drvdata(pdev, phy_dwc3);
591 +
592 + phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
593 + of_phy_simple_xlate);
594 +
595 + if (IS_ERR(phy_provider))
596 + return PTR_ERR(phy_provider);
597 +
598 + return 0;
599 +}
600 +
601 +static struct platform_driver qcom_dwc3_phy_driver = {
602 + .probe = qcom_dwc3_phy_probe,
603 + .driver = {
604 + .name = "qcom-dwc3-usb-phy",
605 + .owner = THIS_MODULE,
606 + .of_match_table = qcom_dwc3_phy_table,
607 + },
608 +};
609 +
610 +module_platform_driver(qcom_dwc3_phy_driver);
611 +
612 +MODULE_ALIAS("platform:phy-qcom-dwc3");
613 +MODULE_LICENSE("GPL v2");
614 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
615 +MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
616 +MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");