OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
---|---|---|---|
4 | office | 1 | /dts-v1/; |
2 | |||
3 | #include "skeleton.dtsi" |
||
4 | #include <dt-bindings/clock/qcom,gcc-ipq806x.h> |
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5 | #include <dt-bindings/mfd/qcom-rpm.h> |
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6 | #include <dt-bindings/clock/qcom,rpmcc.h> |
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7 | #include <dt-bindings/clock/qcom,lcc-ipq806x.h> |
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8 | #include <dt-bindings/soc/qcom,gsbi.h> |
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9 | #include <dt-bindings/reset/qcom,gcc-ipq806x.h> |
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10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
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11 | #include <dt-bindings/gpio/gpio.h> |
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12 | |||
13 | / { |
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14 | model = "Qualcomm IPQ8064"; |
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15 | compatible = "qcom,ipq8064"; |
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16 | interrupt-parent = <&intc>; |
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17 | |||
18 | cpus { |
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19 | #address-cells = <1>; |
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20 | #size-cells = <0>; |
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21 | |||
22 | cpu0: cpu@0 { |
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23 | compatible = "qcom,krait"; |
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24 | enable-method = "qcom,kpss-acc-v1"; |
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25 | device_type = "cpu"; |
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26 | reg = <0>; |
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27 | next-level-cache = <&L2>; |
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28 | qcom,acc = <&acc0>; |
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29 | qcom,saw = <&saw0>; |
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30 | clocks = <&kraitcc 0>, <&kraitcc 4>; |
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31 | clock-names = "cpu", "l2"; |
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32 | clock-latency = <100000>; |
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33 | cpu-supply = <&smb208_s2a>; |
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34 | voltage-tolerance = <5>; |
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35 | cooling-min-state = <0>; |
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36 | cooling-max-state = <10>; |
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37 | #cooling-cells = <2>; |
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38 | cpu-idle-states = <&CPU_SPC>; |
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39 | }; |
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40 | |||
41 | cpu1: cpu@1 { |
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42 | compatible = "qcom,krait"; |
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43 | enable-method = "qcom,kpss-acc-v1"; |
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44 | device_type = "cpu"; |
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45 | reg = <1>; |
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46 | next-level-cache = <&L2>; |
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47 | qcom,acc = <&acc1>; |
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48 | qcom,saw = <&saw1>; |
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49 | clocks = <&kraitcc 1>, <&kraitcc 4>; |
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50 | clock-names = "cpu", "l2"; |
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51 | clock-latency = <100000>; |
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52 | cpu-supply = <&smb208_s2b>; |
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53 | cooling-min-state = <0>; |
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54 | cooling-max-state = <10>; |
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55 | #cooling-cells = <2>; |
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56 | cpu-idle-states = <&CPU_SPC>; |
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57 | }; |
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58 | |||
59 | L2: l2-cache { |
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60 | compatible = "cache"; |
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61 | cache-level = <2>; |
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62 | qcom,saw = <&saw_l2>; |
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63 | }; |
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64 | |||
65 | qcom,l2 { |
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66 | qcom,l2-rates = <384000000 1000000000 1200000000>; |
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67 | }; |
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68 | |||
69 | idle-states { |
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70 | CPU_SPC: spc { |
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71 | compatible = "qcom,idle-state-spc", |
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72 | "arm,idle-state"; |
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73 | entry-latency-us = <400>; |
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74 | exit-latency-us = <900>; |
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75 | min-residency-us = <3000>; |
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76 | }; |
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77 | }; |
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78 | }; |
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79 | |||
80 | thermal-zones { |
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81 | tsens_tz_sensor0 { |
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82 | polling-delay-passive = <0>; |
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83 | polling-delay = <0>; |
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84 | thermal-sensors = <&tsens 0>; |
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85 | |||
86 | trips { |
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87 | cpu-critical-hi { |
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88 | temperature = <125000>; |
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89 | hysteresis = <2000>; |
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90 | type = "critical_high"; |
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91 | }; |
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92 | |||
93 | cpu-config-hi { |
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94 | temperature = <105000>; |
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95 | hysteresis = <2000>; |
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96 | type = "configurable_hi"; |
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97 | }; |
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98 | |||
99 | cpu-config-lo { |
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100 | temperature = <95000>; |
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101 | hysteresis = <2000>; |
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102 | type = "configurable_lo"; |
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103 | }; |
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104 | |||
105 | cpu-critical-low { |
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106 | temperature = <0>; |
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107 | hysteresis = <2000>; |
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108 | type = "critical_low"; |
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109 | }; |
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110 | }; |
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111 | }; |
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112 | |||
113 | tsens_tz_sensor1 { |
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114 | polling-delay-passive = <0>; |
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115 | polling-delay = <0>; |
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116 | thermal-sensors = <&tsens 1>; |
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117 | |||
118 | trips { |
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119 | cpu-critical-hi { |
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120 | temperature = <125000>; |
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121 | hysteresis = <2000>; |
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122 | type = "critical_high"; |
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123 | }; |
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124 | |||
125 | cpu-config-hi { |
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126 | temperature = <105000>; |
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127 | hysteresis = <2000>; |
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128 | type = "configurable_hi"; |
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129 | }; |
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130 | |||
131 | cpu-config-lo { |
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132 | temperature = <95000>; |
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133 | hysteresis = <2000>; |
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134 | type = "configurable_lo"; |
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135 | }; |
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136 | |||
137 | cpu-critical-low { |
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138 | temperature = <0>; |
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139 | hysteresis = <2000>; |
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140 | type = "critical_low"; |
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141 | }; |
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142 | }; |
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143 | }; |
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144 | |||
145 | tsens_tz_sensor2 { |
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146 | polling-delay-passive = <0>; |
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147 | polling-delay = <0>; |
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148 | thermal-sensors = <&tsens 2>; |
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149 | |||
150 | trips { |
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151 | cpu-critical-hi { |
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152 | temperature = <125000>; |
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153 | hysteresis = <2000>; |
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154 | type = "critical_high"; |
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155 | }; |
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156 | |||
157 | cpu-config-hi { |
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158 | temperature = <105000>; |
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159 | hysteresis = <2000>; |
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160 | type = "configurable_hi"; |
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161 | }; |
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162 | |||
163 | cpu-config-lo { |
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164 | temperature = <95000>; |
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165 | hysteresis = <2000>; |
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166 | type = "configurable_lo"; |
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167 | }; |
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168 | |||
169 | cpu-critical-low { |
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170 | temperature = <0>; |
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171 | hysteresis = <2000>; |
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172 | type = "critical_low"; |
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173 | }; |
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174 | }; |
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175 | }; |
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176 | |||
177 | tsens_tz_sensor3 { |
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178 | polling-delay-passive = <0>; |
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179 | polling-delay = <0>; |
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180 | thermal-sensors = <&tsens 3>; |
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181 | |||
182 | trips { |
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183 | cpu-critical-hi { |
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184 | temperature = <125000>; |
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185 | hysteresis = <2000>; |
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186 | type = "critical_high"; |
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187 | }; |
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188 | |||
189 | cpu-config-hi { |
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190 | temperature = <105000>; |
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191 | hysteresis = <2000>; |
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192 | type = "configurable_hi"; |
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193 | }; |
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194 | |||
195 | cpu-config-lo { |
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196 | temperature = <95000>; |
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197 | hysteresis = <2000>; |
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198 | type = "configurable_lo"; |
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199 | }; |
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200 | |||
201 | cpu-critical-low { |
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202 | temperature = <0>; |
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203 | hysteresis = <2000>; |
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204 | type = "critical_low"; |
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205 | }; |
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206 | }; |
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207 | }; |
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208 | |||
209 | tsens_tz_sensor4 { |
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210 | polling-delay-passive = <0>; |
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211 | polling-delay = <0>; |
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212 | thermal-sensors = <&tsens 4>; |
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213 | |||
214 | trips { |
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215 | cpu-critical-hi { |
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216 | temperature = <125000>; |
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217 | hysteresis = <2000>; |
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218 | type = "critical_high"; |
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219 | }; |
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220 | |||
221 | cpu-config-hi { |
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222 | temperature = <105000>; |
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223 | hysteresis = <2000>; |
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224 | type = "configurable_hi"; |
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225 | }; |
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226 | |||
227 | cpu-config-lo { |
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228 | temperature = <95000>; |
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229 | hysteresis = <2000>; |
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230 | type = "configurable_lo"; |
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231 | }; |
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232 | |||
233 | cpu-critical-low { |
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234 | temperature = <0>; |
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235 | hysteresis = <2000>; |
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236 | type = "critical_low"; |
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237 | }; |
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238 | }; |
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239 | }; |
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240 | |||
241 | tsens_tz_sensor5 { |
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242 | polling-delay-passive = <0>; |
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243 | polling-delay = <0>; |
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244 | thermal-sensors = <&tsens 5>; |
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245 | |||
246 | trips { |
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247 | cpu-critical-hi { |
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248 | temperature = <125000>; |
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249 | hysteresis = <2000>; |
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250 | type = "critical_high"; |
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251 | }; |
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252 | |||
253 | cpu-config-hi { |
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254 | temperature = <105000>; |
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255 | hysteresis = <2000>; |
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256 | type = "configurable_hi"; |
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257 | }; |
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258 | |||
259 | cpu-config-lo { |
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260 | temperature = <95000>; |
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261 | hysteresis = <2000>; |
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262 | type = "configurable_lo"; |
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263 | }; |
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264 | |||
265 | cpu-critical-low { |
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266 | temperature = <0>; |
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267 | hysteresis = <2000>; |
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268 | type = "critical_low"; |
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269 | }; |
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270 | }; |
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271 | }; |
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272 | |||
273 | tsens_tz_sensor6 { |
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274 | polling-delay-passive = <0>; |
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275 | polling-delay = <0>; |
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276 | thermal-sensors = <&tsens 6>; |
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277 | |||
278 | trips { |
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279 | cpu-critical-hi { |
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280 | temperature = <125000>; |
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281 | hysteresis = <2000>; |
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282 | type = "critical_high"; |
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283 | }; |
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284 | |||
285 | cpu-config-hi { |
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286 | temperature = <105000>; |
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287 | hysteresis = <2000>; |
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288 | type = "configurable_hi"; |
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289 | }; |
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290 | |||
291 | cpu-config-lo { |
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292 | temperature = <95000>; |
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293 | hysteresis = <2000>; |
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294 | type = "configurable_lo"; |
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295 | }; |
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296 | |||
297 | cpu-critical-low { |
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298 | temperature = <0>; |
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299 | hysteresis = <2000>; |
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300 | type = "critical_low"; |
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301 | }; |
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302 | }; |
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303 | }; |
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304 | |||
305 | tsens_tz_sensor7 { |
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306 | polling-delay-passive = <0>; |
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307 | polling-delay = <0>; |
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308 | thermal-sensors = <&tsens 7>; |
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309 | |||
310 | trips { |
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311 | cpu-critical-hi { |
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312 | temperature = <125000>; |
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313 | hysteresis = <2000>; |
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314 | type = "critical_high"; |
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315 | }; |
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316 | |||
317 | cpu-config-hi { |
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318 | temperature = <105000>; |
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319 | hysteresis = <2000>; |
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320 | type = "configurable_hi"; |
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321 | }; |
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322 | |||
323 | cpu-config-lo { |
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324 | temperature = <95000>; |
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325 | hysteresis = <2000>; |
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326 | type = "configurable_lo"; |
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327 | }; |
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328 | |||
329 | cpu-critical-low { |
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330 | temperature = <0>; |
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331 | hysteresis = <2000>; |
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332 | type = "critical_low"; |
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333 | }; |
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334 | }; |
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335 | }; |
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336 | |||
337 | tsens_tz_sensor8 { |
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338 | polling-delay-passive = <0>; |
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339 | polling-delay = <0>; |
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340 | thermal-sensors = <&tsens 8>; |
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341 | |||
342 | trips { |
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343 | cpu-critical-hi { |
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344 | temperature = <125000>; |
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345 | hysteresis = <2000>; |
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346 | type = "critical_high"; |
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347 | }; |
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348 | |||
349 | cpu-config-hi { |
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350 | temperature = <105000>; |
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351 | hysteresis = <2000>; |
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352 | type = "configurable_hi"; |
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353 | }; |
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354 | |||
355 | cpu-config-lo { |
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356 | temperature = <95000>; |
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357 | hysteresis = <2000>; |
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358 | type = "configurable_lo"; |
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359 | }; |
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360 | |||
361 | cpu-critical-low { |
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362 | temperature = <0>; |
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363 | hysteresis = <2000>; |
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364 | type = "critical_low"; |
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365 | }; |
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366 | }; |
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367 | }; |
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368 | |||
369 | tsens_tz_sensor9 { |
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370 | polling-delay-passive = <0>; |
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371 | polling-delay = <0>; |
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372 | thermal-sensors = <&tsens 9>; |
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373 | |||
374 | trips { |
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375 | cpu-critical-hi { |
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376 | temperature = <125000>; |
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377 | hysteresis = <2000>; |
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378 | type = "critical_high"; |
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379 | }; |
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380 | |||
381 | cpu-config-hi { |
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382 | temperature = <105000>; |
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383 | hysteresis = <2000>; |
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384 | type = "configurable_hi"; |
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385 | }; |
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386 | |||
387 | cpu-config-lo { |
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388 | temperature = <95000>; |
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389 | hysteresis = <2000>; |
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390 | type = "configurable_lo"; |
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391 | }; |
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392 | |||
393 | cpu-critical-low { |
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394 | temperature = <0>; |
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395 | hysteresis = <2000>; |
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396 | type = "critical_low"; |
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397 | }; |
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398 | }; |
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399 | }; |
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400 | |||
401 | tsens_tz_sensor10 { |
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402 | polling-delay-passive = <0>; |
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403 | polling-delay = <0>; |
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404 | thermal-sensors = <&tsens 10>; |
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405 | |||
406 | trips { |
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407 | cpu-critical-hi { |
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408 | temperature = <125000>; |
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409 | hysteresis = <2000>; |
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410 | type = "critical_high"; |
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411 | }; |
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412 | |||
413 | cpu-config-hi { |
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414 | temperature = <105000>; |
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415 | hysteresis = <2000>; |
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416 | type = "configurable_hi"; |
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417 | }; |
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418 | |||
419 | cpu-config-lo { |
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420 | temperature = <95000>; |
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421 | hysteresis = <2000>; |
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422 | type = "configurable_lo"; |
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423 | }; |
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424 | |||
425 | cpu-critical-low { |
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426 | temperature = <0>; |
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427 | hysteresis = <2000>; |
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428 | type = "critical_low"; |
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429 | }; |
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430 | }; |
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431 | }; |
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432 | }; |
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433 | |||
434 | cpu-pmu { |
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435 | compatible = "qcom,krait-pmu"; |
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436 | interrupts = <1 10 0x304>; |
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437 | }; |
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438 | |||
439 | reserved-memory { |
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440 | #address-cells = <1>; |
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441 | #size-cells = <1>; |
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442 | ranges; |
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443 | |||
444 | nss@40000000 { |
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445 | reg = <0x40000000 0x1000000>; |
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446 | no-map; |
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447 | }; |
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448 | |||
449 | smem: smem@41000000 { |
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450 | reg = <0x41000000 0x200000>; |
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451 | no-map; |
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452 | }; |
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453 | }; |
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454 | |||
455 | clocks { |
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456 | cxo_board { |
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457 | compatible = "fixed-clock"; |
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458 | #clock-cells = <0>; |
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459 | clock-frequency = <25000000>; |
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460 | }; |
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461 | |||
462 | pxo_board { |
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463 | compatible = "fixed-clock"; |
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464 | #clock-cells = <0>; |
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465 | clock-frequency = <25000000>; |
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466 | }; |
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467 | |||
468 | sleep_clk: sleep_clk { |
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469 | compatible = "fixed-clock"; |
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470 | clock-frequency = <32768>; |
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471 | #clock-cells = <0>; |
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472 | }; |
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473 | }; |
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474 | |||
475 | firmware { |
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476 | scm { |
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477 | compatible = "qcom,scm-ipq806x"; |
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478 | }; |
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479 | }; |
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480 | |||
481 | kraitcc: clock-controller { |
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482 | compatible = "qcom,krait-cc-v1"; |
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483 | #clock-cells = <1>; |
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484 | }; |
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485 | |||
486 | qcom,pvs { |
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487 | qcom,pvs-format-a; |
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488 | qcom,speed0-pvs0-bin-v0 = |
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489 | < 1400000000 1250000 >, |
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490 | < 1200000000 1200000 >, |
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491 | < 1000000000 1150000 >, |
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492 | < 800000000 1100000 >, |
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493 | < 600000000 1050000 >, |
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494 | < 384000000 1000000 >; |
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495 | |||
496 | qcom,speed0-pvs1-bin-v0 = |
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497 | < 1400000000 1175000 >, |
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498 | < 1200000000 1125000 >, |
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499 | < 1000000000 1075000 >, |
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500 | < 800000000 1025000 >, |
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501 | < 600000000 975000 >, |
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502 | < 384000000 925000 >; |
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503 | |||
504 | qcom,speed0-pvs2-bin-v0 = |
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505 | < 1400000000 1125000 >, |
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506 | < 1200000000 1075000 >, |
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507 | < 1000000000 1025000 >, |
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508 | < 800000000 995000 >, |
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509 | < 600000000 925000 >, |
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510 | < 384000000 875000 >; |
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511 | |||
512 | qcom,speed0-pvs3-bin-v0 = |
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513 | < 1400000000 1050000 >, |
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514 | < 1200000000 1000000 >, |
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515 | < 1000000000 950000 >, |
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516 | < 800000000 900000 >, |
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517 | < 600000000 850000 >, |
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518 | < 384000000 800000 >; |
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519 | }; |
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520 | |||
521 | soc: soc { |
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522 | #address-cells = <1>; |
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523 | #size-cells = <1>; |
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524 | ranges; |
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525 | compatible = "simple-bus"; |
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526 | |||
527 | lpass@28100000 { |
||
528 | compatible = "qcom,lpass-cpu"; |
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529 | status = "disabled"; |
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530 | clocks = <&lcc AHBIX_CLK>, |
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531 | <&lcc MI2S_OSR_CLK>, |
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532 | <&lcc MI2S_BIT_CLK>; |
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533 | clock-names = "ahbix-clk", |
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534 | "mi2s-osr-clk", |
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535 | "mi2s-bit-clk"; |
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536 | interrupts = <0 85 1>; |
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537 | interrupt-names = "lpass-irq-lpaif"; |
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538 | reg = <0x28100000 0x10000>; |
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539 | reg-names = "lpass-lpaif"; |
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540 | }; |
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541 | |||
542 | qfprom: qfprom@700000 { |
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543 | compatible = "qcom,qfprom", "syscon"; |
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544 | reg = <0x700000 0x1000>; |
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545 | #address-cells = <1>; |
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546 | #size-cells = <1>; |
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547 | status = "okay"; |
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548 | tsens_calib: calib@400 { |
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549 | reg = <0x400 0x10>; |
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550 | }; |
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551 | tsens_backup: backup@410 { |
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552 | reg = <0x410 0x10>; |
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553 | }; |
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554 | }; |
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555 | |||
556 | rpm@108000 { |
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557 | compatible = "qcom,rpm-ipq8064"; |
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558 | reg = <0x108000 0x1000>; |
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559 | qcom,ipc = <&l2cc 0x8 2>; |
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560 | |||
561 | interrupts = <0 19 0>, |
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562 | <0 21 0>, |
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563 | <0 22 0>; |
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564 | interrupt-names = "ack", |
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565 | "err", |
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566 | "wakeup"; |
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567 | |||
568 | clocks = <&gcc RPM_MSG_RAM_H_CLK>; |
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569 | clock-names = "ram"; |
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570 | |||
571 | #address-cells = <1>; |
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572 | #size-cells = <0>; |
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573 | |||
574 | rpmcc: clock-controller { |
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575 | compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; |
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576 | #clock-cells = <1>; |
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577 | }; |
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578 | |||
579 | regulators { |
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580 | compatible = "qcom,rpm-smb208-regulators"; |
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581 | |||
582 | smb208_s1a: s1a { |
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583 | regulator-min-microvolt = <1050000>; |
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584 | regulator-max-microvolt = <1150000>; |
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585 | |||
586 | qcom,switch-mode-frequency = <1200000>; |
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587 | |||
588 | }; |
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589 | |||
590 | smb208_s1b: s1b { |
||
591 | regulator-min-microvolt = <1050000>; |
||
592 | regulator-max-microvolt = <1150000>; |
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593 | |||
594 | qcom,switch-mode-frequency = <1200000>; |
||
595 | }; |
||
596 | |||
597 | smb208_s2a: s2a { |
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598 | regulator-min-microvolt = < 800000>; |
||
599 | regulator-max-microvolt = <1250000>; |
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600 | |||
601 | qcom,switch-mode-frequency = <1200000>; |
||
602 | }; |
||
603 | |||
604 | smb208_s2b: s2b { |
||
605 | regulator-min-microvolt = < 800000>; |
||
606 | regulator-max-microvolt = <1250000>; |
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607 | |||
608 | qcom,switch-mode-frequency = <1200000>; |
||
609 | }; |
||
610 | }; |
||
611 | }; |
||
612 | |||
613 | rng@1a500000 { |
||
614 | compatible = "qcom,prng"; |
||
615 | reg = <0x1a500000 0x200>; |
||
616 | clocks = <&gcc PRNG_CLK>; |
||
617 | clock-names = "core"; |
||
618 | }; |
||
619 | |||
620 | qcom_pinmux: pinmux@800000 { |
||
621 | compatible = "qcom,ipq8064-pinctrl"; |
||
622 | reg = <0x800000 0x4000>; |
||
623 | |||
624 | gpio-controller; |
||
625 | #gpio-cells = <2>; |
||
626 | interrupt-controller; |
||
627 | #interrupt-cells = <2>; |
||
628 | interrupts = <0 16 0x4>; |
||
629 | |||
630 | pcie0_pins: pcie0_pinmux { |
||
631 | mux { |
||
632 | pins = "gpio3"; |
||
633 | function = "pcie1_rst"; |
||
634 | drive-strength = <2>; |
||
635 | bias-disable; |
||
636 | }; |
||
637 | }; |
||
638 | |||
639 | pcie1_pins: pcie1_pinmux { |
||
640 | mux { |
||
641 | pins = "gpio48"; |
||
642 | function = "pcie2_rst"; |
||
643 | drive-strength = <2>; |
||
644 | bias-disable; |
||
645 | }; |
||
646 | }; |
||
647 | |||
648 | pcie2_pins: pcie2_pinmux { |
||
649 | mux { |
||
650 | pins = "gpio63"; |
||
651 | function = "pcie3_rst"; |
||
652 | drive-strength = <2>; |
||
653 | bias-disable; |
||
654 | output-low; |
||
655 | }; |
||
656 | }; |
||
657 | }; |
||
658 | |||
659 | intc: interrupt-controller@2000000 { |
||
660 | compatible = "qcom,msm-qgic2"; |
||
661 | interrupt-controller; |
||
662 | #interrupt-cells = <3>; |
||
663 | reg = <0x02000000 0x1000>, |
||
664 | <0x02002000 0x1000>; |
||
665 | }; |
||
666 | |||
667 | timer@200a000 { |
||
668 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; |
||
669 | interrupts = <1 1 0x301>, |
||
670 | <1 2 0x301>, |
||
671 | <1 3 0x301>, |
||
672 | <1 4 0x301>, |
||
673 | <1 5 0x301>; |
||
674 | reg = <0x0200a000 0x100>; |
||
675 | clock-frequency = <25000000>, |
||
676 | <32768>; |
||
677 | clocks = <&sleep_clk>; |
||
678 | clock-names = "sleep"; |
||
679 | cpu-offset = <0x80000>; |
||
680 | }; |
||
681 | |||
682 | acc0: clock-controller@2088000 { |
||
683 | compatible = "qcom,kpss-acc-v1"; |
||
684 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; |
||
685 | clock-output-names = "acpu0_aux"; |
||
686 | }; |
||
687 | |||
688 | acc1: clock-controller@2098000 { |
||
689 | compatible = "qcom,kpss-acc-v1"; |
||
690 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; |
||
691 | clock-output-names = "acpu1_aux"; |
||
692 | }; |
||
693 | |||
694 | l2cc: clock-controller@2011000 { |
||
695 | compatible = "qcom,kpss-gcc", "syscon"; |
||
696 | reg = <0x2011000 0x1000>; |
||
697 | clock-output-names = "acpu_l2_aux"; |
||
698 | }; |
||
699 | |||
700 | saw0: regulator@2089000 { |
||
701 | compatible = "qcom,saw2", "syscon"; |
||
702 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; |
||
703 | regulator; |
||
704 | }; |
||
705 | |||
706 | saw1: regulator@2099000 { |
||
707 | compatible = "qcom,saw2", "syscon"; |
||
708 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; |
||
709 | regulator; |
||
710 | }; |
||
711 | |||
712 | saw_l2: regulator@02012000 { |
||
713 | compatible = "qcom,saw2", "syscon"; |
||
714 | reg = <0x02012000 0x1000>; |
||
715 | regulator; |
||
716 | }; |
||
717 | |||
718 | sic_non_secure: sic-non-secure@12100000 { |
||
719 | compatible = "syscon"; |
||
720 | reg = <0x12100000 0x10000>; |
||
721 | }; |
||
722 | |||
723 | gsbi2: gsbi@12480000 { |
||
724 | compatible = "qcom,gsbi-v1.0.0"; |
||
725 | cell-index = <2>; |
||
726 | reg = <0x12480000 0x100>; |
||
727 | clocks = <&gcc GSBI2_H_CLK>; |
||
728 | clock-names = "iface"; |
||
729 | #address-cells = <1>; |
||
730 | #size-cells = <1>; |
||
731 | ranges; |
||
732 | status = "disabled"; |
||
733 | |||
734 | syscon-tcsr = <&tcsr>; |
||
735 | |||
736 | uart2: serial@12490000 { |
||
737 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
||
738 | reg = <0x12490000 0x1000>, |
||
739 | <0x12480000 0x1000>; |
||
740 | interrupts = <0 195 0x0>; |
||
741 | clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; |
||
742 | clock-names = "core", "iface"; |
||
743 | status = "disabled"; |
||
744 | }; |
||
745 | |||
746 | i2c@124a0000 { |
||
747 | compatible = "qcom,i2c-qup-v1.1.1"; |
||
748 | reg = <0x124a0000 0x1000>; |
||
749 | interrupts = <0 196 0>; |
||
750 | |||
751 | clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; |
||
752 | clock-names = "core", "iface"; |
||
753 | status = "disabled"; |
||
754 | |||
755 | #address-cells = <1>; |
||
756 | #size-cells = <0>; |
||
757 | }; |
||
758 | |||
759 | }; |
||
760 | |||
761 | gsbi4: gsbi@16300000 { |
||
762 | compatible = "qcom,gsbi-v1.0.0"; |
||
763 | cell-index = <4>; |
||
764 | reg = <0x16300000 0x100>; |
||
765 | clocks = <&gcc GSBI4_H_CLK>; |
||
766 | clock-names = "iface"; |
||
767 | #address-cells = <1>; |
||
768 | #size-cells = <1>; |
||
769 | ranges; |
||
770 | status = "disabled"; |
||
771 | |||
772 | syscon-tcsr = <&tcsr>; |
||
773 | |||
774 | gsbi4_serial: serial@16340000 { |
||
775 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
||
776 | reg = <0x16340000 0x1000>, |
||
777 | <0x16300000 0x1000>; |
||
778 | interrupts = <0 152 0x0>; |
||
779 | clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; |
||
780 | clock-names = "core", "iface"; |
||
781 | status = "disabled"; |
||
782 | }; |
||
783 | |||
784 | i2c@16380000 { |
||
785 | compatible = "qcom,i2c-qup-v1.1.1"; |
||
786 | reg = <0x16380000 0x1000>; |
||
787 | interrupts = <0 153 0>; |
||
788 | |||
789 | clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; |
||
790 | clock-names = "core", "iface"; |
||
791 | status = "disabled"; |
||
792 | |||
793 | #address-cells = <1>; |
||
794 | #size-cells = <0>; |
||
795 | }; |
||
796 | }; |
||
797 | |||
798 | gsbi5: gsbi@1a200000 { |
||
799 | compatible = "qcom,gsbi-v1.0.0"; |
||
800 | cell-index = <5>; |
||
801 | reg = <0x1a200000 0x100>; |
||
802 | clocks = <&gcc GSBI5_H_CLK>; |
||
803 | clock-names = "iface"; |
||
804 | #address-cells = <1>; |
||
805 | #size-cells = <1>; |
||
806 | ranges; |
||
807 | status = "disabled"; |
||
808 | |||
809 | syscon-tcsr = <&tcsr>; |
||
810 | |||
811 | uart5: serial@1a240000 { |
||
812 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
||
813 | reg = <0x1a240000 0x1000>, |
||
814 | <0x1a200000 0x1000>; |
||
815 | interrupts = <0 154 0x0>; |
||
816 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; |
||
817 | clock-names = "core", "iface"; |
||
818 | status = "disabled"; |
||
819 | }; |
||
820 | |||
821 | i2c@1a280000 { |
||
822 | compatible = "qcom,i2c-qup-v1.1.1"; |
||
823 | reg = <0x1a280000 0x1000>; |
||
824 | interrupts = <0 155 0>; |
||
825 | |||
826 | clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; |
||
827 | clock-names = "core", "iface"; |
||
828 | status = "disabled"; |
||
829 | |||
830 | #address-cells = <1>; |
||
831 | #size-cells = <0>; |
||
832 | }; |
||
833 | |||
834 | spi@1a280000 { |
||
835 | compatible = "qcom,spi-qup-v1.1.1"; |
||
836 | reg = <0x1a280000 0x1000>; |
||
837 | interrupts = <0 155 0>; |
||
838 | |||
839 | clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; |
||
840 | clock-names = "core", "iface"; |
||
841 | status = "disabled"; |
||
842 | |||
843 | #address-cells = <1>; |
||
844 | #size-cells = <0>; |
||
845 | }; |
||
846 | }; |
||
847 | |||
848 | sata_phy: sata-phy@1b400000 { |
||
849 | compatible = "qcom,ipq806x-sata-phy"; |
||
850 | reg = <0x1b400000 0x200>; |
||
851 | |||
852 | clocks = <&gcc SATA_PHY_CFG_CLK>; |
||
853 | clock-names = "cfg"; |
||
854 | |||
855 | #phy-cells = <0>; |
||
856 | status = "disabled"; |
||
857 | }; |
||
858 | |||
859 | sata@29000000 { |
||
860 | compatible = "qcom,ipq806x-ahci", "generic-ahci"; |
||
861 | reg = <0x29000000 0x180>; |
||
862 | |||
863 | interrupts = <0 209 0x0>; |
||
864 | |||
865 | clocks = <&gcc SFAB_SATA_S_H_CLK>, |
||
866 | <&gcc SATA_H_CLK>, |
||
867 | <&gcc SATA_A_CLK>, |
||
868 | <&gcc SATA_RXOOB_CLK>, |
||
869 | <&gcc SATA_PMALIVE_CLK>; |
||
870 | clock-names = "slave_face", "iface", "core", |
||
871 | "rxoob", "pmalive"; |
||
872 | |||
873 | assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; |
||
874 | assigned-clock-rates = <100000000>, <100000000>; |
||
875 | |||
876 | phys = <&sata_phy>; |
||
877 | phy-names = "sata-phy"; |
||
878 | status = "disabled"; |
||
879 | }; |
||
880 | |||
881 | qcom,ssbi@500000 { |
||
882 | compatible = "qcom,ssbi"; |
||
883 | reg = <0x00500000 0x1000>; |
||
884 | qcom,controller-type = "pmic-arbiter"; |
||
885 | }; |
||
886 | |||
887 | gcc: clock-controller@900000 { |
||
888 | compatible = "qcom,gcc-ipq8064"; |
||
889 | reg = <0x00900000 0x4000>; |
||
890 | #clock-cells = <1>; |
||
891 | #reset-cells = <1>; |
||
892 | #power-domain-cells = <1>; |
||
893 | }; |
||
894 | |||
895 | tsens: thermal-sensor@900000 { |
||
896 | compatible = "qcom,ipq8064-tsens"; |
||
897 | reg = <0x900000 0x3680>; |
||
898 | nvmem-cells = <&tsens_calib>, <&tsens_backup>; |
||
899 | nvmem-cell-names = "calib", "calib_backup"; |
||
900 | interrupts = <0 178 0>; |
||
901 | #thermal-sensor-cells = <1>; |
||
902 | }; |
||
903 | |||
904 | tcsr: syscon@1a400000 { |
||
905 | compatible = "qcom,tcsr-ipq8064", "syscon"; |
||
906 | reg = <0x1a400000 0x100>; |
||
907 | }; |
||
908 | |||
909 | lcc: clock-controller@28000000 { |
||
910 | compatible = "qcom,lcc-ipq8064"; |
||
911 | reg = <0x28000000 0x1000>; |
||
912 | #clock-cells = <1>; |
||
913 | #reset-cells = <1>; |
||
914 | }; |
||
915 | |||
916 | sfpb_mutex_block: syscon@1200600 { |
||
917 | compatible = "syscon"; |
||
918 | reg = <0x01200600 0x100>; |
||
919 | }; |
||
920 | |||
921 | hs_phy_1: phy@100f8800 { |
||
922 | compatible = "qcom,dwc3-hs-usb-phy"; |
||
923 | reg = <0x100f8800 0x30>; |
||
924 | clocks = <&gcc USB30_1_UTMI_CLK>; |
||
925 | clock-names = "ref"; |
||
926 | #phy-cells = <0>; |
||
927 | |||
928 | status = "disabled"; |
||
929 | }; |
||
930 | |||
931 | ss_phy_1: phy@100f8830 { |
||
932 | compatible = "qcom,dwc3-ss-usb-phy"; |
||
933 | reg = <0x100f8830 0x30>; |
||
934 | clocks = <&gcc USB30_1_MASTER_CLK>; |
||
935 | clock-names = "ref"; |
||
936 | #phy-cells = <0>; |
||
937 | |||
938 | status = "disabled"; |
||
939 | }; |
||
940 | |||
941 | hs_phy_0: phy@110f8800 { |
||
942 | compatible = "qcom,dwc3-hs-usb-phy"; |
||
943 | reg = <0x110f8800 0x30>; |
||
944 | clocks = <&gcc USB30_0_UTMI_CLK>; |
||
945 | clock-names = "ref"; |
||
946 | #phy-cells = <0>; |
||
947 | |||
948 | status = "disabled"; |
||
949 | }; |
||
950 | |||
951 | ss_phy_0: phy@110f8830 { |
||
952 | compatible = "qcom,dwc3-ss-usb-phy"; |
||
953 | reg = <0x110f8830 0x30>; |
||
954 | clocks = <&gcc USB30_0_MASTER_CLK>; |
||
955 | clock-names = "ref"; |
||
956 | #phy-cells = <0>; |
||
957 | |||
958 | status = "disabled"; |
||
959 | }; |
||
960 | |||
961 | usb3_0: usb30@0 { |
||
962 | compatible = "qcom,dwc3"; |
||
963 | #address-cells = <1>; |
||
964 | #size-cells = <1>; |
||
965 | clocks = <&gcc USB30_0_MASTER_CLK>; |
||
966 | clock-names = "core"; |
||
967 | |||
968 | ranges; |
||
969 | |||
970 | resets = <&gcc USB30_0_MASTER_RESET>; |
||
971 | reset-names = "usb30_0_mstr_rst"; |
||
972 | |||
973 | status = "disabled"; |
||
974 | |||
975 | dwc3@11000000 { |
||
976 | compatible = "snps,dwc3"; |
||
977 | reg = <0x11000000 0xcd00>; |
||
978 | interrupts = <0 110 0x4>; |
||
979 | phys = <&hs_phy_0>, <&ss_phy_0>; |
||
980 | phy-names = "usb2-phy", "usb3-phy"; |
||
981 | dr_mode = "host"; |
||
982 | snps,dis_u3_susphy_quirk; |
||
983 | }; |
||
984 | }; |
||
985 | |||
986 | usb3_1: usb30@1 { |
||
987 | compatible = "qcom,dwc3"; |
||
988 | #address-cells = <1>; |
||
989 | #size-cells = <1>; |
||
990 | clocks = <&gcc USB30_1_MASTER_CLK>; |
||
991 | clock-names = "core"; |
||
992 | |||
993 | ranges; |
||
994 | |||
995 | resets = <&gcc USB30_1_MASTER_RESET>; |
||
996 | reset-names = "usb30_1_mstr_rst"; |
||
997 | |||
998 | status = "disabled"; |
||
999 | |||
1000 | dwc3@10000000 { |
||
1001 | compatible = "snps,dwc3"; |
||
1002 | reg = <0x10000000 0xcd00>; |
||
1003 | interrupts = <0 205 0x4>; |
||
1004 | phys = <&hs_phy_1>, <&ss_phy_1>; |
||
1005 | phy-names = "usb2-phy", "usb3-phy"; |
||
1006 | dr_mode = "host"; |
||
1007 | snps,dis_u3_susphy_quirk; |
||
1008 | }; |
||
1009 | }; |
||
1010 | |||
1011 | pcie0: pci@1b500000 { |
||
1012 | compatible = "qcom,pcie-ipq8064"; |
||
1013 | reg = <0x1b500000 0x1000 |
||
1014 | 0x1b502000 0x80 |
||
1015 | 0x1b600000 0x100 |
||
1016 | 0x0ff00000 0x100000>; |
||
1017 | reg-names = "dbi", "elbi", "parf", "config"; |
||
1018 | device_type = "pci"; |
||
1019 | linux,pci-domain = <0>; |
||
1020 | bus-range = <0x00 0xff>; |
||
1021 | num-lanes = <1>; |
||
1022 | #address-cells = <3>; |
||
1023 | #size-cells = <2>; |
||
1024 | |||
1025 | ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ |
||
1026 | 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ |
||
1027 | |||
1028 | interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>; |
||
1029 | interrupt-names = "msi"; |
||
1030 | #interrupt-cells = <1>; |
||
1031 | interrupt-map-mask = <0 0 0 0x7>; |
||
1032 | interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
||
1033 | <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
||
1034 | <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
||
1035 | <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
||
1036 | |||
1037 | clocks = <&gcc PCIE_A_CLK>, |
||
1038 | <&gcc PCIE_H_CLK>, |
||
1039 | <&gcc PCIE_PHY_CLK>, |
||
1040 | <&gcc PCIE_AUX_CLK>, |
||
1041 | <&gcc PCIE_ALT_REF_CLK>; |
||
1042 | clock-names = "core", "iface", "phy", "aux", "ref"; |
||
1043 | |||
1044 | assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; |
||
1045 | assigned-clock-rates = <100000000>; |
||
1046 | |||
1047 | resets = <&gcc PCIE_ACLK_RESET>, |
||
1048 | <&gcc PCIE_HCLK_RESET>, |
||
1049 | <&gcc PCIE_POR_RESET>, |
||
1050 | <&gcc PCIE_PCI_RESET>, |
||
1051 | <&gcc PCIE_PHY_RESET>, |
||
1052 | <&gcc PCIE_EXT_RESET>; |
||
1053 | reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; |
||
1054 | |||
1055 | pinctrl-0 = <&pcie0_pins>; |
||
1056 | pinctrl-names = "default"; |
||
1057 | |||
1058 | perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; |
||
1059 | |||
1060 | phy-tx0-term-offset = <7>; |
||
1061 | |||
1062 | status = "disabled"; |
||
1063 | }; |
||
1064 | |||
1065 | pcie1: pci@1b700000 { |
||
1066 | compatible = "qcom,pcie-ipq8064"; |
||
1067 | reg = <0x1b700000 0x1000 |
||
1068 | 0x1b702000 0x80 |
||
1069 | 0x1b800000 0x100 |
||
1070 | 0x31f00000 0x100000>; |
||
1071 | reg-names = "dbi", "elbi", "parf", "config"; |
||
1072 | device_type = "pci"; |
||
1073 | linux,pci-domain = <1>; |
||
1074 | bus-range = <0x00 0xff>; |
||
1075 | num-lanes = <1>; |
||
1076 | #address-cells = <3>; |
||
1077 | #size-cells = <2>; |
||
1078 | |||
1079 | ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ |
||
1080 | 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ |
||
1081 | |||
1082 | interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>; |
||
1083 | interrupt-names = "msi"; |
||
1084 | #interrupt-cells = <1>; |
||
1085 | interrupt-map-mask = <0 0 0 0x7>; |
||
1086 | interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
||
1087 | <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
||
1088 | <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
||
1089 | <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
||
1090 | |||
1091 | clocks = <&gcc PCIE_1_A_CLK>, |
||
1092 | <&gcc PCIE_1_H_CLK>, |
||
1093 | <&gcc PCIE_1_PHY_CLK>, |
||
1094 | <&gcc PCIE_1_AUX_CLK>, |
||
1095 | <&gcc PCIE_1_ALT_REF_CLK>; |
||
1096 | clock-names = "core", "iface", "phy", "aux", "ref"; |
||
1097 | |||
1098 | assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; |
||
1099 | assigned-clock-rates = <100000000>; |
||
1100 | |||
1101 | resets = <&gcc PCIE_1_ACLK_RESET>, |
||
1102 | <&gcc PCIE_1_HCLK_RESET>, |
||
1103 | <&gcc PCIE_1_POR_RESET>, |
||
1104 | <&gcc PCIE_1_PCI_RESET>, |
||
1105 | <&gcc PCIE_1_PHY_RESET>, |
||
1106 | <&gcc PCIE_1_EXT_RESET>; |
||
1107 | reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; |
||
1108 | |||
1109 | pinctrl-0 = <&pcie1_pins>; |
||
1110 | pinctrl-names = "default"; |
||
1111 | |||
1112 | perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; |
||
1113 | |||
1114 | phy-tx0-term-offset = <7>; |
||
1115 | |||
1116 | status = "disabled"; |
||
1117 | }; |
||
1118 | |||
1119 | pcie2: pci@1b900000 { |
||
1120 | compatible = "qcom,pcie-ipq8064"; |
||
1121 | reg = <0x1b900000 0x1000 |
||
1122 | 0x1b902000 0x80 |
||
1123 | 0x1ba00000 0x100 |
||
1124 | 0x35f00000 0x100000>; |
||
1125 | reg-names = "dbi", "elbi", "parf", "config"; |
||
1126 | device_type = "pci"; |
||
1127 | linux,pci-domain = <2>; |
||
1128 | bus-range = <0x00 0xff>; |
||
1129 | num-lanes = <1>; |
||
1130 | #address-cells = <3>; |
||
1131 | #size-cells = <2>; |
||
1132 | |||
1133 | ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ |
||
1134 | 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ |
||
1135 | |||
1136 | interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>; |
||
1137 | interrupt-names = "msi"; |
||
1138 | #interrupt-cells = <1>; |
||
1139 | interrupt-map-mask = <0 0 0 0x7>; |
||
1140 | interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
||
1141 | <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
||
1142 | <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
||
1143 | <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
||
1144 | |||
1145 | clocks = <&gcc PCIE_2_A_CLK>, |
||
1146 | <&gcc PCIE_2_H_CLK>, |
||
1147 | <&gcc PCIE_2_PHY_CLK>, |
||
1148 | <&gcc PCIE_2_AUX_CLK>, |
||
1149 | <&gcc PCIE_2_ALT_REF_CLK>; |
||
1150 | clock-names = "core", "iface", "phy", "aux", "ref"; |
||
1151 | |||
1152 | assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; |
||
1153 | assigned-clock-rates = <100000000>; |
||
1154 | |||
1155 | resets = <&gcc PCIE_2_ACLK_RESET>, |
||
1156 | <&gcc PCIE_2_HCLK_RESET>, |
||
1157 | <&gcc PCIE_2_POR_RESET>, |
||
1158 | <&gcc PCIE_2_PCI_RESET>, |
||
1159 | <&gcc PCIE_2_PHY_RESET>, |
||
1160 | <&gcc PCIE_2_EXT_RESET>; |
||
1161 | reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; |
||
1162 | |||
1163 | pinctrl-0 = <&pcie2_pins>; |
||
1164 | pinctrl-names = "default"; |
||
1165 | |||
1166 | perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; |
||
1167 | |||
1168 | phy-tx0-term-offset = <7>; |
||
1169 | |||
1170 | status = "disabled"; |
||
1171 | }; |
||
1172 | |||
1173 | adm_dma: dma@18300000 { |
||
1174 | compatible = "qcom,adm"; |
||
1175 | reg = <0x18300000 0x100000>; |
||
1176 | interrupts = <0 170 0>; |
||
1177 | #dma-cells = <1>; |
||
1178 | |||
1179 | clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; |
||
1180 | clock-names = "core", "iface"; |
||
1181 | |||
1182 | resets = <&gcc ADM0_RESET>, |
||
1183 | <&gcc ADM0_PBUS_RESET>, |
||
1184 | <&gcc ADM0_C0_RESET>, |
||
1185 | <&gcc ADM0_C1_RESET>, |
||
1186 | <&gcc ADM0_C2_RESET>; |
||
1187 | reset-names = "clk", "pbus", "c0", "c1", "c2"; |
||
1188 | qcom,ee = <0>; |
||
1189 | |||
1190 | status = "disabled"; |
||
1191 | }; |
||
1192 | |||
1193 | nand@1ac00000 { |
||
1194 | compatible = "qcom,ipq806x-nand"; |
||
1195 | reg = <0x1ac00000 0x800>; |
||
1196 | |||
1197 | clocks = <&gcc EBI2_CLK>, |
||
1198 | <&gcc EBI2_AON_CLK>; |
||
1199 | clock-names = "core", "aon"; |
||
1200 | |||
1201 | dmas = <&adm_dma 3>; |
||
1202 | dma-names = "rxtx"; |
||
1203 | qcom,cmd-crci = <15>; |
||
1204 | qcom,data-crci = <3>; |
||
1205 | |||
1206 | status = "disabled"; |
||
1207 | |||
1208 | #address-cells = <1>; |
||
1209 | #size-cells = <0>; |
||
1210 | }; |
||
1211 | |||
1212 | nss_common: syscon@03000000 { |
||
1213 | compatible = "syscon"; |
||
1214 | reg = <0x03000000 0x0000FFFF>; |
||
1215 | }; |
||
1216 | |||
1217 | qsgmii_csr: syscon@1bb00000 { |
||
1218 | compatible = "syscon"; |
||
1219 | reg = <0x1bb00000 0x000001FF>; |
||
1220 | }; |
||
1221 | |||
1222 | stmmac_axi_setup: stmmac-axi-config { |
||
1223 | snps,wr_osr_lmt = <7>; |
||
1224 | snps,rd_osr_lmt = <7>; |
||
1225 | snps,blen = <16 0 0 0 0 0 0>; |
||
1226 | }; |
||
1227 | |||
1228 | gmac0: ethernet@37000000 { |
||
1229 | device_type = "network"; |
||
1230 | compatible = "qcom,ipq806x-gmac"; |
||
1231 | reg = <0x37000000 0x200000>; |
||
1232 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
||
1233 | interrupt-names = "macirq"; |
||
1234 | |||
1235 | snps,axi-config = <&stmmac_axi_setup>; |
||
1236 | snps,pbl = <32>; |
||
1237 | snps,aal = <1>; |
||
1238 | |||
1239 | qcom,nss-common = <&nss_common>; |
||
1240 | qcom,qsgmii-csr = <&qsgmii_csr>; |
||
1241 | |||
1242 | clocks = <&gcc GMAC_CORE1_CLK>; |
||
1243 | clock-names = "stmmaceth"; |
||
1244 | |||
1245 | resets = <&gcc GMAC_CORE1_RESET>; |
||
1246 | reset-names = "stmmaceth"; |
||
1247 | |||
1248 | status = "disabled"; |
||
1249 | }; |
||
1250 | |||
1251 | gmac1: ethernet@37200000 { |
||
1252 | device_type = "network"; |
||
1253 | compatible = "qcom,ipq806x-gmac"; |
||
1254 | reg = <0x37200000 0x200000>; |
||
1255 | interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; |
||
1256 | interrupt-names = "macirq"; |
||
1257 | |||
1258 | snps,axi-config = <&stmmac_axi_setup>; |
||
1259 | snps,pbl = <32>; |
||
1260 | snps,aal = <1>; |
||
1261 | |||
1262 | qcom,nss-common = <&nss_common>; |
||
1263 | qcom,qsgmii-csr = <&qsgmii_csr>; |
||
1264 | |||
1265 | clocks = <&gcc GMAC_CORE2_CLK>; |
||
1266 | clock-names = "stmmaceth"; |
||
1267 | |||
1268 | resets = <&gcc GMAC_CORE2_RESET>; |
||
1269 | reset-names = "stmmaceth"; |
||
1270 | |||
1271 | status = "disabled"; |
||
1272 | }; |
||
1273 | |||
1274 | gmac2: ethernet@37400000 { |
||
1275 | device_type = "network"; |
||
1276 | compatible = "qcom,ipq806x-gmac"; |
||
1277 | reg = <0x37400000 0x200000>; |
||
1278 | interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
||
1279 | interrupt-names = "macirq"; |
||
1280 | |||
1281 | snps,axi-config = <&stmmac_axi_setup>; |
||
1282 | snps,pbl = <32>; |
||
1283 | snps,aal = <1>; |
||
1284 | |||
1285 | qcom,nss-common = <&nss_common>; |
||
1286 | qcom,qsgmii-csr = <&qsgmii_csr>; |
||
1287 | |||
1288 | clocks = <&gcc GMAC_CORE3_CLK>; |
||
1289 | clock-names = "stmmaceth"; |
||
1290 | |||
1291 | resets = <&gcc GMAC_CORE3_RESET>; |
||
1292 | reset-names = "stmmaceth"; |
||
1293 | |||
1294 | status = "disabled"; |
||
1295 | }; |
||
1296 | |||
1297 | gmac3: ethernet@37600000 { |
||
1298 | device_type = "network"; |
||
1299 | compatible = "qcom,ipq806x-gmac"; |
||
1300 | reg = <0x37600000 0x200000>; |
||
1301 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
||
1302 | interrupt-names = "macirq"; |
||
1303 | |||
1304 | snps,axi-config = <&stmmac_axi_setup>; |
||
1305 | snps,pbl = <32>; |
||
1306 | snps,aal = <1>; |
||
1307 | |||
1308 | qcom,nss-common = <&nss_common>; |
||
1309 | qcom,qsgmii-csr = <&qsgmii_csr>; |
||
1310 | |||
1311 | clocks = <&gcc GMAC_CORE4_CLK>; |
||
1312 | clock-names = "stmmaceth"; |
||
1313 | |||
1314 | resets = <&gcc GMAC_CORE4_RESET>; |
||
1315 | reset-names = "stmmaceth"; |
||
1316 | |||
1317 | status = "disabled"; |
||
1318 | }; |
||
1319 | |||
1320 | /* Temporary fixed regulator */ |
||
1321 | vsdcc_fixed: vsdcc-regulator { |
||
1322 | compatible = "regulator-fixed"; |
||
1323 | regulator-name = "SDCC Power"; |
||
1324 | regulator-min-microvolt = <3300000>; |
||
1325 | regulator-max-microvolt = <3300000>; |
||
1326 | regulator-always-on; |
||
1327 | }; |
||
1328 | |||
1329 | sdcc1bam:dma@12402000 { |
||
1330 | compatible = "qcom,bam-v1.3.0"; |
||
1331 | reg = <0x12402000 0x8000>; |
||
1332 | interrupts = <0 98 0>; |
||
1333 | clocks = <&gcc SDC1_H_CLK>; |
||
1334 | clock-names = "bam_clk"; |
||
1335 | #dma-cells = <1>; |
||
1336 | qcom,ee = <0>; |
||
1337 | }; |
||
1338 | |||
1339 | sdcc3bam:dma@12182000 { |
||
1340 | compatible = "qcom,bam-v1.3.0"; |
||
1341 | reg = <0x12182000 0x8000>; |
||
1342 | interrupts = <0 96 0>; |
||
1343 | clocks = <&gcc SDC3_H_CLK>; |
||
1344 | clock-names = "bam_clk"; |
||
1345 | #dma-cells = <1>; |
||
1346 | qcom,ee = <0>; |
||
1347 | }; |
||
1348 | |||
1349 | amba { |
||
1350 | compatible = "arm,amba-bus"; |
||
1351 | #address-cells = <1>; |
||
1352 | #size-cells = <1>; |
||
1353 | ranges; |
||
1354 | sdcc1: sdcc@12400000 { |
||
1355 | status = "disabled"; |
||
1356 | compatible = "arm,pl18x", "arm,primecell"; |
||
1357 | arm,primecell-periphid = <0x00051180>; |
||
1358 | reg = <0x12400000 0x2000>; |
||
1359 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
||
1360 | interrupt-names = "cmd_irq"; |
||
1361 | clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; |
||
1362 | clock-names = "mclk", "apb_pclk"; |
||
1363 | bus-width = <8>; |
||
1364 | max-frequency = <96000000>; |
||
1365 | non-removable; |
||
1366 | cap-sd-highspeed; |
||
1367 | cap-mmc-highspeed; |
||
1368 | vmmc-supply = <&vsdcc_fixed>; |
||
1369 | dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; |
||
1370 | dma-names = "tx", "rx"; |
||
1371 | }; |
||
1372 | |||
1373 | sdcc3: sdcc@12180000 { |
||
1374 | compatible = "arm,pl18x", "arm,primecell"; |
||
1375 | arm,primecell-periphid = <0x00051180>; |
||
1376 | status = "disabled"; |
||
1377 | reg = <0x12180000 0x2000>; |
||
1378 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
||
1379 | interrupt-names = "cmd_irq"; |
||
1380 | clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; |
||
1381 | clock-names = "mclk", "apb_pclk"; |
||
1382 | bus-width = <8>; |
||
1383 | cap-sd-highspeed; |
||
1384 | cap-mmc-highspeed; |
||
1385 | max-frequency = <192000000>; |
||
1386 | #mmc-ddr-1_8v; |
||
1387 | sd-uhs-sdr104; |
||
1388 | sd-uhs-ddr50; |
||
1389 | vqmmc-supply = <&vsdcc_fixed>; |
||
1390 | dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; |
||
1391 | dma-names = "tx", "rx"; |
||
1392 | }; |
||
1393 | }; |
||
1394 | }; |
||
1395 | |||
1396 | sfpb_mutex: sfpb-mutex { |
||
1397 | compatible = "qcom,sfpb-mutex"; |
||
1398 | syscon = <&sfpb_mutex_block 4 4>; |
||
1399 | |||
1400 | #hwlock-cells = <1>; |
||
1401 | }; |
||
1402 | |||
1403 | smem { |
||
1404 | compatible = "qcom,smem"; |
||
1405 | memory-region = <&smem>; |
||
1406 | hwlocks = <&sfpb_mutex 3>; |
||
1407 | }; |
||
1408 | }; |