OpenWrt – Blame information for rev 4

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4 office 1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 */
17  
18 #include "qcom-ipq4019.dtsi"
19 #include "qcom-ipq4019-bus.dtsi"
20 #include <dt-bindings/gpio/gpio.h>
21 #include <dt-bindings/input/input.h>
22 #include <dt-bindings/soc/qcom,tcsr.h>
23  
24 / {
25 model = "Netgear EX61X0v2";
26 compatible = "netgear,ex61x0v2", "qcom,ipq4019";
27  
28 soc {
29 mdio@90000 {
30 status = "okay";
31 };
32  
33 ess-psgmii@98000 {
34 status = "okay";
35 };
36  
37 tcsr@1949000 {
38 compatible = "qcom,tcsr";
39 reg = <0x1949000 0x100>;
40 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
41 };
42  
43 ess_tcsr@1953000 {
44 compatible = "qcom,tcsr";
45 reg = <0x1953000 0x1000>;
46 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
47 };
48  
49 tcsr@1957000 {
50 compatible = "qcom,tcsr";
51 reg = <0x1957000 0x100>;
52 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
53 };
54  
55 serial@78af000 {
56 pinctrl-0 = <&serial_pins>;
57 pinctrl-names = "default";
58 status = "okay";
59 };
60  
61 crypto@8e3a000 {
62 status = "okay";
63 };
64  
65 watchdog@b017000 {
66 status = "okay";
67 };
68  
69 ess-switch@c000000 {
70 status = "okay";
71 };
72  
73 edma@c080000 {
74 status = "okay";
75 qcom,num_gmac = <1>;
76 };
77 };
78  
79 aliases {
80 led-boot = &power_amber;
81 led-failsafe = &power_amber;
82 led-running = &power_green;
83 led-upgrade = &power_amber;
84 };
85  
86 gpio-keys {
87 compatible = "gpio-keys";
88  
89 wps {
90 label = "wps";
91 gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
92 linux,code = <KEY_WPS_BUTTON>;
93 };
94  
95 reset {
96 label = "reset";
97 gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
98 linux,code = <KEY_RESTART>;
99 };
100 };
101  
102 led_spi {
103 compatible = "spi-gpio";
104 #address-cells = <1>;
105 ranges;
106  
107 gpio-sck = <&tlmm 5 GPIO_ACTIVE_HIGH>;
108 gpio-mosi = <&tlmm 4 GPIO_ACTIVE_HIGH>;
109 num-chipselects = <0>;
110  
111 led_gpio: led_gpio@0 {
112 compatible = "fairchild,74hc595";
113 reg = <0>;
114 gpio-controller;
115 #gpio-cells = <2>;
116 registers-number = <1>;
117 spi-max-frequency = <1000000>;
118 };
119 };
120  
121 gpio-leds {
122 compatible = "gpio-leds";
123  
124 power_amber: power_amber {
125 label = "ex61x0v2:amber:power";
126 gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
127 };
128  
129 power_green: power_green {
130 label = "ex61x0v2:green:power";
131 gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
132 };
133  
134 right {
135 label = "ex61x0v2:blue:right";
136 gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
137 };
138  
139 left {
140 label = "ex61x0v2:blue:left";
141 gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
142 };
143  
144 client_green {
145 label = "ex61x0v2:green:client";
146 gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
147 };
148  
149 client_red {
150 label = "ex61x0v2:red:client";
151 gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
152 };
153  
154 router_green {
155 label = "ex61x0v2:green:router";
156 gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
157 };
158  
159 router_red {
160 label = "ex61x0v2:red:router";
161 gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
162 };
163  
164 wps {
165 label = "ex61x0v2:green:wps";
166 gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
167 };
168 };
169 };
170  
171 &tlmm {
172 serial_pins: serial_pinmux {
173 mux {
174 pins = "gpio60", "gpio61";
175 function = "blsp_uart0";
176 bias-disable;
177 };
178 };
179  
180 spi_0_pins: spi_0_pinmux {
181 pin {
182 function = "blsp_spi0";
183 pins = "gpio55", "gpio56", "gpio57";
184 drive-strength = <12>;
185 bias-disable;
186 };
187 pin_cs {
188 function = "gpio";
189 pins = "gpio54";
190 drive-strength = <2>;
191 bias-disable;
192 output-high;
193 };
194 };
195 };
196  
197 &spi_0 {
198 pinctrl-0 = <&spi_0_pins>;
199 pinctrl-names = "default";
200 status = "okay";
201 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
202  
203 mx25l12805d@0 {
204 compatible = "jedec,spi-nor";
205 reg = <0>;
206 spi-max-frequency = <24000000>;
207  
208 partitions {
209 compatible = "fixed-partitions";
210 #address-cells = <1>;
211 #size-cells = <1>;
212  
213 partition0@0 {
214 label = "SBL1";
215 reg = <0x00000000 0x00040000>;
216 read-only;
217 };
218  
219 partition1@40000 {
220 label = "MIBIB";
221 reg = <0x00040000 0x00020000>;
222 read-only;
223 };
224  
225 partition2@60000 {
226 label = "QSEE";
227 reg = <0x00060000 0x00060000>;
228 read-only;
229 };
230  
231 partition3@c0000 {
232 label = "CDT";
233 reg = <0x000c0000 0x00010000>;
234 read-only;
235 };
236  
237 partition4@d0000 {
238 label = "DDRPARAMS";
239 reg = <0x000d0000 0x00010000>;
240 read-only;
241 };
242  
243 partition5@E0000 {
244 label = "APPSBLENV";
245 reg = <0x000e0000 0x00010000>;
246 read-only;
247 };
248  
249 partition6@F0000 {
250 label = "APPSBL";
251 reg = <0x000f0000 0x00080000>;
252 read-only;
253 };
254  
255 partition7@170000 {
256 label = "ART";
257 reg = <0x00170000 0x00010000>;
258 read-only;
259 };
260  
261 partition8@180000 {
262 label = "config";
263 reg = <0x00180000 0x00010000>;
264 read-only;
265 };
266  
267 partition9@190000 {
268 label = "pot";
269 reg = <0x00190000 0x00010000>;
270 read-only;
271 };
272  
273 partition10@1a0000 {
274 label = "dnidata";
275 reg = <0x001a0000 0x00010000>;
276 read-only;
277 };
278  
279 partition11@1b0000 {
280 label = "firmware";
281 reg = <0x001b0000 0x00e10000>;
282 };
283  
284 partition12@fc0000 {
285 label = "language";
286 reg = <0x00fc0000 0x00040000>;
287 read-only;
288 };
289 };
290 };
291 };
292  
293 &blsp_dma {
294 status = "okay";
295 };
296  
297 &cryptobam {
298 status = "okay";
299 };
300  
301 &wifi0 {
302 status = "okay";
303 };
304  
305 &wifi1 {
306 status = "okay";
307 };