OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 57615e112aba6ae4c831d50e769c2c102f013686 Mon Sep 17 00:00:00 2001 |
2 | From: Linus Walleij <linus.walleij@linaro.org> |
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3 | Date: Tue, 7 Jun 2016 22:53:24 +0200 |
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4 | Subject: [PATCH 01/31] cache patch from OpenWRT |
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5 | |||
6 | --- |
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7 | arch/arm/mm/cache-fa.S | 17 ++++++++++++++++- |
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8 | 1 file changed, 16 insertions(+), 1 deletion(-) |
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9 | |||
10 | --- a/arch/arm/mm/cache-fa.S |
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11 | +++ b/arch/arm/mm/cache-fa.S |
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12 | @@ -24,7 +24,8 @@ |
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13 | /* |
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14 | * The size of one data cache line. |
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15 | */ |
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16 | -#define CACHE_DLINESIZE 16 |
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17 | +#define CACHE_DLINESIZE 16 |
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18 | +#define CACHE_DLINESHIFT 4 |
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19 | |||
20 | /* |
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21 | * The total size of the data cache. |
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22 | @@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area) |
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23 | * - start - virtual start address |
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24 | * - end - virtual end address |
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25 | */ |
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26 | +__flush_whole_dcache: |
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27 | + mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache |
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28 | + mov r0, #0 |
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29 | + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |
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30 | + mov pc, lr |
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31 | + |
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32 | fa_dma_inv_range: |
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33 | + sub r3, r1, r0 @ calculate total size |
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34 | + cmp r3, #CACHE_DLIMIT @ total size >= limit? |
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35 | + bhs __flush_whole_dcache @ flush whole D cache |
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36 | + |
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37 | tst r0, #CACHE_DLINESIZE - 1 |
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38 | bic r0, r0, #CACHE_DLINESIZE - 1 |
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39 | mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry |
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40 | @@ -193,6 +204,10 @@ fa_dma_inv_range: |
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41 | * - end - virtual end address |
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42 | */ |
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43 | fa_dma_clean_range: |
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44 | + sub r3, r1, r0 @ calculate total size |
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45 | + cmp r3, #CACHE_DLIMIT @ total size >= limit? |
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46 | + bhs __flush_whole_dcache @ flush whole D cache |
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47 | + |
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48 | bic r0, r0, #CACHE_DLINESIZE - 1 |
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49 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
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50 | add r0, r0, #CACHE_DLINESIZE |