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4 office 1 /*
2 * Cavium CNS3xxx I2C Host Controller
3 *
4 * Copyright 2010 Cavium Network
5 * Copyright 2012 Gateworks Corporation
6 * Chris Lang <clang@gateworks.com>
7 * Tim Harvey <tharvey@gateworks.com>
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 */
13  
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <asm/io.h>
19 #include <linux/wait.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/i2c.h>
23 #include <linux/slab.h>
24 #include <linux/clk.h>
25  
26 /*
27 * We need the memory map
28 */
29  
30 #define I2C_MEM_MAP_ADDR(x) (i2c->base + x)
31 #define I2C_MEM_MAP_VALUE(x) (*((unsigned int volatile*)I2C_MEM_MAP_ADDR(x)))
32  
33 #define I2C_CONTROLLER_REG I2C_MEM_MAP_VALUE(0x00)
34 #define I2C_TIME_OUT_REG I2C_MEM_MAP_VALUE(0x04)
35 #define I2C_SLAVE_ADDRESS_REG I2C_MEM_MAP_VALUE(0x08)
36 #define I2C_WRITE_DATA_REG I2C_MEM_MAP_VALUE(0x0C)
37 #define I2C_READ_DATA_REG I2C_MEM_MAP_VALUE(0x10)
38 #define I2C_INTERRUPT_STATUS_REG I2C_MEM_MAP_VALUE(0x14)
39 #define I2C_INTERRUPT_ENABLE_REG I2C_MEM_MAP_VALUE(0x18)
40 #define I2C_TWI_OUT_DLY_REG I2C_MEM_MAP_VALUE(0x1C)
41  
42 #define I2C_BUS_ERROR_FLAG (0x1)
43 #define I2C_ACTION_DONE_FLAG (0x2)
44  
45 #define CNS3xxx_I2C_ENABLE() (I2C_CONTROLLER_REG) |= ((unsigned int)0x1 << 31)
46 #define CNS3xxx_I2C_DISABLE() (I2C_CONTROLLER_REG) &= ~((unsigned int)0x1 << 31)
47 #define CNS3xxx_I2C_ENABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) |= 0x03
48 #define CNS3xxx_I2C_DISABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) &= 0xfc
49  
50 #define TWI_TIMEOUT (10*HZ)
51 #define I2C_100KHZ 100000
52 #define I2C_200KHZ 200000
53 #define I2C_300KHZ 300000
54 #define I2C_400KHZ 400000
55  
56 #define CNS3xxx_I2C_CLK I2C_100KHZ
57  
58 #define STATE_DONE 1
59 #define STATE_ERROR 2
60  
61 struct cns3xxx_i2c {
62 struct device *dev;
63 void __iomem *base; /* virtual */
64 wait_queue_head_t wait;
65 struct i2c_adapter adap;
66 struct i2c_msg *msg;
67 u8 state; /* see STATE_ */
68 u8 error; /* see TWI_STATUS register */
69 int rd_wr_len;
70 u8 *buf;
71 };
72  
73 static u32 cns3xxx_i2c_func(struct i2c_adapter *adap)
74 {
75 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
76 }
77  
78 static int
79 cns3xxx_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg)
80 {
81 struct cns3xxx_i2c *i2c = i2c_get_adapdata(adap);
82 int i, j;
83 u8 buf[1] = { 0 };
84  
85 if (msg->len == 0) {
86 /*
87 * We are probably doing a probe for a device here,
88 * so set the length to one, and data to 0
89 */
90 msg->len = 1;
91 i2c->buf = buf;
92 } else {
93 i2c->buf = msg->buf;
94 }
95  
96 if (msg->flags & I2C_M_TEN) {
97 printk
98 ("%s:%d: Presently the driver does not handle extended addressing\n",
99 __FUNCTION__, __LINE__);
100 return -EINVAL;
101 }
102 i2c->msg = msg;
103  
104 for (i = 0; i < msg->len; i++) {
105 if (msg->len - i >= 4)
106 i2c->rd_wr_len = 3;
107 else
108 i2c->rd_wr_len = msg->len - i - 1;
109  
110 // Set Data Width and TWI_EN
111 I2C_CONTROLLER_REG = 0x80000000 | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len);
112  
113 // Clear Write Reg
114 I2C_WRITE_DATA_REG = 0;
115  
116 // Set the slave address
117 I2C_SLAVE_ADDRESS_REG = (msg->addr << 1);
118  
119 // Are we Writing
120 if (!(msg->flags & I2C_M_RD)) {
121 I2C_CONTROLLER_REG |= (1 << 4);
122 if (i != 0) {
123 /*
124 * We need to set the address in the first byte.
125 * The base address is going to be in buf[0] and then
126 * it needs to be incremented by i - 1.
127 */
128 i2c->buf--;
129 *i2c->buf = buf[0] + i - 1;
130  
131 if (i2c->rd_wr_len < 3) {
132 i += i2c->rd_wr_len;
133 i2c->rd_wr_len++;
134 I2C_CONTROLLER_REG = 0x80000000 | (1 << 4) | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len);
135 } else {
136 i += i2c->rd_wr_len - 1;
137 }
138 } else {
139 i += i2c->rd_wr_len;
140 buf[0] = *i2c->buf;
141 }
142 for (j = 0; j <= i2c->rd_wr_len; j++) {
143 I2C_WRITE_DATA_REG |= ((*i2c->buf++) << (8 * j));
144 }
145 } else {
146 i += i2c->rd_wr_len;
147 }
148  
149 // Start the Transfer
150 i2c->state = 0; // Clear out the State
151 i2c->error = 0;
152 I2C_CONTROLLER_REG |= (1 << 6);
153  
154 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
155 (i2c->state == STATE_DONE), TWI_TIMEOUT)) {
156 if (i2c->state == STATE_ERROR) {
157 dev_dbg(i2c->dev, "controller error: 0x%2x", i2c->error);
158 return -EAGAIN; // try again
159 }
160 } else {
161 dev_err(i2c->dev, "controller timed out "
162 "waiting for start condition to finish\n");
163 return -ETIMEDOUT;
164 }
165 }
166 return 0;
167 }
168  
169 static int
170 cns3xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
171 {
172 int i;
173 int ret;
174 for (i = 0; i < num; i++)
175 {
176 ret = cns3xxx_i2c_xfer_msg(adap, &msgs[i]);
177 if (ret < 0) {
178 return ret;
179 }
180 }
181 return num;
182 }
183  
184  
185 static struct i2c_algorithm cns3xxx_i2c_algo = {
186 .master_xfer = cns3xxx_i2c_xfer,
187 .functionality = cns3xxx_i2c_func,
188 };
189  
190 static struct i2c_adapter cns3xxx_i2c_adapter = {
191 .owner = THIS_MODULE,
192 .algo = &cns3xxx_i2c_algo,
193 .algo_data = NULL,
194 .nr = 0,
195 .name = "CNS3xxx I2C 0",
196 .retries = 5,
197 };
198  
199 static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c)
200 {
201 struct clk *clk;
202  
203 clk = devm_clk_get(i2c->dev, "cpu");
204 if (WARN_ON(!clk))
205 return;
206  
207 /* Disable the I2C */
208 I2C_CONTROLLER_REG = 0; /* Disabled the I2C */
209  
210 /* Check the Reg Dump when testing */
211 I2C_TIME_OUT_REG =
212 (((((clk_get_rate(clk) / (2 * CNS3xxx_I2C_CLK)) -
213 1) & 0x3FF) << 8) | (1 << 7) | 0x7F);
214 I2C_TWI_OUT_DLY_REG |= 0x3;
215  
216 /* Enable The Interrupt */
217 CNS3xxx_I2C_ENABLE_INTR();
218  
219 /* Clear Interrupt Status (0x2 | 0x1) */
220 I2C_INTERRUPT_STATUS_REG |= (I2C_ACTION_DONE_FLAG | I2C_BUS_ERROR_FLAG);
221  
222 /* Enable the I2C Controller */
223 CNS3xxx_I2C_ENABLE();
224 }
225  
226 static irqreturn_t cns3xxx_i2c_isr(int irq, void *dev_id)
227 {
228 struct cns3xxx_i2c *i2c = dev_id;
229 int i;
230 uint32_t stat = I2C_INTERRUPT_STATUS_REG;
231  
232 /* Clear Interrupt */
233 I2C_INTERRUPT_STATUS_REG |= 0x1;
234  
235 if (stat & I2C_BUS_ERROR_FLAG) {
236 i2c->state = STATE_ERROR;
237 i2c->error = (I2C_INTERRUPT_STATUS_REG & 0xff00)>>8;
238 } else {
239 if (i2c->msg->flags & I2C_M_RD) {
240 for (i = 0; i <= i2c->rd_wr_len; i++)
241 {
242 *i2c->buf++ = ((I2C_READ_DATA_REG >> (8 * i)) & 0xff);
243 }
244 }
245 i2c->state = STATE_DONE;
246 }
247 wake_up(&i2c->wait);
248 return IRQ_HANDLED;
249 }
250  
251 static int cns3xxx_i2c_probe(struct platform_device *pdev)
252 {
253 struct cns3xxx_i2c *i2c;
254 struct resource *res, *res2;
255 int ret;
256  
257 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
258 if (!res) {
259 printk("%s: IORESOURCE_MEM not defined \n", __FUNCTION__);
260 return -ENODEV;
261 }
262  
263 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
264 if (!res2) {
265 printk("%s: IORESOURCE_IRQ not defined \n", __FUNCTION__);
266 return -ENODEV;
267 }
268  
269 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
270 if (!i2c)
271 return -ENOMEM;
272  
273 if (!request_mem_region(res->start, res->end - res->start + 1,
274 pdev->name)) {
275 dev_err(&pdev->dev, "Memory region busy\n");
276 ret = -EBUSY;
277 goto request_mem_failed;
278 }
279  
280 i2c->dev = &pdev->dev;
281 i2c->base = ioremap(res->start, res->end - res->start + 1);
282 if (!i2c->base) {
283 dev_err(&pdev->dev, "Unable to map registers\n");
284 ret = -EIO;
285 goto map_failed;
286 }
287  
288 cns3xxx_i2c_adapter_init(i2c);
289  
290 init_waitqueue_head(&i2c->wait);
291 ret = request_irq(res2->start, cns3xxx_i2c_isr, 0, pdev->name, i2c);
292 if (ret) {
293 dev_err(&pdev->dev, "Cannot claim IRQ\n");
294 goto request_irq_failed;
295 }
296  
297 platform_set_drvdata(pdev, i2c);
298 i2c->adap = cns3xxx_i2c_adapter;
299 i2c_set_adapdata(&i2c->adap, i2c);
300 i2c->adap.dev.parent = &pdev->dev;
301  
302 /* add i2c adapter to i2c tree */
303 ret = i2c_add_numbered_adapter(&i2c->adap);
304 if (ret) {
305 dev_err(&pdev->dev, "Failed to add adapter\n");
306 goto add_adapter_failed;
307 }
308  
309 return 0;
310  
311 add_adapter_failed:
312 free_irq(res2->start, i2c);
313 request_irq_failed:
314 iounmap(i2c->base);
315 map_failed:
316 release_mem_region(res->start, res->end - res->start + 1);
317 request_mem_failed:
318 kfree(i2c);
319  
320 return ret;
321 }
322  
323 static int cns3xxx_i2c_remove(struct platform_device *pdev)
324 {
325 struct cns3xxx_i2c *i2c = platform_get_drvdata(pdev);
326 struct resource *res;
327  
328 /* disable i2c logic */
329 CNS3xxx_I2C_DISABLE_INTR();
330 CNS3xxx_I2C_DISABLE();
331 /* remove adapter & data */
332 i2c_del_adapter(&i2c->adap);
333 platform_set_drvdata(pdev, NULL);
334  
335 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
336 if (res)
337 free_irq(res->start, i2c);
338  
339 iounmap(i2c->base);
340  
341 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
342 if (res)
343 release_mem_region(res->start, res->end - res->start + 1);
344  
345 kfree(i2c);
346  
347 return 0;
348 }
349  
350 static struct platform_driver cns3xxx_i2c_driver = {
351 .probe = cns3xxx_i2c_probe,
352 .remove = cns3xxx_i2c_remove,
353 .driver = {
354 .owner = THIS_MODULE,
355 .name = "cns3xxx-i2c",
356 },
357 };
358  
359 static int __init cns3xxx_i2c_init(void)
360 {
361 return platform_driver_register(&cns3xxx_i2c_driver);
362 }
363  
364 static void __exit cns3xxx_i2c_exit(void)
365 {
366 platform_driver_unregister(&cns3xxx_i2c_driver);
367 }
368  
369 module_init(cns3xxx_i2c_init);
370 module_exit(cns3xxx_i2c_exit);
371  
372 MODULE_AUTHOR("Cavium Networks");
373 MODULE_DESCRIPTION("Cavium CNS3XXX I2C Controller");
374 MODULE_LICENSE("GPL");