OpenWrt – Blame information for rev 4

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4 office 1 /*
2 * Copyright (C) 2012 Gateworks Corporation
3 * Chris Lang <clang@gateworks.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9 #include <linux/linkage.h>
10 #include <asm/assembler.h>
11 #include <asm/asm-offsets.h>
12  
13 #define D_CACHE_LINE_SIZE 32
14  
15 .text
16  
17 /*
18 * R8 - DMA Start Address
19 * R9 - DMA Length
20 * R10 - DMA Direction
21 * R11 - DMA type
22 * R12 - fiq_buffer Address
23 */
24  
25 .global cns3xxx_fiq_end
26 ENTRY(cns3xxx_fiq_start)
27 str r8, [r13]
28  
29 ldmia r12, {r8, r9, r10}
30 and r11, r10, #0x3000000
31 and r10, r10, #0xff
32  
33 teq r11, #0x1000000
34 beq cns3xxx_dma_map_area
35 teq r11, #0x2000000
36 beq cns3xxx_dma_unmap_area
37 /* fall through */
38 cns3xxx_dma_flush_range:
39 bic r8, r8, #D_CACHE_LINE_SIZE - 1
40 1:
41 mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line
42 add r8, r8, #D_CACHE_LINE_SIZE
43 cmp r8, r9
44 blo 1b
45 /* fall through */
46 cns3xxx_fiq_exit:
47 mov r8, #0
48 str r8, [r12, #8]
49 mcr p15, 0, r8, c7, c10, 4 @ drain write buffer
50 subs pc, lr, #4
51  
52 cns3xxx_dma_map_area:
53 add r9, r9, r8
54 teq r10, #DMA_FROM_DEVICE
55 beq cns3xxx_dma_inv_range
56 teq r10, #DMA_TO_DEVICE
57 bne cns3xxx_dma_flush_range
58 /* fall through */
59 cns3xxx_dma_clean_range:
60 bic r8, r8, #D_CACHE_LINE_SIZE - 1
61 1:
62 mcr p15, 0, r8, c7, c10, 1 @ clean D line
63 add r8, r8, #D_CACHE_LINE_SIZE
64 cmp r8, r9
65 blo 1b
66 b cns3xxx_fiq_exit
67  
68 cns3xxx_dma_unmap_area:
69 add r9, r9, r8
70 teq r10, #DMA_TO_DEVICE
71 beq cns3xxx_fiq_exit
72 /* fall through */
73 cns3xxx_dma_inv_range:
74 tst r8, #D_CACHE_LINE_SIZE - 1
75 bic r8, r8, #D_CACHE_LINE_SIZE - 1
76 mcrne p15, 0, r8, c7, c10, 1 @ clean D line
77 tst r9, #D_CACHE_LINE_SIZE - 1
78 bic r9, r9, #D_CACHE_LINE_SIZE - 1
79 mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line
80 1:
81 mcr p15, 0, r8, c7, c6, 1 @ invalidate D line
82 add r8, r8, #D_CACHE_LINE_SIZE
83 cmp r8, r9
84 blo 1b
85 b cns3xxx_fiq_exit
86  
87 cns3xxx_fiq_end: