OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 1cacd0f7b0d35f8e3d3f8a69ecb3b5e436d6b9e8 Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jogo@openwrt.org> |
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3 | Date: Sun, 22 Dec 2013 13:25:25 +0100 |
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4 | Subject: [PATCH 52/56] MIPS: BCM63XX: fixup mapped SPI flash access on boot |
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5 | |||
6 | Some bootloaders leave the flash access in an invalid state with dual |
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7 | read enabled; fix it by disabling it and falling back to simple fast |
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8 | reads. |
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9 | |||
10 | Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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11 | --- |
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12 | arch/mips/bcm63xx/dev-flash.c | 51 ++++++++++++++++++++++++++++++++++++ |
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13 | 1 file changed, 51 insertions(+) |
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14 | |||
15 | --- a/arch/mips/bcm63xx/dev-flash.c |
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16 | +++ b/arch/mips/bcm63xx/dev-flash.c |
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17 | @@ -16,6 +16,7 @@ |
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18 | #include <linux/mtd/mtd.h> |
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19 | #include <linux/mtd/partitions.h> |
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20 | #include <linux/mtd/physmap.h> |
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21 | +#include <linux/mtd/spi-nor.h> |
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22 | |||
23 | #include <bcm63xx_cpu.h> |
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24 | #include <bcm63xx_dev_flash.h> |
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25 | @@ -110,9 +111,59 @@ static int __init bcm63xx_detect_flash_t |
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26 | } |
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27 | } |
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28 | |||
29 | +#define HSSPI_FLASH_CTRL_REG 0x14 |
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30 | +#define FLASH_CTRL_READ_OPCODE_MASK 0xff |
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31 | +#define FLASH_CTRL_ADDR_BYTES_MASK (0x3 << 8) |
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32 | +#define FLASH_CTRL_ADDR_BYTES_2 (0 << 8) |
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33 | +#define FLASH_CTRL_ADDR_BYTES_3 (1 << 8) |
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34 | +#define FLASH_CTRL_ADDR_BYTES_4 (2 << 8) |
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35 | +#define FLASH_CTRL_DUMMY_BYTES_SHIFT 10 |
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36 | +#define FLASH_CTRL_DUMMY_BYTES_MASK (0x3 << FLASH_CTRL_DUMMY_BYTES_SHIFT) |
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37 | +#define FLASH_CTRL_MB_EN (1 << 23) |
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38 | + |
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39 | void __init bcm63xx_flash_detect(void) |
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40 | { |
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41 | flash_type = bcm63xx_detect_flash_type(); |
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42 | + |
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43 | + /* ensure flash mapping has sane values */ |
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44 | + if (flash_type == BCM63XX_FLASH_TYPE_SERIAL && |
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45 | + (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || |
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46 | + BCMCPU_IS_63268())) { |
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47 | + u32 val = bcm_rset_readl(RSET_HSSPI, HSSPI_FLASH_CTRL_REG); |
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48 | + |
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49 | + if (val & FLASH_CTRL_MB_EN) { |
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50 | + /* cfe might configure non working dual-io mode */ |
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51 | + val &= ~FLASH_CTRL_MB_EN; |
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52 | + val &= ~FLASH_CTRL_READ_OPCODE_MASK; |
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53 | + val &= ~FLASH_CTRL_DUMMY_BYTES_MASK; |
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54 | + val |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT; |
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55 | + |
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56 | + switch (val & FLASH_CTRL_ADDR_BYTES_MASK) { |
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57 | + case FLASH_CTRL_ADDR_BYTES_3: |
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58 | + val |= SPINOR_OP_READ_FAST; |
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59 | + break; |
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60 | + case FLASH_CTRL_ADDR_BYTES_4: |
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61 | + val |= SPINOR_OP_READ_FAST_4B; |
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62 | + break; |
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63 | + case FLASH_CTRL_ADDR_BYTES_2: |
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64 | + default: |
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65 | + pr_warn("unsupported address byte mode (%x), not fixing up\n", |
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66 | + val & FLASH_CTRL_ADDR_BYTES_MASK); |
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67 | + return; |
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68 | + } |
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69 | + } else { |
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70 | + /* ensure dummy bytes is set to 1 for _FAST reads */ |
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71 | + u8 cmd = val & FLASH_CTRL_READ_OPCODE_MASK; |
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72 | + |
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73 | + if (cmd != SPINOR_OP_READ_FAST && cmd != SPINOR_OP_READ_FAST_4B) |
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74 | + return; |
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75 | + |
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76 | + val &= ~FLASH_CTRL_DUMMY_BYTES_MASK; |
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77 | + val |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT; |
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78 | + } |
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79 | + |
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80 | + bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG); |
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81 | + } |
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82 | } |
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83 | |||
84 | int __init bcm63xx_flash_register(void) |