OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | / { |
2 | #address-cells = <1>; |
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3 | #size-cells = <1>; |
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4 | compatible = "brcm,bcm6348"; |
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5 | |||
6 | aliases { |
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7 | pflash = &pflash; |
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8 | pinctrl = &pinctrl; |
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9 | serial0 = &uart0; |
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10 | spi0 = &lsspi; |
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11 | }; |
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12 | |||
13 | cpus { |
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14 | #address-cells = <1>; |
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15 | #size-cells = <0>; |
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16 | |||
17 | cpu@0 { |
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18 | compatible = "brcm,bmips3300", "mips,mips4Kc"; |
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19 | device_type = "cpu"; |
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20 | reg = <0>; |
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21 | }; |
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22 | }; |
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23 | |||
24 | cpu_intc: interrupt-controller { |
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25 | #address-cells = <0>; |
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26 | compatible = "mti,cpu-interrupt-controller"; |
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27 | |||
28 | interrupt-controller; |
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29 | #interrupt-cells = <1>; |
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30 | }; |
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31 | |||
32 | memory { device_type = "memory"; reg = <0 0>; }; |
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33 | |||
34 | pflash: nor@1fc00000 { |
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35 | compatible = "cfi-flash"; |
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36 | reg = <0x1fc00000 0x400000>; |
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37 | bank-width = <2>; |
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38 | #address-cells = <1>; |
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39 | #size-cells = <1>; |
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40 | |||
41 | status = "disabled"; |
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42 | }; |
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43 | |||
44 | ubus@fff00000 { |
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45 | #address-cells = <1>; |
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46 | #size-cells = <1>; |
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47 | ranges; |
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48 | compatible = "simple-bus"; |
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49 | interrupt-parent = <&periph_intc>; |
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50 | |||
51 | periph_intc: interrupt-controller@fffe000c { |
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52 | compatible = "brcm,bcm6345-l1-intc"; |
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53 | reg = <0xfffe000c 0x8>; |
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54 | |||
55 | interrupt-controller; |
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56 | #interrupt-cells = <1>; |
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57 | |||
58 | interrupt-parent = <&cpu_intc>; |
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59 | interrupts = <2>; |
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60 | }; |
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61 | |||
62 | ext_intc: interrupt-controller@fffe0014 { |
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63 | compatible = "brcm,bcm6345-ext-intc"; |
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64 | reg = <0xfffe0014 0x4>; |
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65 | |||
66 | interrupt-controller; |
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67 | #interrupt-cells = <2>; |
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68 | |||
69 | interrupt-parent = <&cpu_intc>; |
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70 | interrupts = <3>, <4>, <5>, <6>; |
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71 | |||
72 | brcm,field-width = <5>; |
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73 | }; |
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74 | |||
75 | pinctrl: pin-controller@fffe0400 { |
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76 | compatible = "brcm,bcm6348-pinctrl"; |
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77 | reg = <0xfffe0400 0x8>, |
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78 | <0xfffe0408 0x8>, |
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79 | <0xfffe0418 0x4>; |
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80 | reg-names = "dirout", "dat", "mode"; |
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81 | |||
82 | gpio-controller; |
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83 | #gpio-cells = <2>; |
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84 | |||
85 | interrupt-parent = <&ext_intc>; |
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86 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>; |
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87 | interrupt-names = "gpio32", "gpio33", "gpio34", "gpio35"; |
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88 | |||
89 | pinctrl_ext_ephy: ext_ephy { |
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90 | function = "ext_ephy"; |
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91 | groups = "group1", "group4"; |
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92 | }; |
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93 | |||
94 | pinctrl_mii_snoop: mii_snoop { |
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95 | function = "ext_ephy"; |
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96 | groups = "group1", "group4"; |
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97 | }; |
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98 | |||
99 | pinctrl_legacy_led: legacy_led { |
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100 | function = "legacy_led"; |
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101 | groups = "group4"; |
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102 | }; |
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103 | |||
104 | pinctrl_mii_pccard: mii_pccard { |
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105 | function = "mii_pccard"; |
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106 | groups = "group1"; |
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107 | }; |
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108 | |||
109 | pinctrl_pci: pci { |
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110 | function = "pci"; |
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111 | groups = "group2"; |
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112 | }; |
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113 | |||
114 | pinctrl_spi_master_uart: spi_master_uart { |
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115 | function = "spi_master_uart"; |
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116 | groups = "group1"; |
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117 | }; |
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118 | |||
119 | pinctrl_ext_mii: ext_mii { |
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120 | function = "ext_mii"; |
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121 | groups = "group0", "group3"; |
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122 | }; |
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123 | |||
124 | pinctrl_utopia: utopia { |
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125 | function = "utopia"; |
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126 | groups = "group0", "group1", "group3"; |
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127 | }; |
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128 | }; |
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129 | |||
130 | uart0: serial@fffe0300 { |
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131 | compatible = "brcm,bcm6345-uart"; |
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132 | reg = <0xfffe0300 0x18>; |
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133 | |||
134 | interrupt-parent = <&periph_intc>; |
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135 | interrupts = <2>; |
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136 | |||
137 | /* clocks = <&periph_clk>; */ |
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138 | /* clock-names = "refclk"; */ |
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139 | |||
140 | status = "disabled"; |
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141 | }; |
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142 | |||
143 | lsspi: spi@fffe0c00 { |
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144 | #address-cells = <1>; |
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145 | #size-cells = <0>; |
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146 | compatible = "brcm,bcm6348-spi"; |
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147 | reg = <0xfffe0c00 0x40>; |
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148 | interrupts = <1>; |
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149 | /* clocks = <&clkctl 9>; */ |
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150 | |||
151 | }; |
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152 | }; |
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153 | }; |