OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 01ffdd37dcd3c9e526ac9135bfd289beb45f84a0 Mon Sep 17 00:00:00 2001 |
2 | From: Eric Anholt <eric@anholt.net> |
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3 | Date: Wed, 10 Feb 2016 16:17:29 -0800 |
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4 | Subject: [PATCH] drm/vc4: Add support for feeding DSI encoders from the pixel |
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5 | valve. |
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6 | |||
7 | We have to set a different pixel format, which tells the hardware to |
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8 | use the pix_width field that's fed in sideband from the DSI encoder to |
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9 | divide the "pixel" clock. |
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10 | |||
11 | Signed-off-by: Eric Anholt <eric@anholt.net> |
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12 | --- |
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13 | drivers/gpu/drm/vc4/vc4_crtc.c | 33 +++++++++++++++++++-------------- |
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14 | drivers/gpu/drm/vc4/vc4_regs.h | 2 ++ |
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15 | 2 files changed, 21 insertions(+), 14 deletions(-) |
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16 | |||
17 | --- a/drivers/gpu/drm/vc4/vc4_crtc.c |
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18 | +++ b/drivers/gpu/drm/vc4/vc4_crtc.c |
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19 | @@ -352,38 +352,40 @@ static u32 vc4_get_fifo_full_level(u32 f |
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20 | } |
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21 | |||
22 | /* |
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23 | - * Returns the clock select bit for the connector attached to the |
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24 | - * CRTC. |
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25 | + * Returns the encoder attached to the CRTC. |
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26 | + * |
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27 | + * VC4 can only scan out to one encoder at a time, while the DRM core |
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28 | + * allows drivers to push pixels to more than one encoder from the |
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29 | + * same CRTC. |
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30 | */ |
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31 | -static int vc4_get_clock_select(struct drm_crtc *crtc) |
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32 | +static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) |
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33 | { |
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34 | struct drm_connector *connector; |
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35 | |||
36 | drm_for_each_connector(connector, crtc->dev) { |
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37 | if (connector->state->crtc == crtc) { |
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38 | - struct drm_encoder *encoder = connector->encoder; |
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39 | - struct vc4_encoder *vc4_encoder = |
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40 | - to_vc4_encoder(encoder); |
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41 | - |
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42 | - return vc4_encoder->clock_select; |
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43 | + return connector->encoder; |
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44 | } |
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45 | } |
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46 | |||
47 | - return -1; |
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48 | + return NULL; |
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49 | } |
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50 | |||
51 | static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) |
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52 | { |
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53 | struct drm_device *dev = crtc->dev; |
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54 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
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55 | + struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); |
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56 | + struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); |
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57 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
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58 | struct drm_crtc_state *state = crtc->state; |
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59 | struct drm_display_mode *mode = &state->adjusted_mode; |
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60 | bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; |
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61 | u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; |
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62 | - u32 format = PV_CONTROL_FORMAT_24; |
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63 | + bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || |
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64 | + vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); |
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65 | + u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; |
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66 | bool debug_dump_regs = false; |
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67 | - int clock_select = vc4_get_clock_select(crtc); |
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68 | |||
69 | if (debug_dump_regs) { |
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70 | DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); |
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71 | @@ -439,17 +441,19 @@ static void vc4_crtc_mode_set_nofb(struc |
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72 | */ |
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73 | CRTC_WRITE(PV_V_CONTROL, |
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74 | PV_VCONTROL_CONTINUOUS | |
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75 | + (is_dsi ? PV_VCONTROL_DSI : 0) | |
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76 | PV_VCONTROL_INTERLACE | |
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77 | VC4_SET_FIELD(mode->htotal * pixel_rep / 2, |
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78 | PV_VCONTROL_ODD_DELAY)); |
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79 | CRTC_WRITE(PV_VSYNCD_EVEN, 0); |
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80 | } else { |
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81 | - CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS); |
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82 | + CRTC_WRITE(PV_V_CONTROL, |
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83 | + PV_VCONTROL_CONTINUOUS | |
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84 | + (is_dsi ? PV_VCONTROL_DSI : 0)); |
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85 | } |
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86 | |||
87 | CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); |
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88 | |||
89 | - |
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90 | CRTC_WRITE(PV_CONTROL, |
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91 | VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | |
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92 | VC4_SET_FIELD(vc4_get_fifo_full_level(format), |
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93 | @@ -458,7 +462,8 @@ static void vc4_crtc_mode_set_nofb(struc |
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94 | PV_CONTROL_CLR_AT_START | |
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95 | PV_CONTROL_TRIGGER_UNDERFLOW | |
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96 | PV_CONTROL_WAIT_HSTART | |
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97 | - VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) | |
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98 | + VC4_SET_FIELD(vc4_encoder->clock_select, |
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99 | + PV_CONTROL_CLK_SELECT) | |
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100 | PV_CONTROL_FIFO_CLR | |
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101 | PV_CONTROL_EN); |
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102 | |||
103 | --- a/drivers/gpu/drm/vc4/vc4_regs.h |
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104 | +++ b/drivers/gpu/drm/vc4/vc4_regs.h |
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105 | @@ -190,6 +190,8 @@ |
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106 | # define PV_VCONTROL_ODD_DELAY_SHIFT 6 |
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107 | # define PV_VCONTROL_ODD_FIRST BIT(5) |
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108 | # define PV_VCONTROL_INTERLACE BIT(4) |
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109 | +# define PV_VCONTROL_DSI BIT(3) |
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110 | +# define PV_VCONTROL_COMMAND BIT(2) |
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111 | # define PV_VCONTROL_CONTINUOUS BIT(1) |
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112 | # define PV_VCONTROL_VIDEN BIT(0) |
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113 |