OpenWrt – Blame information for rev 4
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4 | office | 1 | From 999db52750c062708532e1357ea3942cc619794f Mon Sep 17 00:00:00 2001 |
2 | From: Eric Anholt <eric@anholt.net> |
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3 | Date: Wed, 18 Jan 2017 07:31:55 +1100 |
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4 | Subject: [PATCH] clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL |
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5 | dividers. |
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6 | |||
7 | Our core PLLs are intended to be configured once and left alone. With |
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8 | the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would |
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9 | change PLLD just to get closer to the requested DSI clock, thus |
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10 | changing PLLD_PER, the UART and ethernet PHY clock rates downstream of |
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11 | it, and breaking ethernet. |
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12 | |||
13 | We *do* want PLLH to change so that PLLH_AUX can be exactly the value |
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14 | we want, though. Thus, we need to have a per-divider policy of |
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15 | whether to pass rate changes up. |
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16 | |||
17 | Signed-off-by: Eric Anholt <eric@anholt.net> |
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18 | Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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19 | (cherry picked from commit 55486091bd1e1c5ed28c43c0d6b3392468a9adb5) |
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20 | --- |
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21 | drivers/clk/bcm/clk-bcm2835.c | 42 ++++++++++++++++++++++++++++-------------- |
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22 | 1 file changed, 28 insertions(+), 14 deletions(-) |
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23 | |||
24 | --- a/drivers/clk/bcm/clk-bcm2835.c |
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25 | +++ b/drivers/clk/bcm/clk-bcm2835.c |
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26 | @@ -428,6 +428,7 @@ struct bcm2835_pll_divider_data { |
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27 | u32 load_mask; |
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28 | u32 hold_mask; |
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29 | u32 fixed_divider; |
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30 | + u32 flags; |
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31 | }; |
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32 | |||
33 | struct bcm2835_clock_data { |
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34 | @@ -1258,7 +1259,7 @@ bcm2835_register_pll_divider(struct bcm2 |
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35 | init.num_parents = 1; |
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36 | init.name = divider_name; |
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37 | init.ops = &bcm2835_pll_divider_clk_ops; |
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38 | - init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; |
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39 | + init.flags = data->flags | CLK_IGNORE_UNUSED; |
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40 | |||
41 | divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); |
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42 | if (!divider) |
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43 | @@ -1481,7 +1482,8 @@ static const struct bcm2835_clk_desc clk |
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44 | .a2w_reg = A2W_PLLA_CORE, |
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45 | .load_mask = CM_PLLA_LOADCORE, |
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46 | .hold_mask = CM_PLLA_HOLDCORE, |
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47 | - .fixed_divider = 1), |
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48 | + .fixed_divider = 1, |
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49 | + .flags = CLK_SET_RATE_PARENT), |
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50 | [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( |
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51 | .name = "plla_per", |
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52 | .source_pll = "plla", |
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53 | @@ -1489,7 +1491,8 @@ static const struct bcm2835_clk_desc clk |
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54 | .a2w_reg = A2W_PLLA_PER, |
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55 | .load_mask = CM_PLLA_LOADPER, |
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56 | .hold_mask = CM_PLLA_HOLDPER, |
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57 | - .fixed_divider = 1), |
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58 | + .fixed_divider = 1, |
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59 | + .flags = CLK_SET_RATE_PARENT), |
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60 | [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( |
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61 | .name = "plla_dsi0", |
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62 | .source_pll = "plla", |
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63 | @@ -1505,7 +1508,8 @@ static const struct bcm2835_clk_desc clk |
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64 | .a2w_reg = A2W_PLLA_CCP2, |
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65 | .load_mask = CM_PLLA_LOADCCP2, |
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66 | .hold_mask = CM_PLLA_HOLDCCP2, |
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67 | - .fixed_divider = 1), |
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68 | + .fixed_divider = 1, |
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69 | + .flags = CLK_SET_RATE_PARENT), |
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70 | |||
71 | /* PLLB is used for the ARM's clock. */ |
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72 | [BCM2835_PLLB] = REGISTER_PLL( |
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73 | @@ -1529,7 +1533,8 @@ static const struct bcm2835_clk_desc clk |
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74 | .a2w_reg = A2W_PLLB_ARM, |
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75 | .load_mask = CM_PLLB_LOADARM, |
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76 | .hold_mask = CM_PLLB_HOLDARM, |
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77 | - .fixed_divider = 1), |
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78 | + .fixed_divider = 1, |
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79 | + .flags = CLK_SET_RATE_PARENT), |
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80 | |||
81 | /* |
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82 | * PLLC is the core PLL, used to drive the core VPU clock. |
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83 | @@ -1558,7 +1563,8 @@ static const struct bcm2835_clk_desc clk |
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84 | .a2w_reg = A2W_PLLC_CORE0, |
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85 | .load_mask = CM_PLLC_LOADCORE0, |
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86 | .hold_mask = CM_PLLC_HOLDCORE0, |
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87 | - .fixed_divider = 1), |
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88 | + .fixed_divider = 1, |
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89 | + .flags = CLK_SET_RATE_PARENT), |
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90 | [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( |
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91 | .name = "pllc_core1", |
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92 | .source_pll = "pllc", |
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93 | @@ -1566,7 +1572,8 @@ static const struct bcm2835_clk_desc clk |
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94 | .a2w_reg = A2W_PLLC_CORE1, |
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95 | .load_mask = CM_PLLC_LOADCORE1, |
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96 | .hold_mask = CM_PLLC_HOLDCORE1, |
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97 | - .fixed_divider = 1), |
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98 | + .fixed_divider = 1, |
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99 | + .flags = CLK_SET_RATE_PARENT), |
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100 | [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( |
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101 | .name = "pllc_core2", |
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102 | .source_pll = "pllc", |
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103 | @@ -1574,7 +1581,8 @@ static const struct bcm2835_clk_desc clk |
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104 | .a2w_reg = A2W_PLLC_CORE2, |
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105 | .load_mask = CM_PLLC_LOADCORE2, |
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106 | .hold_mask = CM_PLLC_HOLDCORE2, |
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107 | - .fixed_divider = 1), |
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108 | + .fixed_divider = 1, |
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109 | + .flags = CLK_SET_RATE_PARENT), |
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110 | [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( |
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111 | .name = "pllc_per", |
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112 | .source_pll = "pllc", |
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113 | @@ -1582,7 +1590,8 @@ static const struct bcm2835_clk_desc clk |
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114 | .a2w_reg = A2W_PLLC_PER, |
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115 | .load_mask = CM_PLLC_LOADPER, |
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116 | .hold_mask = CM_PLLC_HOLDPER, |
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117 | - .fixed_divider = 1), |
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118 | + .fixed_divider = 1, |
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119 | + .flags = CLK_SET_RATE_PARENT), |
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120 | |||
121 | /* |
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122 | * PLLD is the display PLL, used to drive DSI display panels. |
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123 | @@ -1611,7 +1620,8 @@ static const struct bcm2835_clk_desc clk |
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124 | .a2w_reg = A2W_PLLD_CORE, |
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125 | .load_mask = CM_PLLD_LOADCORE, |
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126 | .hold_mask = CM_PLLD_HOLDCORE, |
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127 | - .fixed_divider = 1), |
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128 | + .fixed_divider = 1, |
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129 | + .flags = CLK_SET_RATE_PARENT), |
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130 | [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( |
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131 | .name = "plld_per", |
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132 | .source_pll = "plld", |
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133 | @@ -1619,7 +1629,8 @@ static const struct bcm2835_clk_desc clk |
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134 | .a2w_reg = A2W_PLLD_PER, |
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135 | .load_mask = CM_PLLD_LOADPER, |
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136 | .hold_mask = CM_PLLD_HOLDPER, |
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137 | - .fixed_divider = 1), |
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138 | + .fixed_divider = 1, |
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139 | + .flags = CLK_SET_RATE_PARENT), |
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140 | [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( |
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141 | .name = "plld_dsi0", |
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142 | .source_pll = "plld", |
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143 | @@ -1664,7 +1675,8 @@ static const struct bcm2835_clk_desc clk |
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144 | .a2w_reg = A2W_PLLH_RCAL, |
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145 | .load_mask = CM_PLLH_LOADRCAL, |
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146 | .hold_mask = 0, |
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147 | - .fixed_divider = 10), |
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148 | + .fixed_divider = 10, |
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149 | + .flags = CLK_SET_RATE_PARENT), |
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150 | [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( |
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151 | .name = "pllh_aux", |
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152 | .source_pll = "pllh", |
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153 | @@ -1672,7 +1684,8 @@ static const struct bcm2835_clk_desc clk |
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154 | .a2w_reg = A2W_PLLH_AUX, |
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155 | .load_mask = CM_PLLH_LOADAUX, |
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156 | .hold_mask = 0, |
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157 | - .fixed_divider = 1), |
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158 | + .fixed_divider = 1, |
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159 | + .flags = CLK_SET_RATE_PARENT), |
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160 | [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( |
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161 | .name = "pllh_pix", |
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162 | .source_pll = "pllh", |
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163 | @@ -1680,7 +1693,8 @@ static const struct bcm2835_clk_desc clk |
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164 | .a2w_reg = A2W_PLLH_PIX, |
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165 | .load_mask = CM_PLLH_LOADPIX, |
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166 | .hold_mask = 0, |
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167 | - .fixed_divider = 10), |
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168 | + .fixed_divider = 10, |
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169 | + .flags = CLK_SET_RATE_PARENT), |
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170 | |||
171 | /* the clocks */ |
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172 |