OpenWrt – Blame information for rev 4

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4 office 1 /*
2 * This is a part of mm/cache-v7.S with extracted entry flushing D-cache. We
3 * need it for Broadcom devices with broken bootloader leaving cache enabled.
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2005 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12  
13 #include <linux/linkage.h>
14 #include <linux/init.h>
15  
16 __INIT
17  
18 /*
19 * v7_flush_dcache_all()
20 *
21 * Flush the whole D-cache.
22 *
23 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
24 *
25 * - mm - mm_struct describing address space
26 */
27 ENTRY(v7_flush_dcache_all)
28 dmb @ ensure ordering with previous memory accesses
29 mrc p15, 1, r0, c0, c0, 1 @ read clidr
30 mov r3, r0, lsr #23 @ move LoC into position
31 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
32 beq finished @ if loc is 0, then no need to clean
33 start_flush_levels:
34 mov r10, #0 @ start clean at cache level 0
35 flush_levels:
36 add r2, r10, r10, lsr #1 @ work out 3x current cache level
37 mov r1, r0, lsr r2 @ extract cache type bits from clidr
38 and r1, r1, #7 @ mask of the bits for current cache only
39 cmp r1, #2 @ see what cache we have at this level
40 blt skip @ skip if no cache, or just i-cache
41 #ifdef CONFIG_PREEMPT
42 save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
43 #endif
44 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
45 isb @ isb to sych the new cssr&csidr
46 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
47 #ifdef CONFIG_PREEMPT
48 restore_irqs_notrace r9
49 #endif
50 and r2, r1, #7 @ extract the length of the cache lines
51 add r2, r2, #4 @ add 4 (line length offset)
52 movw r4, #0x3ff
53 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
54 clz r5, r4 @ find bit position of way size increment
55 movw r7, #0x7fff
56 ands r7, r7, r1, lsr #13 @ extract max number of the index size
57 loop1:
58 mov r9, r7 @ create working copy of max index
59 loop2:
60 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
61 THUMB( lsl r6, r4, r5 )
62 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
63 ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
64 THUMB( lsl r6, r9, r2 )
65 THUMB( orr r11, r11, r6 ) @ factor index number into r11
66 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
67 subs r9, r9, #1 @ decrement the index
68 bge loop2
69 subs r4, r4, #1 @ decrement the way
70 bge loop1
71 skip:
72 add r10, r10, #2 @ increment cache number
73 cmp r3, r10
74 bgt flush_levels
75 finished:
76 mov r10, #0 @ swith back to cache level 0
77 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
78 dsb st
79 isb
80 ret lr
81 ENDPROC(v7_flush_dcache_all)