OpenWrt – Blame information for rev 4

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Rev:
Rev Author Line No. Line
4 office 1 --- a/arch/mips/ath25/Kconfig
2 +++ b/arch/mips/ath25/Kconfig
3 @@ -8,6 +8,7 @@ config SOC_AR5312
4 config SOC_AR2315
5 bool "Atheros AR2315+ SoC support"
6 depends on ATH25
7 + select GPIO_AR2315
8 default y
9  
10 config PCI_AR2315
11 --- a/arch/mips/ath25/ar2315.c
12 +++ b/arch/mips/ath25/ar2315.c
13 @@ -21,6 +21,8 @@
14 #include <linux/interrupt.h>
15 #include <linux/platform_device.h>
16 #include <linux/reboot.h>
17 +#include <linux/delay.h>
18 +#include <linux/gpio.h>
19 #include <asm/bootinfo.h>
20 #include <asm/reboot.h>
21 #include <asm/time.h>
22 @@ -167,11 +169,42 @@ void __init ar2315_arch_init_irq(void)
23 ar2315_misc_irq_domain = domain;
24 }
25  
26 +static struct resource ar2315_gpio_res[] = {
27 + {
28 + .name = "ar2315-gpio",
29 + .flags = IORESOURCE_MEM,
30 + .start = AR2315_RST_BASE + AR2315_GPIO,
31 + .end = AR2315_RST_BASE + AR2315_GPIO + 0x10 - 1,
32 + },
33 + {
34 + .name = "ar2315-gpio",
35 + .flags = IORESOURCE_IRQ,
36 + },
37 + {
38 + .name = "ar2315-gpio-irq-base",
39 + .flags = IORESOURCE_IRQ,
40 + .start = AR231X_GPIO_IRQ_BASE,
41 + .end = AR231X_GPIO_IRQ_BASE,
42 + }
43 +};
44 +
45 +static struct platform_device ar2315_gpio = {
46 + .id = -1,
47 + .name = "ar2315-gpio",
48 + .resource = ar2315_gpio_res,
49 + .num_resources = ARRAY_SIZE(ar2315_gpio_res)
50 +};
51 +
52 void __init ar2315_init_devices(void)
53 {
54 /* Find board configuration */
55 ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
56  
57 + ar2315_gpio_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
58 + AR2315_MISC_IRQ_GPIO);
59 + ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
60 + platform_device_register(&ar2315_gpio);
61 +
62 ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
63 }
64  
65 @@ -187,8 +220,8 @@ static void ar2315_restart(char *command
66 /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
67 * a workaround. Give it some time to attempt a gpio based hardware
68 * reset (atheros reference design workaround) */
69 -
70 - /* TODO: implement the GPIO reset workaround */
71 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
72 + mdelay(100);
73  
74 /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
75 * workaround. Attempt to jump to the mips reset location -
76 --- a/drivers/gpio/Kconfig
77 +++ b/drivers/gpio/Kconfig
78 @@ -105,6 +105,13 @@ config GPIO_AMDPT
79 driver for GPIO functionality on Promontory IOHub
80 Require ACPI ASL code to enumerate as a platform device.
81  
82 +config GPIO_AR2315
83 + bool "AR2315 SoC GPIO support"
84 + default y if SOC_AR2315
85 + depends on SOC_AR2315
86 + help
87 + Say yes here to enable GPIO support for Atheros AR2315+ SoCs.
88 +
89 config GPIO_AR5312
90 bool "AR5312 SoC GPIO support"
91 default y if SOC_AR5312
92 --- a/drivers/gpio/Makefile
93 +++ b/drivers/gpio/Makefile
94 @@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-alte
95 obj-$(CONFIG_GPIO_ALTERA_A10SR) += gpio-altera-a10sr.o
96 obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
97 obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o
98 +obj-$(CONFIG_GPIO_AR2315) += gpio-ar2315.o
99 obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
100 obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
101 obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o
102 --- /dev/null
103 +++ b/drivers/gpio/gpio-ar2315.c
104 @@ -0,0 +1,233 @@
105 +/*
106 + * This file is subject to the terms and conditions of the GNU General Public
107 + * License. See the file "COPYING" in the main directory of this archive
108 + * for more details.
109 + *
110 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
111 + * Copyright (C) 2006 FON Technology, SL.
112 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
113 + * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>
114 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
115 + */
116 +
117 +#include <linux/kernel.h>
118 +#include <linux/init.h>
119 +#include <linux/platform_device.h>
120 +#include <linux/gpio.h>
121 +#include <linux/irq.h>
122 +
123 +#define DRIVER_NAME "ar2315-gpio"
124 +
125 +#define AR2315_GPIO_DI 0x0000
126 +#define AR2315_GPIO_DO 0x0008
127 +#define AR2315_GPIO_DIR 0x0010
128 +#define AR2315_GPIO_INT 0x0018
129 +
130 +#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
131 +#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
132 +#define AR2315_GPIO_DIR_I(x) (0) /* input */
133 +
134 +#define AR2315_GPIO_INT_NUM_M 0x3F /* mask for GPIO num */
135 +#define AR2315_GPIO_INT_TRIG(x) ((x) << 6) /* interrupt trigger */
136 +#define AR2315_GPIO_INT_TRIG_M (0x3 << 6) /* mask for int trig */
137 +
138 +#define AR2315_GPIO_INT_TRIG_OFF 0 /* Triggerring off */
139 +#define AR2315_GPIO_INT_TRIG_LOW 1 /* Low Level Triggered */
140 +#define AR2315_GPIO_INT_TRIG_HIGH 2 /* High Level Triggered */
141 +#define AR2315_GPIO_INT_TRIG_EDGE 3 /* Edge Triggered */
142 +
143 +#define AR2315_GPIO_NUM 22
144 +
145 +static u32 ar2315_gpio_intmask;
146 +static u32 ar2315_gpio_intval;
147 +static unsigned ar2315_gpio_irq_base;
148 +static void __iomem *ar2315_mem;
149 +
150 +static inline u32 ar2315_gpio_reg_read(unsigned reg)
151 +{
152 + return __raw_readl(ar2315_mem + reg);
153 +}
154 +
155 +static inline void ar2315_gpio_reg_write(unsigned reg, u32 val)
156 +{
157 + __raw_writel(val, ar2315_mem + reg);
158 +}
159 +
160 +static inline void ar2315_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
161 +{
162 + ar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val);
163 +}
164 +
165 +static void ar2315_gpio_irq_handler(struct irq_desc *desc)
166 +{
167 + u32 pend;
168 + int bit = -1;
169 +
170 + /* only do one gpio interrupt at a time */
171 + pend = ar2315_gpio_reg_read(AR2315_GPIO_DI);
172 + pend ^= ar2315_gpio_intval;
173 + pend &= ar2315_gpio_intmask;
174 +
175 + if (pend) {
176 + bit = fls(pend) - 1;
177 + pend &= ~(1 << bit);
178 + ar2315_gpio_intval ^= (1 << bit);
179 + }
180 +
181 + /* Enable interrupt with edge detection */
182 + if ((ar2315_gpio_reg_read(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
183 + AR2315_GPIO_DIR_I(bit))
184 + return;
185 +
186 + if (bit >= 0)
187 + generic_handle_irq(ar2315_gpio_irq_base + bit);
188 +}
189 +
190 +static void ar2315_gpio_int_setup(unsigned gpio, int trig)
191 +{
192 + u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_INT);
193 +
194 + reg &= ~(AR2315_GPIO_INT_NUM_M | AR2315_GPIO_INT_TRIG_M);
195 + reg |= gpio | AR2315_GPIO_INT_TRIG(trig);
196 + ar2315_gpio_reg_write(AR2315_GPIO_INT, reg);
197 +}
198 +
199 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
200 +{
201 + unsigned gpio = d->irq - ar2315_gpio_irq_base;
202 + u32 dir = ar2315_gpio_reg_read(AR2315_GPIO_DIR);
203 +
204 + /* Enable interrupt with edge detection */
205 + if ((dir & AR2315_GPIO_DIR_M(gpio)) != AR2315_GPIO_DIR_I(gpio))
206 + return;
207 +
208 + ar2315_gpio_intmask |= (1 << gpio);
209 + ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_EDGE);
210 +}
211 +
212 +static void ar2315_gpio_irq_mask(struct irq_data *d)
213 +{
214 + unsigned gpio = d->irq - ar2315_gpio_irq_base;
215 +
216 + /* Disable interrupt */
217 + ar2315_gpio_intmask &= ~(1 << gpio);
218 + ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_OFF);
219 +}
220 +
221 +static struct irq_chip ar2315_gpio_irq_chip = {
222 + .name = DRIVER_NAME,
223 + .irq_unmask = ar2315_gpio_irq_unmask,
224 + .irq_mask = ar2315_gpio_irq_mask,
225 +};
226 +
227 +static void ar2315_gpio_irq_init(unsigned irq)
228 +{
229 + unsigned i;
230 +
231 + ar2315_gpio_intval = ar2315_gpio_reg_read(AR2315_GPIO_DI);
232 + for (i = 0; i < AR2315_GPIO_NUM; i++) {
233 + unsigned _irq = ar2315_gpio_irq_base + i;
234 +
235 + irq_set_chip_and_handler(_irq, &ar2315_gpio_irq_chip,
236 + handle_level_irq);
237 + }
238 + irq_set_chained_handler(irq, ar2315_gpio_irq_handler);
239 +}
240 +
241 +static int ar2315_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
242 +{
243 + return (ar2315_gpio_reg_read(AR2315_GPIO_DI) >> gpio) & 1;
244 +}
245 +
246 +static void ar2315_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
247 +{
248 + u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_DO);
249 +
250 + reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
251 + ar2315_gpio_reg_write(AR2315_GPIO_DO, reg);
252 +}
253 +
254 +static int ar2315_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
255 +{
256 + ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 1 << gpio, 0);
257 + return 0;
258 +}
259 +
260 +static int ar2315_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
261 +{
262 + ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 0, 1 << gpio);
263 + ar2315_gpio_set_val(chip, gpio, val);
264 + return 0;
265 +}
266 +
267 +static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
268 +{
269 + return ar2315_gpio_irq_base + gpio;
270 +}
271 +
272 +static struct gpio_chip ar2315_gpio_chip = {
273 + .label = DRIVER_NAME,
274 + .direction_input = ar2315_gpio_dir_in,
275 + .direction_output = ar2315_gpio_dir_out,
276 + .set = ar2315_gpio_set_val,
277 + .get = ar2315_gpio_get_val,
278 + .to_irq = ar2315_gpio_to_irq,
279 + .base = 0,
280 + .ngpio = AR2315_GPIO_NUM,
281 +};
282 +
283 +static int ar2315_gpio_probe(struct platform_device *pdev)
284 +{
285 + struct device *dev = &pdev->dev;
286 + struct resource *res;
287 + unsigned irq;
288 + int ret;
289 +
290 + if (ar2315_mem)
291 + return -EBUSY;
292 +
293 + res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
294 + "ar2315-gpio-irq-base");
295 + if (!res) {
296 + dev_err(dev, "not found GPIO IRQ base\n");
297 + return -ENXIO;
298 + }
299 + ar2315_gpio_irq_base = res->start;
300 +
301 + res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, DRIVER_NAME);
302 + if (!res) {
303 + dev_err(dev, "not found IRQ number\n");
304 + return -ENXIO;
305 + }
306 + irq = res->start;
307 +
308 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, DRIVER_NAME);
309 + ar2315_mem = devm_ioremap_resource(dev, res);
310 + if (IS_ERR(ar2315_mem))
311 + return PTR_ERR(ar2315_mem);
312 +
313 + ar2315_gpio_chip.parent = dev;
314 + ret = gpiochip_add(&ar2315_gpio_chip);
315 + if (ret) {
316 + dev_err(dev, "failed to add gpiochip\n");
317 + return ret;
318 + }
319 +
320 + ar2315_gpio_irq_init(irq);
321 +
322 + return 0;
323 +}
324 +
325 +static struct platform_driver ar2315_gpio_driver = {
326 + .probe = ar2315_gpio_probe,
327 + .driver = {
328 + .name = DRIVER_NAME,
329 + .owner = THIS_MODULE,
330 + }
331 +};
332 +
333 +static int __init ar2315_gpio_init(void)
334 +{
335 + return platform_driver_register(&ar2315_gpio_driver);
336 +}
337 +subsys_initcall(ar2315_gpio_init);
338 --- a/arch/mips/ath25/devices.h
339 +++ b/arch/mips/ath25/devices.h
340 @@ -4,6 +4,11 @@
341  
342 #include <linux/cpu.h>
343  
344 +#define AR231X_GPIO_IRQ_BASE 0x30
345 +
346 +/* GPIO number for AR2315/16 reset issue workaround */
347 +#define AR2315_RESET_GPIO 5
348 +
349 #define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
350  
351 #define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
352 --- a/arch/mips/ath25/ar2315_regs.h
353 +++ b/arch/mips/ath25/ar2315_regs.h
354 @@ -315,6 +315,9 @@
355 #define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
356 #define AR2315_MEM_CFG_BANKADDR_BITS_S 3
357  
358 +/* GPIO MMR base address */
359 +#define AR2315_GPIO 0x0088
360 +
361 /*
362 * Local Bus Interface Registers
363 */