OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | --- a/arch/mips/ath25/Kconfig |
2 | +++ b/arch/mips/ath25/Kconfig |
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3 | @@ -2,6 +2,7 @@ |
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4 | config SOC_AR5312 |
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5 | bool "Atheros AR5312/AR2312+ SoC support" |
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6 | depends on ATH25 |
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7 | + select GPIO_AR5312 |
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8 | default y |
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9 | |||
10 | config SOC_AR2315 |
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11 | --- a/arch/mips/ath25/ar5312.c |
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12 | +++ b/arch/mips/ath25/ar5312.c |
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13 | @@ -22,6 +22,7 @@ |
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14 | #include <linux/platform_device.h> |
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15 | #include <linux/mtd/physmap.h> |
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16 | #include <linux/reboot.h> |
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17 | +#include <linux/gpio.h> |
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18 | #include <asm/bootinfo.h> |
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19 | #include <asm/reboot.h> |
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20 | #include <asm/time.h> |
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21 | @@ -180,6 +181,22 @@ static struct platform_device ar5312_phy |
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22 | .num_resources = 1, |
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23 | }; |
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24 | |||
25 | +static struct resource ar5312_gpio_res[] = { |
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26 | + { |
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27 | + .name = "ar5312-gpio", |
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28 | + .flags = IORESOURCE_MEM, |
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29 | + .start = AR5312_GPIO_BASE, |
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30 | + .end = AR5312_GPIO_BASE + AR5312_GPIO_SIZE - 1, |
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31 | + }, |
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32 | +}; |
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33 | + |
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34 | +static struct platform_device ar5312_gpio = { |
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35 | + .name = "ar5312-gpio", |
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36 | + .id = -1, |
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37 | + .resource = ar5312_gpio_res, |
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38 | + .num_resources = ARRAY_SIZE(ar5312_gpio_res), |
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39 | +}; |
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40 | + |
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41 | static void __init ar5312_flash_init(void) |
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42 | { |
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43 | void __iomem *flashctl_base; |
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44 | @@ -247,6 +264,8 @@ void __init ar5312_init_devices(void) |
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45 | |||
46 | platform_device_register(&ar5312_physmap_flash); |
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47 | |||
48 | + platform_device_register(&ar5312_gpio); |
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49 | + |
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50 | switch (ath25_soc) { |
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51 | case ATH25_SOC_AR5312: |
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52 | if (!ath25_board.radio) |
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53 | --- a/drivers/gpio/Kconfig |
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54 | +++ b/drivers/gpio/Kconfig |
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55 | @@ -105,6 +105,13 @@ config GPIO_AMDPT |
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56 | driver for GPIO functionality on Promontory IOHub |
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57 | Require ACPI ASL code to enumerate as a platform device. |
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58 | |||
59 | +config GPIO_AR5312 |
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60 | + bool "AR5312 SoC GPIO support" |
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61 | + default y if SOC_AR5312 |
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62 | + depends on SOC_AR5312 |
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63 | + help |
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64 | + Say yes here to enable GPIO support for Atheros AR5312/AR2312+ SoCs. |
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65 | + |
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66 | config GPIO_ASPEED |
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67 | tristate "Aspeed GPIO support" |
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68 | depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO |
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69 | --- a/drivers/gpio/Makefile |
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70 | +++ b/drivers/gpio/Makefile |
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71 | @@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-alte |
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72 | obj-$(CONFIG_GPIO_ALTERA_A10SR) += gpio-altera-a10sr.o |
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73 | obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o |
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74 | obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o |
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75 | +obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o |
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76 | obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o |
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77 | obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o |
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78 | obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o |
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79 | --- /dev/null |
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80 | +++ b/drivers/gpio/gpio-ar5312.c |
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81 | @@ -0,0 +1,121 @@ |
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82 | +/* |
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83 | + * This file is subject to the terms and conditions of the GNU General Public |
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84 | + * License. See the file "COPYING" in the main directory of this archive |
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85 | + * for more details. |
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86 | + * |
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87 | + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. |
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88 | + * Copyright (C) 2006 FON Technology, SL. |
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89 | + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org> |
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90 | + * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name> |
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91 | + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com> |
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92 | + */ |
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93 | + |
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94 | +#include <linux/kernel.h> |
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95 | +#include <linux/init.h> |
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96 | +#include <linux/platform_device.h> |
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97 | +#include <linux/gpio.h> |
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98 | + |
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99 | +#define DRIVER_NAME "ar5312-gpio" |
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100 | + |
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101 | +#define AR5312_GPIO_DO 0x00 /* output register */ |
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102 | +#define AR5312_GPIO_DI 0x04 /* intput register */ |
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103 | +#define AR5312_GPIO_CR 0x08 /* control register */ |
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104 | + |
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105 | +#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ |
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106 | +#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */ |
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107 | +#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */ |
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108 | +#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ |
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109 | +#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ |
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110 | + |
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111 | +#define AR5312_GPIO_NUM 8 |
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112 | + |
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113 | +static void __iomem *ar5312_mem; |
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114 | + |
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115 | +static inline u32 ar5312_gpio_reg_read(unsigned reg) |
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116 | +{ |
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117 | + return __raw_readl(ar5312_mem + reg); |
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118 | +} |
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119 | + |
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120 | +static inline void ar5312_gpio_reg_write(unsigned reg, u32 val) |
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121 | +{ |
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122 | + __raw_writel(val, ar5312_mem + reg); |
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123 | +} |
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124 | + |
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125 | +static inline void ar5312_gpio_reg_mask(unsigned reg, u32 mask, u32 val) |
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126 | +{ |
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127 | + ar5312_gpio_reg_write(reg, (ar5312_gpio_reg_read(reg) & ~mask) | val); |
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128 | +} |
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129 | + |
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130 | +static int ar5312_gpio_get_val(struct gpio_chip *chip, unsigned gpio) |
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131 | +{ |
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132 | + return (ar5312_gpio_reg_read(AR5312_GPIO_DI) >> gpio) & 1; |
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133 | +} |
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134 | + |
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135 | +static void ar5312_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val) |
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136 | +{ |
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137 | + u32 reg = ar5312_gpio_reg_read(AR5312_GPIO_DO); |
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138 | + |
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139 | + reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio); |
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140 | + ar5312_gpio_reg_write(AR5312_GPIO_DO, reg); |
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141 | +} |
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142 | + |
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143 | +static int ar5312_gpio_dir_in(struct gpio_chip *chip, unsigned gpio) |
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144 | +{ |
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145 | + ar5312_gpio_reg_mask(AR5312_GPIO_CR, 0, 1 << gpio); |
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146 | + return 0; |
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147 | +} |
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148 | + |
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149 | +static int ar5312_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val) |
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150 | +{ |
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151 | + ar5312_gpio_reg_mask(AR5312_GPIO_CR, 1 << gpio, 0); |
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152 | + ar5312_gpio_set_val(chip, gpio, val); |
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153 | + return 0; |
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154 | +} |
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155 | + |
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156 | +static struct gpio_chip ar5312_gpio_chip = { |
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157 | + .label = DRIVER_NAME, |
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158 | + .direction_input = ar5312_gpio_dir_in, |
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159 | + .direction_output = ar5312_gpio_dir_out, |
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160 | + .set = ar5312_gpio_set_val, |
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161 | + .get = ar5312_gpio_get_val, |
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162 | + .base = 0, |
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163 | + .ngpio = AR5312_GPIO_NUM, |
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164 | +}; |
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165 | + |
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166 | +static int ar5312_gpio_probe(struct platform_device *pdev) |
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167 | +{ |
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168 | + struct device *dev = &pdev->dev; |
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169 | + struct resource *res; |
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170 | + int ret; |
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171 | + |
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172 | + if (ar5312_mem) |
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173 | + return -EBUSY; |
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174 | + |
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175 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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176 | + ar5312_mem = devm_ioremap_resource(dev, res); |
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177 | + if (IS_ERR(ar5312_mem)) |
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178 | + return PTR_ERR(ar5312_mem); |
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179 | + |
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180 | + ar5312_gpio_chip.parent = dev; |
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181 | + ret = gpiochip_add(&ar5312_gpio_chip); |
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182 | + if (ret) { |
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183 | + dev_err(dev, "failed to add gpiochip\n"); |
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184 | + return ret; |
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185 | + } |
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186 | + |
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187 | + return 0; |
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188 | +} |
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189 | + |
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190 | +static struct platform_driver ar5312_gpio_driver = { |
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191 | + .probe = ar5312_gpio_probe, |
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192 | + .driver = { |
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193 | + .name = DRIVER_NAME, |
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194 | + .owner = THIS_MODULE, |
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195 | + } |
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196 | +}; |
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197 | + |
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198 | +static int __init ar5312_gpio_init(void) |
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199 | +{ |
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200 | + return platform_driver_register(&ar5312_gpio_driver); |
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201 | +} |
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202 | +subsys_initcall(ar5312_gpio_init); |
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203 | --- a/arch/mips/Kconfig |
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204 | +++ b/arch/mips/Kconfig |
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205 | @@ -174,6 +174,7 @@ config ATH25 |
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206 | select CEVT_R4K |
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207 | select CSRC_R4K |
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208 | select DMA_NONCOHERENT |
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209 | + select GPIOLIB |
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210 | select IRQ_MIPS_CPU |
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211 | select IRQ_DOMAIN |
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212 | select SYS_HAS_CPU_MIPS32_R1 |