OpenWrt – Blame information for rev 4
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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4 | office | 1 | //*--------------------------------------------------------------------------- |
| 2 | //* ATMEL Microcontroller Software Support - ROUSSET - |
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| 3 | //*--------------------------------------------------------------------------- |
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| 4 | //* The software is delivered "AS IS" without warranty or condition of any |
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| 5 | //* kind, either express, implied or statutory. This includes without |
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| 6 | //* limitation any warranty or condition with respect to merchantability or |
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| 7 | //* fitness for any particular purpose, or against the infringements of |
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| 8 | //* intellectual property rights of others. |
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| 9 | //*--------------------------------------------------------------------------- |
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| 10 | //* File Name : AT91C_MCI_Device.h |
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| 11 | //* Object : Data Flash Atmel Description File |
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| 12 | //* Translator : |
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| 13 | //* |
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| 14 | //* 1.0 26/11/02 FB : Creation |
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| 15 | //*--------------------------------------------------------------------------- |
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| 16 | |||
| 17 | #ifndef AT91C_MCI_Device_h |
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| 18 | #define AT91C_MCI_Device_h |
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| 19 | |||
| 20 | #include "AT91RM9200.h" |
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| 21 | #include "lib_AT91RM9200.h" |
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| 22 | |||
| 23 | typedef unsigned int AT91S_MCIDeviceStatus; |
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| 24 | |||
| 25 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 26 | |||
| 27 | #define AT91C_CARD_REMOVED 0 |
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| 28 | #define AT91C_MMC_CARD_INSERTED 1 |
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| 29 | #define AT91C_SD_CARD_INSERTED 2 |
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| 30 | |||
| 31 | #define AT91C_NO_ARGUMENT 0x0 |
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| 32 | |||
| 33 | #define AT91C_FIRST_RCA 0xCAFE |
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| 34 | #define AT91C_MAX_MCI_CARDS 10 |
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| 35 | |||
| 36 | #define AT91C_BUS_WIDTH_1BIT 0x00 |
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| 37 | #define AT91C_BUS_WIDTH_4BITS 0x02 |
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| 38 | |||
| 39 | /* Driver State */ |
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| 40 | #define AT91C_MCI_IDLE 0x0 |
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| 41 | #define AT91C_MCI_TIMEOUT_ERROR 0x1 |
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| 42 | #define AT91C_MCI_RX_SINGLE_BLOCK 0x2 |
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| 43 | #define AT91C_MCI_RX_MULTIPLE_BLOCK 0x3 |
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| 44 | #define AT91C_MCI_RX_STREAM 0x4 |
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| 45 | #define AT91C_MCI_TX_SINGLE_BLOCK 0x5 |
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| 46 | #define AT91C_MCI_TX_MULTIPLE_BLOCK 0x6 |
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| 47 | #define AT91C_MCI_TX_STREAM 0x7 |
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| 48 | |||
| 49 | /* TimeOut */ |
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| 50 | #define AT91C_TIMEOUT_CMDRDY 30 |
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| 51 | |||
| 52 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 53 | // MMC & SDCard Structures |
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| 54 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 55 | |||
| 56 | /*-----------------------------------------------*/ |
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| 57 | /* SDCard Device Descriptor Structure Definition */ |
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| 58 | /*-----------------------------------------------*/ |
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| 59 | typedef struct _AT91S_MciDeviceDesc |
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| 60 | { |
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| 61 | volatile unsigned char state; |
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| 62 | unsigned char SDCard_bus_width; |
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| 63 | |||
| 64 | } AT91S_MciDeviceDesc, *AT91PS_MciDeviceDesc; |
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| 65 | |||
| 66 | /*---------------------------------------------*/ |
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| 67 | /* MMC & SDCard Structure Device Features */ |
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| 68 | /*---------------------------------------------*/ |
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| 69 | typedef struct _AT91S_MciDeviceFeatures |
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| 70 | { |
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| 71 | unsigned char Card_Inserted; // (0=AT91C_CARD_REMOVED) (1=AT91C_MMC_CARD_INSERTED) (2=AT91C_SD_CARD_INSERTED) |
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| 72 | unsigned int Relative_Card_Address; // RCA |
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| 73 | unsigned int Max_Read_DataBlock_Length; // 2^(READ_BL_LEN) in CSD |
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| 74 | unsigned int Max_Write_DataBlock_Length; // 2^(WRITE_BL_LEN) in CSD |
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| 75 | unsigned char Read_Partial; // READ_BL_PARTIAL |
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| 76 | unsigned char Write_Partial; // WRITE_BL_PARTIAL |
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| 77 | unsigned char Erase_Block_Enable; // ERASE_BLK_EN |
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| 78 | unsigned char Read_Block_Misalignment; // READ_BLK_MISALIGN |
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| 79 | unsigned char Write_Block_Misalignment; // WRITE_BLK_MISALIGN |
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| 80 | unsigned char Sector_Size; // SECTOR_SIZE |
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| 81 | unsigned int Memory_Capacity; // Size in bits of the device |
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| 82 | |||
| 83 | } AT91S_MciDeviceFeatures, *AT91PS_MciDeviceFeatures ; |
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| 84 | |||
| 85 | /*---------------------------------------------*/ |
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| 86 | /* MCI Device Structure Definition */ |
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| 87 | /*---------------------------------------------*/ |
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| 88 | typedef struct _AT91S_MciDevice |
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| 89 | { |
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| 90 | AT91PS_MciDeviceDesc pMCI_DeviceDesc; // MCI device descriptor |
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| 91 | AT91PS_MciDeviceFeatures pMCI_DeviceFeatures;// Pointer on a MCI device features array |
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| 92 | }AT91S_MciDevice, *AT91PS_MciDevice; |
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| 93 | |||
| 94 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 95 | // MCI_CMD Register Value |
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| 96 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 97 | #define AT91C_POWER_ON_INIT (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_INIT | AT91C_MCI_OPDCMD) |
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| 98 | |||
| 99 | ///////////////////////////////////////////////////////////////// |
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| 100 | // Class 0 & 1 commands: Basic commands and Read Stream commands |
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| 101 | ///////////////////////////////////////////////////////////////// |
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| 102 | |||
| 103 | #define AT91C_GO_IDLE_STATE_CMD (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE ) |
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| 104 | #define AT91C_MMC_GO_IDLE_STATE_CMD (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_OPDCMD) |
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| 105 | #define AT91C_MMC_SEND_OP_COND_CMD (1 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD) |
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| 106 | #define AT91C_ALL_SEND_CID_CMD (2 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 ) |
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| 107 | #define AT91C_MMC_ALL_SEND_CID_CMD (2 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_OPDCMD) |
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| 108 | #define AT91C_SET_RELATIVE_ADDR_CMD (3 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) |
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| 109 | #define AT91C_MMC_SET_RELATIVE_ADDR_CMD (3 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT | AT91C_MCI_OPDCMD) |
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| 110 | |||
| 111 | #define AT91C_SET_DSR_CMD (4 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_NO | AT91C_MCI_MAXLAT ) // no tested |
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| 112 | |||
| 113 | #define AT91C_SEL_DESEL_CARD_CMD (7 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) |
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| 114 | #define AT91C_SEND_CSD_CMD (9 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_MAXLAT ) |
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| 115 | #define AT91C_SEND_CID_CMD (10 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_MAXLAT ) |
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| 116 | #define AT91C_MMC_READ_DAT_UNTIL_STOP_CMD (11 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT ) |
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| 117 | |||
| 118 | #define AT91C_STOP_TRANSMISSION_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) |
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| 119 | #define AT91C_STOP_TRANSMISSION_SYNC_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_SYNC | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) |
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| 120 | #define AT91C_SEND_STATUS_CMD (13 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) |
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| 121 | #define AT91C_GO_INACTIVE_STATE_CMD (15 | AT91C_MCI_RSPTYP_NO ) |
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| 122 | |||
| 123 | //*------------------------------------------------ |
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| 124 | //* Class 2 commands: Block oriented Read commands |
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| 125 | //*------------------------------------------------ |
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| 126 | |||
| 127 | #define AT91C_SET_BLOCKLEN_CMD (16 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) |
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| 128 | #define AT91C_READ_SINGLE_BLOCK_CMD (17 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_BLOCK | AT91C_MCI_TRDIR | AT91C_MCI_MAXLAT) |
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| 129 | #define AT91C_READ_MULTIPLE_BLOCK_CMD (18 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_MULTIPLE | AT91C_MCI_TRDIR | AT91C_MCI_MAXLAT) |
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| 130 | |||
| 131 | //*-------------------------------------------- |
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| 132 | //* Class 3 commands: Sequential write commands |
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| 133 | //*-------------------------------------------- |
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| 134 | |||
| 135 | #define AT91C_MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 & ~(AT91C_MCI_TRDIR) | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT ) // MMC |
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| 136 | |||
| 137 | //*------------------------------------------------ |
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| 138 | //* Class 4 commands: Block oriented write commands |
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| 139 | //*------------------------------------------------ |
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| 140 | |||
| 141 | #define AT91C_WRITE_BLOCK_CMD (24 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_BLOCK & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT) |
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| 142 | #define AT91C_WRITE_MULTIPLE_BLOCK_CMD (25 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_MULTIPLE & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT) |
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| 143 | #define AT91C_PROGRAM_CSD_CMD (27 | AT91C_MCI_RSPTYP_48 ) |
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| 144 | |||
| 145 | |||
| 146 | //*---------------------------------------- |
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| 147 | //* Class 6 commands: Group Write protect |
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| 148 | //*---------------------------------------- |
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| 149 | |||
| 150 | #define AT91C_SET_WRITE_PROT_CMD (28 | AT91C_MCI_RSPTYP_48 ) |
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| 151 | #define AT91C_CLR_WRITE_PROT_CMD (29 | AT91C_MCI_RSPTYP_48 ) |
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| 152 | #define AT91C_SEND_WRITE_PROT_CMD (30 | AT91C_MCI_RSPTYP_48 ) |
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| 153 | |||
| 154 | |||
| 155 | //*---------------------------------------- |
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| 156 | //* Class 5 commands: Erase commands |
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| 157 | //*---------------------------------------- |
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| 158 | |||
| 159 | #define AT91C_TAG_SECTOR_START_CMD (32 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) |
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| 160 | #define AT91C_TAG_SECTOR_END_CMD (33 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) |
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| 161 | #define AT91C_MMC_UNTAG_SECTOR_CMD (34 | AT91C_MCI_RSPTYP_48 ) |
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| 162 | #define AT91C_MMC_TAG_ERASE_GROUP_START_CMD (35 | AT91C_MCI_RSPTYP_48 ) |
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| 163 | #define AT91C_MMC_TAG_ERASE_GROUP_END_CMD (36 | AT91C_MCI_RSPTYP_48 ) |
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| 164 | #define AT91C_MMC_UNTAG_ERASE_GROUP_CMD (37 | AT91C_MCI_RSPTYP_48 ) |
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| 165 | #define AT91C_ERASE_CMD (38 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT ) |
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| 166 | |||
| 167 | //*---------------------------------------- |
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| 168 | //* Class 7 commands: Lock commands |
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| 169 | //*---------------------------------------- |
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| 170 | |||
| 171 | #define AT91C_LOCK_UNLOCK (42 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) // no tested |
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| 172 | |||
| 173 | //*----------------------------------------------- |
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| 174 | // Class 8 commands: Application specific commands |
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| 175 | //*----------------------------------------------- |
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| 176 | |||
| 177 | #define AT91C_APP_CMD (55 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) |
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| 178 | #define AT91C_GEN_CMD (56 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) // no tested |
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| 179 | |||
| 180 | #define AT91C_SDCARD_SET_BUS_WIDTH_CMD (6 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) |
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| 181 | #define AT91C_SDCARD_STATUS_CMD (13 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) |
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| 182 | #define AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) |
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| 183 | #define AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) |
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| 184 | #define AT91C_SDCARD_APP_OP_COND_CMD (41 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO ) |
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| 185 | #define AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD (42 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) |
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| 186 | #define AT91C_SDCARD_SEND_SCR_CMD (51 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) |
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| 187 | |||
| 188 | #define AT91C_SDCARD_APP_ALL_CMD (AT91C_SDCARD_SET_BUS_WIDTH_CMD +\ |
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| 189 | AT91C_SDCARD_STATUS_CMD +\ |
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| 190 | AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD +\ |
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| 191 | AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\ |
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| 192 | AT91C_SDCARD_APP_OP_COND_CMD +\ |
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| 193 | AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD +\ |
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| 194 | AT91C_SDCARD_SEND_SCR_CMD) |
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| 195 | |||
| 196 | //*---------------------------------------- |
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| 197 | //* Class 9 commands: IO Mode commands |
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| 198 | //*---------------------------------------- |
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| 199 | |||
| 200 | #define AT91C_MMC_FAST_IO_CMD (39 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT) |
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| 201 | #define AT91C_MMC_GO_IRQ_STATE_CMD (40 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) |
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| 202 | |||
| 203 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 204 | // Functions returnals |
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| 205 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 206 | #define AT91C_CMD_SEND_OK 0 // Command ok |
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| 207 | #define AT91C_CMD_SEND_ERROR -1 // Command failed |
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| 208 | #define AT91C_INIT_OK 2 // Init Successfull |
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| 209 | #define AT91C_INIT_ERROR 3 // Init Failed |
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| 210 | #define AT91C_READ_OK 4 // Read Successfull |
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| 211 | #define AT91C_READ_ERROR 5 // Read Failed |
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| 212 | #define AT91C_WRITE_OK 6 // Write Successfull |
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| 213 | #define AT91C_WRITE_ERROR 7 // Write Failed |
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| 214 | #define AT91C_ERASE_OK 8 // Erase Successfull |
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| 215 | #define AT91C_ERASE_ERROR 9 // Erase Failed |
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| 216 | #define AT91C_CARD_SELECTED_OK 10 // Card Selection Successfull |
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| 217 | #define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed |
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| 218 | |||
| 219 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 220 | // MCI_SR Errors |
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| 221 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 222 | #define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE |\ |
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| 223 | AT91C_MCI_OVRE |\ |
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| 224 | AT91C_MCI_DTOE |\ |
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| 225 | AT91C_MCI_DCRCE |\ |
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| 226 | AT91C_MCI_RTOE |\ |
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| 227 | AT91C_MCI_RENDE |\ |
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| 228 | AT91C_MCI_RCRCE |\ |
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| 229 | AT91C_MCI_RDIRE |\ |
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| 230 | AT91C_MCI_RINDE) |
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| 231 | |||
| 232 | //////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 233 | // OCR Register |
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| 234 | //////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 235 | #define AT91C_VDD_16_17 (1 << 4) |
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| 236 | #define AT91C_VDD_17_18 (1 << 5) |
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| 237 | #define AT91C_VDD_18_19 (1 << 6) |
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| 238 | #define AT91C_VDD_19_20 (1 << 7) |
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| 239 | #define AT91C_VDD_20_21 (1 << 8) |
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| 240 | #define AT91C_VDD_21_22 (1 << 9) |
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| 241 | #define AT91C_VDD_22_23 (1 << 10) |
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| 242 | #define AT91C_VDD_23_24 (1 << 11) |
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| 243 | #define AT91C_VDD_24_25 (1 << 12) |
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| 244 | #define AT91C_VDD_25_26 (1 << 13) |
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| 245 | #define AT91C_VDD_26_27 (1 << 14) |
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| 246 | #define AT91C_VDD_27_28 (1 << 15) |
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| 247 | #define AT91C_VDD_28_29 (1 << 16) |
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| 248 | #define AT91C_VDD_29_30 (1 << 17) |
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| 249 | #define AT91C_VDD_30_31 (1 << 18) |
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| 250 | #define AT91C_VDD_31_32 (1 << 19) |
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| 251 | #define AT91C_VDD_32_33 (1 << 20) |
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| 252 | #define AT91C_VDD_33_34 (1 << 21) |
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| 253 | #define AT91C_VDD_34_35 (1 << 22) |
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| 254 | #define AT91C_VDD_35_36 (1 << 23) |
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| 255 | #define AT91C_CARD_POWER_UP_BUSY (1 << 31) |
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| 256 | |||
| 257 | #define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 +\ |
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| 258 | AT91C_VDD_28_29 +\ |
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| 259 | AT91C_VDD_29_30 +\ |
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| 260 | AT91C_VDD_30_31 +\ |
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| 261 | AT91C_VDD_31_32 +\ |
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| 262 | AT91C_VDD_32_33) |
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| 263 | |||
| 264 | //////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 265 | // CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1) |
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| 266 | //////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 267 | #define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus |
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| 268 | #define AT91C_SR_IDLE (0 << 9) |
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| 269 | #define AT91C_SR_READY (1 << 9) |
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| 270 | #define AT91C_SR_IDENT (2 << 9) |
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| 271 | #define AT91C_SR_STBY (3 << 9) |
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| 272 | #define AT91C_SR_TRAN (4 << 9) |
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| 273 | #define AT91C_SR_DATA (5 << 9) |
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| 274 | #define AT91C_SR_RCV (6 << 9) |
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| 275 | #define AT91C_SR_PRG (7 << 9) |
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| 276 | #define AT91C_SR_DIS (8 << 9) |
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| 277 | |||
| 278 | #define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN) |
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| 279 | |||
| 280 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 281 | // MMC CSD register header File |
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| 282 | // AT91C_CSD_xxx_S for shift value |
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| 283 | // AT91C_CSD_xxx_M for mask value |
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| 284 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 285 | |||
| 286 | // First Response INT <=> CSD[3] : bits 0 to 31 |
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| 287 | #define AT91C_CSD_BIT0_S 0 // [0:0] |
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| 288 | #define AT91C_CSD_BIT0_M 0x01 |
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| 289 | #define AT91C_CSD_CRC_S 1 // [7:1] |
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| 290 | #define AT91C_CSD_CRC_M 0x7F |
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| 291 | #define AT91C_CSD_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility |
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| 292 | #define AT91C_CSD_MMC_ECC_M 0x03 |
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| 293 | #define AT91C_CSD_FILE_FMT_S 10 // [11:10] |
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| 294 | #define AT91C_CSD_FILE_FMT_M 0x03 |
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| 295 | #define AT91C_CSD_TMP_WP_S 12 // [12:12] |
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| 296 | #define AT91C_CSD_TMP_WP_M 0x01 |
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| 297 | #define AT91C_CSD_PERM_WP_S 13 // [13:13] |
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| 298 | #define AT91C_CSD_PERM_WP_M 0x01 |
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| 299 | #define AT91C_CSD_COPY_S 14 // [14:14] |
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| 300 | #define AT91C_CSD_COPY_M 0x01 |
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| 301 | #define AT91C_CSD_FILE_FMT_GRP_S 15 // [15:15] |
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| 302 | #define AT91C_CSD_FILE_FMT_GRP_M 0x01 |
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| 303 | // reserved 16 // [20:16] |
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| 304 | // reserved 0x1F |
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| 305 | #define AT91C_CSD_WBLOCK_P_S 21 // [21:21] |
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| 306 | #define AT91C_CSD_WBLOCK_P_M 0x01 |
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| 307 | #define AT91C_CSD_WBLEN_S 22 // [25:22] |
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| 308 | #define AT91C_CSD_WBLEN_M 0x0F |
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| 309 | #define AT91C_CSD_R2W_F_S 26 // [28:26] |
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| 310 | #define AT91C_CSD_R2W_F_M 0x07 |
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| 311 | #define AT91C_CSD_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility |
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| 312 | #define AT91C_CSD_MMC_DEF_ECC_M 0x03 |
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| 313 | #define AT91C_CSD_WP_GRP_EN_S 31 // [31:31] |
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| 314 | #define AT91C_CSD_WP_GRP_EN_M 0x01 |
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| 315 | |||
| 316 | // Seconde Response INT <=> CSD[2] : bits 32 to 63 |
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| 317 | #define AT91C_CSD_v21_WP_GRP_SIZE_S 0 // [38:32] |
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| 318 | #define AT91C_CSD_v21_WP_GRP_SIZE_M 0x7F |
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| 319 | #define AT91C_CSD_v21_SECT_SIZE_S 7 // [45:39] |
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| 320 | #define AT91C_CSD_v21_SECT_SIZE_M 0x7F |
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| 321 | #define AT91C_CSD_v21_ER_BLEN_EN_S 14 // [46:46] |
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| 322 | #define AT91C_CSD_v21_ER_BLEN_EN_M 0x01 |
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| 323 | |||
| 324 | #define AT91C_CSD_v22_WP_GRP_SIZE_S 0 // [36:32] |
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| 325 | #define AT91C_CSD_v22_WP_GRP_SIZE_M 0x1F |
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| 326 | #define AT91C_CSD_v22_ER_GRP_SIZE_S 5 // [41:37] |
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| 327 | #define AT91C_CSD_v22_ER_GRP_SIZE_M 0x1F |
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| 328 | #define AT91C_CSD_v22_SECT_SIZE_S 10 // [46:42] |
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| 329 | #define AT91C_CSD_v22_SECT_SIZE_M 0x1F |
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| 330 | |||
| 331 | #define AT91C_CSD_C_SIZE_M_S 15 // [49:47] |
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| 332 | #define AT91C_CSD_C_SIZE_M_M 0x07 |
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| 333 | #define AT91C_CSD_VDD_WMAX_S 18 // [52:50] |
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| 334 | #define AT91C_CSD_VDD_WMAX_M 0x07 |
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| 335 | #define AT91C_CSD_VDD_WMIN_S 21 // [55:53] |
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| 336 | #define AT91C_CSD_VDD_WMIN_M 0x07 |
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| 337 | #define AT91C_CSD_RCUR_MAX_S 24 // [58:56] |
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| 338 | #define AT91C_CSD_RCUR_MAX_M 0x07 |
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| 339 | #define AT91C_CSD_RCUR_MIN_S 27 // [61:59] |
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| 340 | #define AT91C_CSD_RCUR_MIN_M 0x07 |
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| 341 | #define AT91C_CSD_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE |
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| 342 | #define AT91C_CSD_CSIZE_L_M 0x03 |
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| 343 | |||
| 344 | // Third Response INT <=> CSD[1] : bits 64 to 95 |
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| 345 | #define AT91C_CSD_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE |
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| 346 | #define AT91C_CSD_CSIZE_H_M 0x03FF |
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| 347 | // reserved 10 // [75:74] |
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| 348 | // reserved 0x03 |
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| 349 | #define AT91C_CSD_DSR_I_S 12 // [76:76] |
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| 350 | #define AT91C_CSD_DSR_I_M 0x01 |
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| 351 | #define AT91C_CSD_RD_B_MIS_S 13 // [77:77] |
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| 352 | #define AT91C_CSD_RD_B_MIS_M 0x01 |
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| 353 | #define AT91C_CSD_WR_B_MIS_S 14 // [78:78] |
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| 354 | #define AT91C_CSD_WR_B_MIS_M 0x01 |
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| 355 | #define AT91C_CSD_RD_B_PAR_S 15 // [79:79] |
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| 356 | #define AT91C_CSD_RD_B_PAR_M 0x01 |
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| 357 | #define AT91C_CSD_RD_B_LEN_S 16 // [83:80] |
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| 358 | #define AT91C_CSD_RD_B_LEN_M 0x0F |
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| 359 | #define AT91C_CSD_CCC_S 20 // [95:84] |
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| 360 | #define AT91C_CSD_CCC_M 0x0FFF |
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| 361 | |||
| 362 | // Fourth Response INT <=> CSD[0] : bits 96 to 127 |
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| 363 | #define AT91C_CSD_TRANS_SPEED_S 0 // [103:96] |
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| 364 | #define AT91C_CSD_TRANS_SPEED_M 0xFF |
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| 365 | #define AT91C_CSD_NSAC_S 8 // [111:104] |
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| 366 | #define AT91C_CSD_NSAC_M 0xFF |
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| 367 | #define AT91C_CSD_TAAC_S 16 // [119:112] |
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| 368 | #define AT91C_CSD_TAAC_M 0xFF |
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| 369 | // reserved 24 // [121:120] |
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| 370 | // reserved 0x03 |
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| 371 | #define AT91C_CSD_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility |
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| 372 | #define AT91C_CSD_MMC_SPEC_VERS_M 0x0F |
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| 373 | #define AT91C_CSD_STRUCT_S 30 // [127:126] |
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| 374 | #define AT91C_CSD_STRUCT_M 0x03 |
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| 375 | |||
| 376 | ///////////////////////////////////////////////////////////////////////////////////////////////////// |
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| 377 | |||
| 378 | #endif |
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| 379 |