OpenWrt – Blame information for rev 4

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Rev Author Line No. Line
4 office 1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
3 @@ -659,6 +659,7 @@
4  
5 #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
6 #define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
7 +#define AR933X_BOOTSTRAP_USB_MODE_HOST BIT(3)
8 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
9  
10 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
11 @@ -688,6 +689,8 @@
12  
13 #define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
14  
15 +#define AR933X_USB_CONFIG_HOST_ONLY BIT(8)
16 +
17 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
18 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
19 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
20 --- a/arch/mips/ath79/dev-usb.c
21 +++ b/arch/mips/ath79/dev-usb.c
22 @@ -19,6 +19,9 @@
23 #include <linux/platform_device.h>
24 #include <linux/usb/ehci_pdriver.h>
25 #include <linux/usb/ohci_pdriver.h>
26 +#include <linux/usb/otg.h>
27 +#include <linux/usb/chipidea.h>
28 +#include <linux/usb/usb_phy_generic.h>
29  
30 #include <asm/mach-ath79/ath79.h>
31 #include <asm/mach-ath79/ar71xx_regs.h>
32 @@ -170,6 +173,44 @@ static void __init ar913x_usb_setup(void
33 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
34 }
35  
36 +static void __init ar9xxx_ci_usb_setup(int bus_id, int irq)
37 +{
38 + struct ci_hdrc_platform_data ci_pdata;
39 + bool host_mode = true;
40 +
41 + if (soc_is_ar933x())
42 + host_mode = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP) &
43 + AR933X_BOOTSTRAP_USB_MODE_HOST;
44 + else
45 + host_mode = !(ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP) &
46 + AR934X_BOOTSTRAP_USB_MODE_DEVICE);
47 +
48 + if (host_mode) {
49 + ath79_usb_register("ehci-platform", bus_id,
50 + AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
51 + irq, &ath79_ehci_pdata_v2,
52 + sizeof(ath79_ehci_pdata_v2));
53 +
54 + return;
55 + }
56 +
57 + memset(&ci_pdata, 0, sizeof(ci_pdata));
58 + ci_pdata.name = "ci_hdrc_ar9xxx";
59 + ci_pdata.capoffset = DEF_CAPOFFSET;
60 + ci_pdata.dr_mode = USB_DR_MODE_PERIPHERAL;
61 + ci_pdata.flags = CI_HDRC_DUAL_ROLE_NOT_OTG | CI_HDRC_DP_ALWAYS_PULLUP;
62 + ci_pdata.vbus_extcon.edev = ERR_PTR(-ENODEV);
63 + ci_pdata.id_extcon.edev = ERR_PTR(-ENODEV);
64 + ci_pdata.itc_setting = 1;
65 +
66 + platform_device_register_simple("usb_phy_generic",
67 + PLATFORM_DEVID_AUTO, NULL, 0);
68 +
69 + ath79_usb_register("ci_hdrc", -1,
70 + AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
71 + irq, &ci_pdata, sizeof(ci_pdata));
72 +}
73 +
74 static void __init ar933x_usb_setup(void)
75 {
76 ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
77 @@ -181,10 +222,7 @@ static void __init ar933x_usb_setup(void
78 ath79_device_reset_clear(AR933X_RESET_USB_PHY);
79 mdelay(10);
80  
81 - ath79_usb_register("ehci-platform", -1,
82 - AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
83 - ATH79_CPU_IRQ(3),
84 - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
85 + ar9xxx_ci_usb_setup(-1, ATH79_CPU_IRQ(3));
86 }
87  
88 static void enable_tx_tx_idp_violation_fix(unsigned base)
89 @@ -230,10 +268,7 @@ static void __init ar934x_usb_setup(void
90 if (ath79_soc_rev >= 3)
91 ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier;
92  
93 - ath79_usb_register("ehci-platform", -1,
94 - AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
95 - ATH79_CPU_IRQ(3),
96 - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
97 + ar9xxx_ci_usb_setup(-1, ATH79_CPU_IRQ(3));
98 }
99  
100 static void __init qca953x_usb_setup(void)
101 @@ -254,10 +289,7 @@ static void __init qca953x_usb_setup(voi
102 ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
103 udelay(1000);
104  
105 - ath79_usb_register("ehci-platform", -1,
106 - QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
107 - ATH79_CPU_IRQ(3),
108 - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
109 + ar9xxx_ci_usb_setup(-1, ATH79_CPU_IRQ(3));
110 }
111  
112 static void qca955x_usb_reset_notifier(struct platform_device *pdev)
113 @@ -285,10 +317,7 @@ static void __init qca955x_usb_setup(voi
114 {
115 ath79_ehci_pdata_v2.reset_notifier = qca955x_usb_reset_notifier;
116  
117 - ath79_usb_register("ehci-platform", 0,
118 - QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
119 - ATH79_IP3_IRQ(0),
120 - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
121 + ar9xxx_ci_usb_setup(0, ATH79_IP3_IRQ(0));
122  
123 ath79_usb_register("ehci-platform", 1,
124 QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,