OpenWrt – Blame information for rev 4

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Rev Author Line No. Line
4 office 1 --- a/arch/mips/ath79/mach-ap136.c
2 +++ b/arch/mips/ath79/mach-ap136.c
3 @@ -18,23 +18,29 @@
4 *
5 */
6  
7 -#include <linux/pci.h>
8 -#include <linux/ath9k_platform.h>
9 +#include <linux/platform_device.h>
10 +#include <linux/ar8216_platform.h>
11  
12 -#include "machtypes.h"
13 +#include <asm/mach-ath79/ar71xx_regs.h>
14 +
15 +#include "common.h"
16 +#include "pci.h"
17 +#include "dev-ap9x-pci.h"
18 #include "dev-gpio-buttons.h"
19 +#include "dev-eth.h"
20 #include "dev-leds-gpio.h"
21 -#include "dev-spi.h"
22 +#include "dev-m25p80.h"
23 +#include "dev-nfc.h"
24 #include "dev-usb.h"
25 #include "dev-wmac.h"
26 -#include "pci.h"
27 +#include "machtypes.h"
28  
29 -#define AP136_GPIO_LED_STATUS_RED 14
30 -#define AP136_GPIO_LED_STATUS_GREEN 19
31 #define AP136_GPIO_LED_USB 4
32 -#define AP136_GPIO_LED_WLAN_2G 13
33 #define AP136_GPIO_LED_WLAN_5G 12
34 +#define AP136_GPIO_LED_WLAN_2G 13
35 +#define AP136_GPIO_LED_STATUS_RED 14
36 #define AP136_GPIO_LED_WPS_RED 15
37 +#define AP136_GPIO_LED_STATUS_GREEN 19
38 #define AP136_GPIO_LED_WPS_GREEN 20
39  
40 #define AP136_GPIO_BTN_WPS 16
41 @@ -43,37 +49,39 @@
42 #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
43 #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
44  
45 -#define AP136_WMAC_CALDATA_OFFSET 0x1000
46 -#define AP136_PCIE_CALDATA_OFFSET 0x5000
47 +#define AP136_MAC0_OFFSET 0
48 +#define AP136_MAC1_OFFSET 6
49 +#define AP136_WMAC_CALDATA_OFFSET 0x1000
50 +#define AP136_PCIE_CALDATA_OFFSET 0x5000
51  
52 static struct gpio_led ap136_leds_gpio[] __initdata = {
53 {
54 - .name = "qca:green:status",
55 + .name = "ap136:green:status",
56 .gpio = AP136_GPIO_LED_STATUS_GREEN,
57 .active_low = 1,
58 },
59 {
60 - .name = "qca:red:status",
61 + .name = "ap136:red:status",
62 .gpio = AP136_GPIO_LED_STATUS_RED,
63 .active_low = 1,
64 },
65 {
66 - .name = "qca:green:wps",
67 + .name = "ap136:green:wps",
68 .gpio = AP136_GPIO_LED_WPS_GREEN,
69 .active_low = 1,
70 },
71 {
72 - .name = "qca:red:wps",
73 + .name = "ap136:red:wps",
74 .gpio = AP136_GPIO_LED_WPS_RED,
75 .active_low = 1,
76 },
77 {
78 - .name = "qca:red:wlan-2g",
79 + .name = "ap136:red:wlan-2g",
80 .gpio = AP136_GPIO_LED_WLAN_2G,
81 .active_low = 1,
82 },
83 {
84 - .name = "qca:red:usb",
85 + .name = "ap136:red:usb",
86 .gpio = AP136_GPIO_LED_USB,
87 .active_low = 1,
88 }
89 @@ -98,59 +106,151 @@ static struct gpio_keys_button ap136_gpi
90 },
91 };
92  
93 -static struct spi_board_info ap136_spi_info[] = {
94 - {
95 - .bus_num = 0,
96 - .chip_select = 0,
97 - .max_speed_hz = 25000000,
98 - .modalias = "mx25l6405d",
99 - }
100 +static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
101 +static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
102 +
103 +static struct ar8327_platform_data ap136_ar8327_data = {
104 + .pad0_cfg = &ap136_ar8327_pad0_cfg,
105 + .pad6_cfg = &ap136_ar8327_pad6_cfg,
106 + .port0_cfg = {
107 + .force_link = 1,
108 + .speed = AR8327_PORT_SPEED_1000,
109 + .duplex = 1,
110 + .txpause = 1,
111 + .rxpause = 1,
112 + },
113 + .port6_cfg = {
114 + .force_link = 1,
115 + .speed = AR8327_PORT_SPEED_1000,
116 + .duplex = 1,
117 + .txpause = 1,
118 + .rxpause = 1,
119 + },
120 };
121  
122 -static struct ath79_spi_platform_data ap136_spi_data = {
123 - .bus_num = 0,
124 - .num_chipselect = 1,
125 +static struct mdio_board_info ap136_mdio0_info[] = {
126 + {
127 + .bus_id = "ag71xx-mdio.0",
128 + .phy_addr = 0,
129 + .platform_data = &ap136_ar8327_data,
130 + },
131 };
132  
133 -#ifdef CONFIG_PCI
134 -static struct ath9k_platform_data ap136_ath9k_data;
135 +static void __init ap136_common_setup(void)
136 +{
137 + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
138 +
139 + ath79_register_m25p80(NULL);
140 +
141 + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
142 + ap136_leds_gpio);
143 + ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
144 + ARRAY_SIZE(ap136_gpio_keys),
145 + ap136_gpio_keys);
146 +
147 + ath79_register_usb();
148 + ath79_register_nfc();
149 +
150 + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
151 +
152 + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
153  
154 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
155 + ath79_register_mdio(0, 0x0);
156 + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
157 +
158 + mdiobus_register_board_info(ap136_mdio0_info,
159 + ARRAY_SIZE(ap136_mdio0_info));
160 +
161 + /* GMAC0 is connected to the RMGII interface */
162 + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
163 + ath79_eth0_data.phy_mask = BIT(0);
164 + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
165 +
166 + ath79_register_eth(0);
167 +
168 + /* GMAC1 is connected tot eh SGMII interface */
169 + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
170 + ath79_eth1_data.speed = SPEED_1000;
171 + ath79_eth1_data.duplex = DUPLEX_FULL;
172 +
173 + ath79_register_eth(1);
174 +}
175 +
176 +static void __init ap136_010_setup(void)
177 {
178 - if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
179 - dev->dev.platform_data = &ap136_ath9k_data;
180 + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
181  
182 - return 0;
183 + /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
184 + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
185 + ap136_ar8327_pad0_cfg.txclk_delay_en = true;
186 + ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
187 + ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
188 + ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
189 +
190 + /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
191 + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
192 + ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
193 + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
194 +
195 + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
196 + ath79_eth1_pll_data.pll_1000 = 0x03000101;
197 +
198 + ap136_common_setup();
199 + ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
200 }
201  
202 -static void __init ap136_pci_init(u8 *eeprom)
203 +MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
204 + "Atheros AP136-010 reference board",
205 + ap136_010_setup);
206 +
207 +static void __init ap136_020_common_setup(void)
208 {
209 - memcpy(ap136_ath9k_data.eeprom_data, eeprom,
210 - sizeof(ap136_ath9k_data.eeprom_data));
211 + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
212 + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
213 + ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
214 +
215 + /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
216 + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
217 + ap136_ar8327_pad6_cfg.txclk_delay_en = true;
218 + ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
219 + ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
220 + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
221  
222 - ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
223 - ath79_register_pci();
224 + ath79_eth0_pll_data.pll_1000 = 0x56000000;
225 + ath79_eth1_pll_data.pll_1000 = 0x03000101;
226 +
227 + ap136_common_setup();
228 }
229 -#else
230 -static inline void ap136_pci_init(u8 *eeprom) {}
231 -#endif /* CONFIG_PCI */
232  
233 -static void __init ap136_setup(void)
234 +static void __init ap136_020_setup(void)
235 {
236 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
237  
238 - ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
239 - ap136_leds_gpio);
240 - ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
241 - ARRAY_SIZE(ap136_gpio_keys),
242 - ap136_gpio_keys);
243 - ath79_register_spi(&ap136_spi_data, ap136_spi_info,
244 - ARRAY_SIZE(ap136_spi_info));
245 - ath79_register_usb();
246 - ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
247 - ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
248 + ap136_020_common_setup();
249 + ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
250 }
251  
252 -MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
253 - "Atheros AP136-010 reference board",
254 - ap136_setup);
255 +MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
256 + "Atheros AP136-020 reference board",
257 + ap136_020_setup);
258 +
259 +/*
260 + * AP135-020 is similar to AP136-020, any future AP135 specific init
261 + * code can be added here.
262 + */
263 +static void __init ap135_020_setup(void)
264 +{
265 + ap136_leds_gpio[0].name = "ap135:green:status";
266 + ap136_leds_gpio[1].name = "ap135:red:status";
267 + ap136_leds_gpio[2].name = "ap135:green:wps";
268 + ap136_leds_gpio[3].name = "ap135:red:wps";
269 + ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
270 + ap136_leds_gpio[5].name = "ap135:red:usb";
271 +
272 + ap136_020_common_setup();
273 + ath79_register_pci();
274 +}
275 +
276 +MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
277 + "Atheros AP135-020 reference board",
278 + ap135_020_setup);
279 --- a/arch/mips/ath79/Kconfig
280 +++ b/arch/mips/ath79/Kconfig
281 @@ -16,16 +16,17 @@ config ATH79_MACH_AP121
282 Atheros AP121 reference board.
283  
284 config ATH79_MACH_AP136
285 - bool "Atheros AP136 reference board"
286 + bool "Atheros AP136/AP135 reference board"
287 select SOC_QCA955X
288 select ATH79_DEV_GPIO_BUTTONS
289 select ATH79_DEV_LEDS_GPIO
290 + select ATH79_DEV_NFC
291 select ATH79_DEV_SPI
292 select ATH79_DEV_USB
293 select ATH79_DEV_WMAC
294 help
295 Say 'Y' here if you want your kernel to support the
296 - Atheros AP136 reference board.
297 + Atheros AP136 or AP135 reference boards.
298  
299 config ATH79_MACH_AP81
300 bool "Atheros AP81 reference board"