OpenWrt – Blame information for rev 4

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4 office 1 /*
2 * TP-LINK TL-WR841N/ND v1 board support
3 *
4 * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10  
11 #include <linux/mtd/mtd.h>
12 #include <linux/mtd/partitions.h>
13 #include <linux/platform_device.h>
14  
15 #include <asm/mach-ath79/ath79.h>
16  
17 #include "dev-dsa.h"
18 #include "dev-eth.h"
19 #include "dev-gpio-buttons.h"
20 #include "dev-leds-gpio.h"
21 #include "dev-m25p80.h"
22 #include "machtypes.h"
23 #include "pci.h"
24  
25 #define TL_WR841ND_V1_GPIO_LED_SYSTEM 2
26 #define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4
27 #define TL_WR841ND_V1_GPIO_LED_QSS_RED 5
28  
29 #define TL_WR841ND_V1_GPIO_BTN_RESET 3
30 #define TL_WR841ND_V1_GPIO_BTN_QSS 7
31  
32 #define TL_WR841ND_V1_KEYS_POLL_INTERVAL 20 /* msecs */
33 #define TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL \
34 (3 * TL_WR841ND_V1_KEYS_POLL_INTERVAL)
35  
36 static struct mtd_partition tl_wr841n_v1_partitions[] = {
37 {
38 .name = "redboot",
39 .offset = 0,
40 .size = 0x020000,
41 .mask_flags = MTD_WRITEABLE,
42 }, {
43 .name = "kernel",
44 .offset = 0x020000,
45 .size = 0x140000,
46 }, {
47 .name = "rootfs",
48 .offset = 0x160000,
49 .size = 0x280000,
50 }, {
51 .name = "config",
52 .offset = 0x3e0000,
53 .size = 0x020000,
54 .mask_flags = MTD_WRITEABLE,
55 }, {
56 .name = "firmware",
57 .offset = 0x020000,
58 .size = 0x3c0000,
59 }
60 };
61  
62 static struct flash_platform_data tl_wr841n_v1_flash_data = {
63 .parts = tl_wr841n_v1_partitions,
64 .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions),
65 };
66  
67 static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = {
68 {
69 .name = "tp-link:green:system",
70 .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM,
71 .active_low = 1,
72 }, {
73 .name = "tp-link:red:qss",
74 .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED,
75 }, {
76 .name = "tp-link:green:qss",
77 .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN,
78 }
79 };
80  
81 static struct gpio_keys_button tl_wr841n_v1_gpio_keys[] __initdata = {
82 {
83 .desc = "reset",
84 .type = EV_KEY,
85 .code = KEY_RESTART,
86 .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL,
87 .gpio = TL_WR841ND_V1_GPIO_BTN_RESET,
88 .active_low = 1,
89 }, {
90 .desc = "qss",
91 .type = EV_KEY,
92 .code = KEY_WPS_BUTTON,
93 .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL,
94 .gpio = TL_WR841ND_V1_GPIO_BTN_QSS,
95 .active_low = 1,
96 }
97 };
98  
99 static struct dsa_chip_data tl_wr841n_v1_dsa_chip = {
100 .port_names[0] = "wan",
101 .port_names[1] = "lan1",
102 .port_names[2] = "lan2",
103 .port_names[3] = "lan3",
104 .port_names[4] = "lan4",
105 .port_names[5] = "cpu",
106 };
107  
108 static struct dsa_platform_data tl_wr841n_v1_dsa_data = {
109 .nr_chips = 1,
110 .chip = &tl_wr841n_v1_dsa_chip,
111 };
112  
113 static void __init tl_wr841n_v1_setup(void)
114 {
115 u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
116  
117 ath79_register_mdio(0, 0x0);
118  
119 ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
120 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
121 ath79_eth0_data.speed = SPEED_100;
122 ath79_eth0_data.duplex = DUPLEX_FULL;
123  
124 ath79_register_eth(0);
125 ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev,
126 &tl_wr841n_v1_dsa_data);
127  
128 ath79_register_m25p80(&tl_wr841n_v1_flash_data);
129  
130 ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio),
131 tl_wr841n_v1_leds_gpio);
132  
133 ath79_register_gpio_keys_polled(-1, TL_WR841ND_V1_KEYS_POLL_INTERVAL,
134 ARRAY_SIZE(tl_wr841n_v1_gpio_keys),
135 tl_wr841n_v1_gpio_keys);
136 ath79_register_pci();
137 }
138  
139 MIPS_MACHINE(ATH79_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1",
140 tl_wr841n_v1_setup);