OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | /* |
2 | * OpenMesh OM5P-ACv2 support |
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3 | * |
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4 | * Copyright (C) 2013 Marek Lindner <marek@open-mesh.com> |
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5 | * Copyright (C) 2014-2016 Sven Eckelmann <sven@open-mesh.com> |
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6 | * Copyright (C) 2015 Open-Mesh - Jim Collar <jim.collar@eqware.net> |
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7 | * |
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8 | * This program is free software; you can redistribute it and/or modify it |
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9 | * under the terms of the GNU General Public License version 2 as published |
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10 | * by the Free Software Foundation. |
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11 | */ |
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12 | |||
13 | #include <linux/gpio.h> |
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14 | #include <linux/mtd/mtd.h> |
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15 | #include <linux/mtd/partitions.h> |
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16 | #include <linux/platform_device.h> |
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17 | #include <linux/i2c.h> |
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18 | #include <linux/i2c-algo-bit.h> |
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19 | #include <linux/i2c-gpio.h> |
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20 | #include <linux/platform_data/phy-at803x.h> |
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21 | |||
22 | #include <asm/mach-ath79/ar71xx_regs.h> |
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23 | #include <asm/mach-ath79/ath79.h> |
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24 | |||
25 | #include "common.h" |
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26 | #include "dev-ap9x-pci.h" |
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27 | #include "dev-eth.h" |
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28 | #include "dev-gpio-buttons.h" |
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29 | #include "dev-leds-gpio.h" |
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30 | #include "dev-m25p80.h" |
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31 | #include "dev-wmac.h" |
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32 | #include "machtypes.h" |
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33 | #include "pci.h" |
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34 | |||
35 | #define OM5PACV2_GPIO_LED_POWER 14 |
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36 | #define OM5PACV2_GPIO_LED_GREEN 13 |
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37 | #define OM5PACV2_GPIO_LED_RED 23 |
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38 | #define OM5PACV2_GPIO_LED_YELLOW 15 |
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39 | #define OM5PACV2_GPIO_BTN_RESET 1 |
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40 | #define OM5PACV2_GPIO_I2C_SCL 18 |
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41 | #define OM5PACV2_GPIO_I2C_SDA 19 |
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42 | #define OM5PACV2_GPIO_PA_DCDC 2 |
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43 | #define OM5PACV2_GPIO_PA_HIGH 16 |
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44 | |||
45 | #define OM5PACV2_KEYS_POLL_INTERVAL 20 /* msecs */ |
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46 | #define OM5PACV2_KEYS_DEBOUNCE_INTERVAL (3 * OM5PACV2_KEYS_POLL_INTERVAL) |
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47 | |||
48 | #define OM5PACV2_WMAC_CALDATA_OFFSET 0x1000 |
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49 | |||
50 | static struct gpio_led om5pacv2_leds_gpio[] __initdata = { |
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51 | { |
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52 | .name = "om5pac:blue:power", |
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53 | .gpio = OM5PACV2_GPIO_LED_POWER, |
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54 | .active_low = 1, |
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55 | }, { |
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56 | .name = "om5pac:red:wifi", |
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57 | .gpio = OM5PACV2_GPIO_LED_RED, |
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58 | .active_low = 1, |
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59 | }, { |
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60 | .name = "om5pac:yellow:wifi", |
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61 | .gpio = OM5PACV2_GPIO_LED_YELLOW, |
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62 | .active_low = 1, |
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63 | }, { |
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64 | .name = "om5pac:green:wifi", |
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65 | .gpio = OM5PACV2_GPIO_LED_GREEN, |
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66 | .active_low = 1, |
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67 | } |
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68 | }; |
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69 | |||
70 | static struct gpio_keys_button om5pacv2_gpio_keys[] __initdata = { |
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71 | { |
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72 | .desc = "reset", |
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73 | .type = EV_KEY, |
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74 | .code = KEY_RESTART, |
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75 | .debounce_interval = OM5PACV2_KEYS_DEBOUNCE_INTERVAL, |
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76 | .gpio = OM5PACV2_GPIO_BTN_RESET, |
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77 | .active_low = 1, |
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78 | } |
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79 | }; |
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80 | |||
81 | static struct i2c_gpio_platform_data om5pacv2_i2c_device_platdata = { |
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82 | .sda_pin = OM5PACV2_GPIO_I2C_SDA, |
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83 | .scl_pin = OM5PACV2_GPIO_I2C_SCL, |
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84 | .udelay = 10, |
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85 | .sda_is_open_drain = 1, |
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86 | .scl_is_open_drain = 1, |
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87 | }; |
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88 | |||
89 | static struct platform_device om5pacv2_i2c_device = { |
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90 | .name = "i2c-gpio", |
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91 | .id = 0, |
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92 | .dev = { |
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93 | .platform_data = &om5pacv2_i2c_device_platdata, |
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94 | }, |
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95 | }; |
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96 | |||
97 | static struct i2c_board_info om5pacv2_i2c_devs[] __initdata = { |
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98 | { |
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99 | I2C_BOARD_INFO("tmp423", 0x4e), |
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100 | }, |
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101 | }; |
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102 | |||
103 | static struct flash_platform_data om5pacv2_flash_data = { |
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104 | .type = "mx25l12805d", |
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105 | }; |
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106 | |||
107 | static struct at803x_platform_data om5pacv2_an_at803x_data = { |
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108 | .disable_smarteee = 1, |
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109 | .enable_rgmii_rx_delay = 1, |
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110 | .enable_rgmii_tx_delay = 1, |
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111 | }; |
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112 | |||
113 | static struct at803x_platform_data om5pacv2_an_at8031_data = { |
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114 | .disable_smarteee = 1, |
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115 | .enable_rgmii_rx_delay = 1, |
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116 | .enable_rgmii_tx_delay = 1, |
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117 | }; |
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118 | |||
119 | static struct mdio_board_info om5pacv2_an_mdio0_info[] = { |
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120 | { |
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121 | .bus_id = "ag71xx-mdio.0", |
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122 | .phy_addr = 4, |
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123 | .platform_data = &om5pacv2_an_at803x_data, |
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124 | }, |
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125 | { |
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126 | .bus_id = "ag71xx-mdio.1", |
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127 | .phy_addr = 1, |
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128 | .platform_data = &om5pacv2_an_at8031_data, |
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129 | }, |
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130 | }; |
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131 | |||
132 | static void __init om5p_acv2_setup_qca955x_eth_cfg(u32 mask, |
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133 | unsigned int rxd, |
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134 | unsigned int rxdv, |
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135 | unsigned int txd, |
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136 | unsigned int txe) |
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137 | { |
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138 | void __iomem *base; |
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139 | u32 t; |
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140 | |||
141 | base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); |
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142 | |||
143 | t = mask; |
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144 | t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; |
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145 | t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; |
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146 | t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; |
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147 | t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; |
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148 | |||
149 | __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); |
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150 | |||
151 | iounmap(base); |
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152 | } |
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153 | |||
154 | static void __init om5p_acv2_setup(void) |
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155 | { |
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156 | u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); |
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157 | u8 mac[6]; |
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158 | |||
159 | /* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */ |
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160 | ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE); |
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161 | ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO); |
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162 | ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO); |
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163 | gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH, |
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164 | "PA DC/DC"); |
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165 | gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH"); |
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166 | |||
167 | /* temperature sensor */ |
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168 | platform_device_register(&om5pacv2_i2c_device); |
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169 | i2c_register_board_info(0, om5pacv2_i2c_devs, |
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170 | ARRAY_SIZE(om5pacv2_i2c_devs)); |
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171 | |||
172 | ath79_register_m25p80(&om5pacv2_flash_data); |
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173 | ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio), |
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174 | om5pacv2_leds_gpio); |
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175 | ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL, |
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176 | ARRAY_SIZE(om5pacv2_gpio_keys), |
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177 | om5pacv2_gpio_keys); |
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178 | |||
179 | ath79_init_mac(mac, art, 0x02); |
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180 | ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac); |
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181 | |||
182 | om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0); |
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183 | ath79_register_mdio(0, 0x0); |
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184 | ath79_register_mdio(1, 0x0); |
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185 | |||
186 | mdiobus_register_board_info(om5pacv2_an_mdio0_info, |
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187 | ARRAY_SIZE(om5pacv2_an_mdio0_info)); |
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188 | |||
189 | ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00); |
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190 | ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01); |
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191 | |||
192 | /* GMAC0 is connected to the PHY4 */ |
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193 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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194 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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195 | ath79_eth0_data.phy_mask = BIT(4); |
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196 | ath79_eth0_pll_data.pll_1000 = 0x82000101; |
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197 | ath79_eth0_pll_data.pll_100 = 0x80000101; |
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198 | ath79_eth0_pll_data.pll_10 = 0x80001313; |
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199 | ath79_register_eth(0); |
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200 | |||
201 | /* GMAC1 is connected to MDIO1 in SGMII mode */ |
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202 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
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203 | ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; |
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204 | ath79_eth1_data.phy_mask = BIT(1); |
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205 | ath79_eth1_pll_data.pll_1000 = 0x03000101; |
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206 | ath79_eth1_pll_data.pll_100 = 0x80000101; |
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207 | ath79_eth1_pll_data.pll_10 = 0x80001313; |
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208 | ath79_eth1_data.speed = SPEED_1000; |
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209 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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210 | ath79_register_eth(1); |
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211 | |||
212 | ath79_register_pci(); |
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213 | } |
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214 | |||
215 | MIPS_MACHINE(ATH79_MACH_OM5P_ACv2, "OM5P-ACv2", "OpenMesh OM5P ACv2", om5p_acv2_setup); |