OpenWrt – Blame information for rev 4

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4 office 1 /*
2 * Atheros AR934X SoCs built-in NAND flash controller support
3 *
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10  
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/irq.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/platform/ar934x_nfc.h>
19  
20 #include <asm/mach-ath79/ath79.h>
21 #include <asm/mach-ath79/ar71xx_regs.h>
22  
23 #include "dev-nfc.h"
24  
25 static struct resource ath79_nfc_resources[2];
26 static u64 ar934x_nfc_dmamask = DMA_BIT_MASK(32);
27 static struct ar934x_nfc_platform_data ath79_nfc_data;
28  
29 static struct platform_device ath79_nfc_device = {
30 .name = AR934X_NFC_DRIVER_NAME,
31 .id = -1,
32 .resource = ath79_nfc_resources,
33 .num_resources = ARRAY_SIZE(ath79_nfc_resources),
34 .dev = {
35 .dma_mask = &ar934x_nfc_dmamask,
36 .coherent_dma_mask = DMA_BIT_MASK(32),
37 .platform_data = &ath79_nfc_data,
38 },
39 };
40  
41 static void __init ath79_nfc_init_resource(struct resource res[2],
42 unsigned long base,
43 unsigned long size,
44 int irq)
45 {
46 memset(res, 0, sizeof(struct resource) * 2);
47  
48 res[0].flags = IORESOURCE_MEM;
49 res[0].start = base;
50 res[0].end = base + size - 1;
51  
52 res[1].flags = IORESOURCE_IRQ;
53 res[1].start = irq;
54 res[1].end = irq;
55 }
56  
57 static void ar934x_nfc_hw_reset(bool active)
58 {
59 if (active) {
60 ath79_device_reset_set(AR934X_RESET_NANDF);
61 udelay(100);
62  
63 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH_ANALOG);
64 udelay(250);
65 } else {
66 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH_ANALOG);
67 udelay(250);
68  
69 ath79_device_reset_clear(AR934X_RESET_NANDF);
70 udelay(100);
71 }
72 }
73  
74 static void ar934x_nfc_setup(void)
75 {
76 ath79_nfc_data.hw_reset = ar934x_nfc_hw_reset;
77  
78 ath79_nfc_init_resource(ath79_nfc_resources,
79 AR934X_NFC_BASE, AR934X_NFC_SIZE,
80 ATH79_MISC_IRQ(21));
81  
82 platform_device_register(&ath79_nfc_device);
83 }
84  
85 static void qca955x_nfc_hw_reset(bool active)
86 {
87 if (active) {
88 ath79_device_reset_set(QCA955X_RESET_NANDF);
89 udelay(250);
90 } else {
91 ath79_device_reset_clear(QCA955X_RESET_NANDF);
92 udelay(100);
93 }
94 }
95  
96 static void qca955x_nfc_setup(void)
97 {
98 ath79_nfc_data.hw_reset = qca955x_nfc_hw_reset;
99  
100 ath79_nfc_init_resource(ath79_nfc_resources,
101 QCA955X_NFC_BASE, QCA955X_NFC_SIZE,
102 ATH79_MISC_IRQ(21));
103  
104 platform_device_register(&ath79_nfc_device);
105 }
106  
107 void __init ath79_nfc_set_select_chip(void (*f)(int chip_no))
108 {
109 ath79_nfc_data.select_chip = f;
110 }
111  
112 void __init ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd))
113 {
114 ath79_nfc_data.scan_fixup = f;
115 }
116  
117 void __init ath79_nfc_set_swap_dma(bool enable)
118 {
119 ath79_nfc_data.swap_dma = enable;
120 }
121  
122 void __init ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode)
123 {
124 ath79_nfc_data.ecc_mode = mode;
125 }
126  
127 void __init ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts)
128 {
129 ath79_nfc_data.parts = parts;
130 ath79_nfc_data.nr_parts = nr_parts;
131 }
132  
133 void __init ath79_register_nfc(void)
134 {
135 if (soc_is_ar934x())
136 ar934x_nfc_setup();
137 else if (soc_is_qca955x())
138 qca955x_nfc_setup();
139 else
140 BUG();
141 }