OpenWrt – Blame information for rev 4

Subversion Repositories:
Rev:
Rev Author Line No. Line
4 office 1 --- a/drivers/net/wireless/ath/ath9k/hw.c
2 +++ b/drivers/net/wireless/ath/ath9k/hw.c
3 @@ -246,6 +246,19 @@ void ath9k_hw_get_channel_centers(struct
4 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
5 }
6  
7 +static inline void ath9k_hw_disable_pll_lock_detect(struct ath_hw *ah)
8 +{
9 + /* On AR9330 and AR9340 devices, some PHY registers must be
10 + * tuned to gain better stability/performance. These registers
11 + * might be changed while doing wlan reset so the registers must
12 + * be reprogrammed after each reset.
13 + */
14 + REG_CLR_BIT(ah, AR_PHY_USB_CTRL1, BIT(20));
15 + REG_RMW(ah, AR_PHY_USB_CTRL2,
16 + (1 << 21) | (0xf << 22),
17 + (1 << 21) | (0x3 << 22));
18 +}
19 +
20 /******************/
21 /* Chip Revisions */
22 /******************/
23 @@ -1414,6 +1427,9 @@ static bool ath9k_hw_set_reset(struct at
24 udelay(50);
25 }
26  
27 + if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
28 + ath9k_hw_disable_pll_lock_detect(ah);
29 +
30 return true;
31 }
32  
33 @@ -1513,6 +1529,9 @@ static bool ath9k_hw_chip_reset(struct a
34 ar9003_hw_internal_regulator_apply(ah);
35 ath9k_hw_init_pll(ah, chan);
36  
37 + if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
38 + ath9k_hw_disable_pll_lock_detect(ah);
39 +
40 return true;
41 }
42  
43 @@ -1820,8 +1839,14 @@ static int ath9k_hw_do_fastcc(struct ath
44 if (AR_SREV_9271(ah))
45 ar9002_hw_load_ani_reg(ah, chan);
46  
47 + if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
48 + ath9k_hw_disable_pll_lock_detect(ah);
49 +
50 return 0;
51 fail:
52 + if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
53 + ath9k_hw_disable_pll_lock_detect(ah);
54 +
55 return -EINVAL;
56 }
57  
58 @@ -2075,6 +2100,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
59 ath9k_hw_set_radar_params(ah);
60 }
61  
62 + if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
63 + ath9k_hw_disable_pll_lock_detect(ah);
64 +
65 return 0;
66 }
67 EXPORT_SYMBOL(ath9k_hw_reset);
68 --- a/drivers/net/wireless/ath/ath9k/phy.h
69 +++ b/drivers/net/wireless/ath/ath9k/phy.h
70 @@ -48,6 +48,9 @@
71 #define AR_PHY_PLL_CONTROL 0x16180
72 #define AR_PHY_PLL_MODE 0x16184
73  
74 +#define AR_PHY_USB_CTRL1 0x16c84
75 +#define AR_PHY_USB_CTRL2 0x16c88
76 +
77 enum ath9k_ant_div_comb_lna_conf {
78 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
79 ATH_ANT_DIV_COMB_LNA2,