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4 office 1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_deu.h
4 ** DESCRIPTION : Data Encryption Unit Driver
5 ** COPYRIGHT : Copyright (c) 2009
6 ** Infineon Technologies AG
7 ** Am Campeon 1-12, 85579 Neubiberg, Germany
8 **
9 ** This program is free software; you can redistribute it and/or modify
10 ** it under the terms of the GNU General Public License as published by
11 ** the Free Software Foundation; either version 2 of the License, or
12 ** (at your option) any later version.
13 **
14 ** HISTORY
15 ** $Date $Author $Comment
16 ** 08,Sept 2009 Mohammad Firdaus Initial UEIP release
17 *******************************************************************************/
18 /*!
19 \defgroup IFX_DEU IFX_DEU_DRIVERS
20 \ingroup API
21 \brief ifx deu driver module
22 */
23  
24 /*!
25 \file ifxmips_deu.h
26 \brief main deu driver header file
27 */
28  
29 /*!
30 \defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS
31 \ingroup IFX_DEU
32 \brief ifx deu definitions
33 */
34  
35  
36 #ifndef IFXMIPS_DEU_H
37 #define IFXMIPS_DEU_H
38  
39 #include <crypto/algapi.h>
40 #include <linux/interrupt.h>
41  
42 #define IFXDEU_ALIGNMENT 16
43  
44 #define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100)
45 #define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000))
46 #define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010))
47 #define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050))
48 #define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0))
49 #define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100))
50  
51 #define PFX "ifxdeu: "
52 #define CLC_START IFX_DEU_CLK
53 #define IFXDEU_CRA_PRIORITY 300
54 #define IFXDEU_COMPOSITE_PRIORITY 400
55 //#define KSEG1 0xA0000000
56 #define IFX_PMU_ENABLE 1
57 #define IFX_PMU_DISABLE 0
58  
59 #define CRYPTO_DIR_ENCRYPT 1
60 #define CRYPTO_DIR_DECRYPT 0
61  
62 #define AES_IDLE 0
63 #define AES_BUSY 1
64 #define AES_STARTED 2
65 #define AES_COMPLETED 3
66 #define DES_IDLE 0
67 #define DES_BUSY 1
68 #define DES_STARTED 2
69 #define DES_COMPLETED 3
70  
71 #define PROCESS_SCATTER 1
72 #define PROCESS_NEW_PACKET 2
73  
74 #define PMU_DEU BIT(20)
75 #define START_DEU_POWER \
76 do { \
77 volatile struct clc_controlr_t *clc = (struct clc_controlr_t *) CLC_START; \
78 ltq_pmu_enable(PMU_DEU); \
79 clc->FSOE = 0; \
80 clc->SBWE = 0; \
81 clc->SPEN = 0; \
82 clc->SBWE = 0; \
83 clc->DISS = 0; \
84 clc->DISR = 0; \
85 } while(0)
86  
87 #define STOP_DEU_POWER \
88 do { \
89 volatile struct clc_controlr_t *clc = (struct clc_controlr_t *) CLC_START; \
90 ltq_pmu_disable(PMU_DEU); \
91 clc->FSOE = 1; \
92 clc->SBWE = 1; \
93 clc->SPEN = 1; \
94 clc->SBWE = 1; \
95 clc->DISS = 1; \
96 clc->DISR = 1; \
97 } while (0)
98  
99 /*
100 * Not used anymore in UEIP (use IFX_DES_CON, IFX_AES_CON, etc instead)
101 * #define DEU_BASE (KSEG1+0x1E103100)
102 * #define DES_CON (DEU_BASE+0x10)
103 * #define AES_CON (DEU_BASE+0x50)
104 * #define HASH_CON (DEU_BASE+0xB0)
105 * #define DMA_CON (DEU_BASE+0xEC)
106 * #define INT_CON (DEU_BASE+0xF4)
107 * #define ARC4_CON (DEU_BASE+0x100)
108 */
109  
110  
111 int ifxdeu_init_des (void);
112 int ifxdeu_init_aes (void);
113 int ifxdeu_init_arc4 (void);
114 int ifxdeu_init_sha1 (void);
115 int ifxdeu_init_md5 (void);
116 int ifxdeu_init_sha1_hmac (void);
117 int ifxdeu_init_md5_hmac (void);
118 int __init lqdeu_async_aes_init(void);
119 int __init lqdeu_async_des_init(void);
120  
121 void ifxdeu_fini_des (void);
122 void ifxdeu_fini_aes (void);
123 void ifxdeu_fini_arc4 (void);
124 void ifxdeu_fini_sha1 (void);
125 void ifxdeu_fini_md5 (void);
126 void ifxdeu_fini_sha1_hmac (void);
127 void ifxdeu_fini_md5_hmac (void);
128 void __exit ifxdeu_fini_dma(void);
129 void __exit lqdeu_fini_async_aes(void);
130 void __exit lqdeu_fini_async_des(void);
131 void __exit deu_fini (void);
132 int deu_dma_init (void);
133  
134  
135  
136 #define DEU_WAKELIST_INIT(queue) \
137 init_waitqueue_head(&queue)
138  
139 #define DEU_WAIT_EVENT_TIMEOUT(queue, event, flags, timeout) \
140 do { \
141 wait_event_interruptible_timeout((queue), \
142 test_bit((event), &(flags)), (timeout)); \
143 clear_bit((event), &(flags)); \
144 }while (0)
145  
146  
147 #define DEU_WAKEUP_EVENT(queue, event, flags) \
148 do { \
149 set_bit((event), &(flags)); \
150 wake_up_interruptible(&(queue)); \
151 }while (0)
152  
153 #define DEU_WAIT_EVENT(queue, event, flags) \
154 do { \
155 wait_event_interruptible(queue, \
156 test_bit((event), &(flags))); \
157 clear_bit((event), &(flags)); \
158 }while (0)
159  
160 typedef struct deu_drv_priv {
161 wait_queue_head_t deu_thread_wait;
162 #define DEU_EVENT 1
163 #define DES_ASYNC_EVENT 2
164 #define AES_ASYNC_EVENT 3
165 volatile long des_event_flags;
166 volatile long aes_event_flags;
167 volatile long deu_event_flags;
168 int event_src;
169 u32 *deu_rx_buf;
170 u32 *outcopy;
171 u32 deu_rx_len;
172  
173 struct aes_priv *aes_dataptr;
174 struct des_priv *des_dataptr;
175 }deu_drv_priv_t;
176  
177  
178 /**
179 * struct aes_priv_t - ASYNC AES
180 * @lock: spinlock lock
181 * @lock_flag: flag for spinlock activities
182 * @list: crypto queue API list
183 * @hw_status: DEU hw status flag
184 * @aes_wait_flag: flag for sleep queue
185 * @aes_wait_queue: queue attributes for aes
186 * @bytes_processed: number of bytes to process by DEU
187 * @aes_pid: pid number for AES thread
188 * @aes_sync: atomic wait sync for AES
189 *
190 */
191  
192 typedef struct {
193 spinlock_t lock;
194 struct crypto_queue list;
195 unsigned int hw_status;
196 volatile long aes_wait_flag;
197 wait_queue_head_t aes_wait_queue;
198  
199 pid_t aes_pid;
200  
201 struct tasklet_struct aes_task;
202  
203 } aes_priv_t;
204  
205 /**
206 * struct des_priv_t - ASYNC DES
207 * @lock: spinlock lock
208 * @list: crypto queue API list
209 * @hw_status: DEU hw status flag
210 * @des_wait_flag: flag for sleep queue
211 * @des_wait_queue: queue attributes for des
212 * @des_pid: pid number for DES thread
213 * @des_sync: atomic wait sync for DES
214 *
215 */
216  
217 typedef struct {
218 spinlock_t lock;
219 struct crypto_queue list;
220 unsigned int hw_status;
221 volatile long des_wait_flag;
222 wait_queue_head_t des_wait_queue;
223  
224 pid_t des_pid;
225  
226 struct tasklet_struct des_task;
227  
228 } des_priv_t;
229  
230 #endif /* IFXMIPS_DEU_H */
231  
232