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4 office 1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_atm_fw_regs_vr9.h
4 ** PROJECT : UEIP
5 ** MODULES : ATM (ADSL)
6 **
7 ** DATE : 1 AUG 2005
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : ATM Driver (Firmware Registers)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 4 AUG 2005 Xu Liang Initiate Version
22 ** 23 OCT 2006 Xu Liang Add GPL header.
23 ** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
24 *******************************************************************************/
25  
26  
27  
28 #ifndef IFXMIPS_ATM_FW_REGS_VR9_H
29 #define IFXMIPS_ATM_FW_REGS_VR9_H
30  
31 #define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001))
32  
33 /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
34 #define CFG_WRX_HTUTS SB_BUFFER(0x2010)
35 /* WAN RX Queue Number */
36 #define CFG_WRX_QNUM SB_BUFFER(0x2011)
37 /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
38 #define CFG_WRX_DCHNUM SB_BUFFER(0x2012)
39 /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
40 #define CFG_WTX_DCHNUM SB_BUFFER(0x2013)
41 /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
42 #define CFG_WRDES_DELAY SB_BUFFER(0x2014)
43 /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */
44 #define WRX_DMACH_ON SB_BUFFER(0x2015)
45 /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */
46 #define WTX_DMACH_ON SB_BUFFER(0x2016)
47 /* WAN RX HUNT Threshold, must be between 2 to 8. */
48 #define WRX_HUNT_BITTH SB_BUFFER(0x2017)
49 /* i < 16 */
50 #define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config *) SB_BUFFER(0x4C00 + (i) * 20))
51 /* i < 8 */
52 #define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config *) SB_BUFFER(0x4F80 + (i) * 7))
53 /* i < 2 */
54 #define WTX_PORT_CONFIG(i) ((struct wtx_port_config *) SB_BUFFER(0x4FB8 + (i)))
55 /* i < 16 */
56 #define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config *) SB_BUFFER(0x3A00 + (i) * 27))
57 /* i < 16 */
58 #define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config *) SB_BUFFER(0x3A01 + (i) * 27))
59  
60 #define WAN_MIB_TABLE ((struct wan_mib_table *) SB_BUFFER(0x4EF0))
61 /* i < 32 */
62 #define HTU_ENTRY(i) ((struct htu_entry *) SB_BUFFER(0x26A0 + (i)))
63 /* i < 32 */
64 #define HTU_MASK(i) ((struct htu_mask *) SB_BUFFER(0x26C0 + (i)))
65 /* i < 32 */
66 #define HTU_RESULT(i) ((struct htu_result *) SB_BUFFER(0x26E0 + (i)))
67 /* bit 0~3 - 0x0F: in showtime, 0x00: not in showtime */
68 #define UTP_CFG SB_BUFFER(0x2018)
69  
70  
71  
72 #endif // IFXMIPS_ATM_FW_REGS_VR9_H