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4 office 1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_atm_ar9.c
4 ** PROJECT : UEIP
5 ** MODULES : ATM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
23  
24  
25  
26 /*
27 * ####################################
28 * Head File
29 * ####################################
30 */
31  
32 /*
33 * Common Head File
34 */
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <asm/delay.h>
44  
45 /*
46 * Chip Specific Head File
47 */
48 #include "ifxmips_atm_core.h"
49  
50 #include "ifxmips_atm_fw_ar9.h"
51 #include "ifxmips_atm_fw_regs_ar9.h"
52  
53 #include <lantiq_soc.h>
54  
55  
56  
57 /*
58 * ####################################
59 * Definition
60 * ####################################
61 */
62  
63 /*
64 * EMA Settings
65 */
66 #define EMA_CMD_BUF_LEN 0x0040
67 #define EMA_CMD_BASE_ADDR (0x00003B80 << 2)
68 #define EMA_DATA_BUF_LEN 0x0100
69 #define EMA_DATA_BASE_ADDR (0x00003C00 << 2)
70 #define EMA_WRITE_BURST 0x2
71 #define EMA_READ_BURST 0x2
72  
73  
74  
75 /*
76 * ####################################
77 * Declaration
78 * ####################################
79 */
80  
81 /*
82 * Hardware Init/Uninit Functions
83 */
84 static inline void init_pmu(void);
85 static inline void uninit_pmu(void);
86 static inline void reset_ppe(void);
87 static inline void init_ema(void);
88 static inline void init_mailbox(void);
89 static inline void clear_share_buffer(void);
90  
91  
92  
93 /*
94 * ####################################
95 * Local Variable
96 * ####################################
97 */
98  
99  
100  
101 /*
102 * ####################################
103 * Local Function
104 * ####################################
105 */
106  
107 #define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
108 #define IFX_PMU_MODULE_PPE_TC BIT(21)
109 #define IFX_PMU_MODULE_PPE_EMA BIT(22)
110 #define IFX_PMU_MODULE_PPE_QSB BIT(18)
111 #define IFX_PMU_MODULE_TPE BIT(13)
112 #define IFX_PMU_MODULE_DSL_DFE BIT(9)
113  
114 static inline void init_pmu(void)
115 {
116 ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
117 IFX_PMU_MODULE_PPE_TC |
118 IFX_PMU_MODULE_PPE_EMA |
119 IFX_PMU_MODULE_PPE_QSB |
120 IFX_PMU_MODULE_TPE |
121 IFX_PMU_MODULE_DSL_DFE);
122 }
123  
124 static inline void uninit_pmu(void)
125 {
126 }
127  
128 static inline void reset_ppe(void)
129 {
130 #ifdef MODULE
131 // reset PPE
132 // ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
133 #endif
134 }
135  
136 static inline void init_ema(void)
137 {
138 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
139 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
140 IFX_REG_W32(0x000000FF, EMA_IER);
141 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
142 }
143  
144 static inline void init_mailbox(void)
145 {
146 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
147 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
148 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
149 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
150 }
151  
152 static inline void clear_share_buffer(void)
153 {
154 volatile u32 *p = SB_RAM0_ADDR(0);
155 unsigned int i;
156  
157 for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN + SB_RAM4_DWLEN; i++ )
158 IFX_REG_W32(0, p++);
159 }
160  
161 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
162 {
163 volatile u32 *dest;
164  
165 if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
166 || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
167 return -1;
168  
169 if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
170 IFX_REG_W32(0x00, CDM_CFG);
171 else
172 IFX_REG_W32(0x04, CDM_CFG);
173  
174 /* copy code */
175 dest = CDM_CODE_MEMORY(0, 0);
176 while ( code_dword_len-- > 0 )
177 IFX_REG_W32(*code_src++, dest++);
178  
179 /* copy data */
180 dest = CDM_DATA_MEMORY(0, 0);
181 while ( data_dword_len-- > 0 )
182 IFX_REG_W32(*data_src++, dest++);
183  
184 return 0;
185 }
186  
187 void ar9_fw_ver(unsigned int *major, unsigned int *minor)
188 {
189 ASSERT(major != NULL, "pointer is NULL");
190 ASSERT(minor != NULL, "pointer is NULL");
191  
192 *major = FW_VER_ID->major;
193 *minor = FW_VER_ID->minor;
194 }
195  
196 void ar9_init(void)
197 {
198 init_pmu();
199 reset_ppe();
200 init_ema();
201 init_mailbox();
202 clear_share_buffer();
203 }
204  
205 void ar9_shutdown(void)
206 {
207 ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 |
208 IFX_PMU_MODULE_PPE_TC |
209 IFX_PMU_MODULE_PPE_EMA |
210 IFX_PMU_MODULE_PPE_QSB |
211 IFX_PMU_MODULE_TPE |
212 IFX_PMU_MODULE_DSL_DFE);
213 }
214  
215 int ar9_start(int pp32)
216 {
217 int ret;
218  
219 ret = pp32_download_code(ar9_fw_bin, sizeof(ar9_fw_bin) / sizeof(*ar9_fw_bin),
220 ar9_fw_data, sizeof(ar9_fw_data) / sizeof(*ar9_fw_data));
221 if ( ret != 0 )
222 return ret;
223  
224 IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
225  
226 udelay(10);
227  
228 return 0;
229 }
230  
231 void ar9_stop(int pp32)
232 {
233 IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));
234 }
235  
236 struct ltq_atm_ops ar9_ops = {
237 .init = ar9_init,
238 .shutdown = ar9_shutdown,
239 .start = ar9_start,
240 .stop = ar9_stop,
241 .fw_ver = ar9_fw_ver,
242 };
243  
244