OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | #ifndef _NAS782X_SYSCTL_H |
2 | #define _NAS782X_SYSCTL_H |
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3 | |||
4 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
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5 | #include <asm/types.h> |
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6 | #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ |
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7 | |||
8 | #include <asm/arch/hardware.h> |
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9 | |||
10 | /** |
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11 | * System block reset and clock control |
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12 | */ |
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13 | #define SYS_CTRL_PCI_STAT (SYS_CONTROL_BASE + 0x20) |
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14 | #define SYS_CTRL_CLK_SET_CTRL (SYS_CONTROL_BASE + 0x2C) |
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15 | #define SYS_CTRL_CLK_CLR_CTRL (SYS_CONTROL_BASE + 0x30) |
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16 | #define SYS_CTRL_RST_SET_CTRL (SYS_CONTROL_BASE + 0x34) |
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17 | #define SYS_CTRL_RST_CLR_CTRL (SYS_CONTROL_BASE + 0x38) |
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18 | #define SYS_CTRL_PLLSYS_CTRL (SYS_CONTROL_BASE + 0x48) |
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19 | #define SYS_CTRL_PLLSYS_KEY_CTRL (SYS_CONTROL_BASE + 0x6C) |
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20 | #define SYS_CTRL_GMAC_CTRL (SYS_CONTROL_BASE + 0x78) |
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21 | |||
22 | /* Scratch registers */ |
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23 | #define SYS_CTRL_SCRATCHWORD0 (SYS_CONTROL_BASE + 0xc4) |
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24 | #define SYS_CTRL_SCRATCHWORD1 (SYS_CONTROL_BASE + 0xc8) |
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25 | #define SYS_CTRL_SCRATCHWORD2 (SYS_CONTROL_BASE + 0xcc) |
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26 | #define SYS_CTRL_SCRATCHWORD3 (SYS_CONTROL_BASE + 0xd0) |
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27 | |||
28 | #define SYS_CTRL_PLLA_CTRL0 (SYS_CONTROL_BASE + 0x1F0) |
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29 | #define SYS_CTRL_PLLA_CTRL1 (SYS_CONTROL_BASE + 0x1F4) |
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30 | #define SYS_CTRL_PLLA_CTRL2 (SYS_CONTROL_BASE + 0x1F8) |
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31 | #define SYS_CTRL_PLLA_CTRL3 (SYS_CONTROL_BASE + 0x1FC) |
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32 | |||
33 | #define SYS_CTRL_GMAC_AUTOSPEED 3 |
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34 | #define SYS_CTRL_GMAC_RGMII 2 |
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35 | #define SYS_CTRL_GMAC_SIMPLE_MUX 1 |
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36 | #define SYS_CTRL_GMAC_CKEN_GTX 0 |
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37 | |||
38 | #define SYS_CTRL_CKCTRL_CTRL_ADDR (SYS_CONTROL_BASE + 0x64) |
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39 | |||
40 | #define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0 |
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41 | #define SYS_CTRL_CKCTRL_SLOW_BIT 8 |
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42 | |||
43 | |||
44 | #define SYS_CTRL_USBHSMPH_CTRL (SYS_CONTROL_BASE + 0x40) |
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45 | #define SYS_CTRL_USBHSMPH_STAT (SYS_CONTROL_BASE + 0x44) |
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46 | #define SYS_CTRL_REF300_DIV (SYS_CONTROL_BASE + 0xF8) |
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47 | #define SYS_CTRL_USBHSPHY_CTRL (SYS_CONTROL_BASE + 0x84) |
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48 | #define SYS_CTRL_USB_CTRL (SYS_CONTROL_BASE + 0x90) |
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49 | |||
50 | /* System control multi-function pin function selection */ |
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51 | #define SYS_CTRL_SECONDARY_SEL (SYS_CONTROL_BASE + 0x14) |
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52 | #define SYS_CTRL_TERTIARY_SEL (SYS_CONTROL_BASE + 0x8c) |
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53 | #define SYS_CTRL_QUATERNARY_SEL (SYS_CONTROL_BASE + 0x94) |
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54 | #define SYS_CTRL_DEBUG_SEL (SYS_CONTROL_BASE + 0x9c) |
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55 | #define SYS_CTRL_ALTERNATIVE_SEL (SYS_CONTROL_BASE + 0xa4) |
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56 | #define SYS_CTRL_PULLUP_SEL (SYS_CONTROL_BASE + 0xac) |
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57 | |||
58 | /* Secure control multi-function pin function selection */ |
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59 | #define SEC_CTRL_SECONDARY_SEL (SEC_CONTROL_BASE + 0x14) |
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60 | #define SEC_CTRL_TERTIARY_SEL (SEC_CONTROL_BASE + 0x8c) |
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61 | #define SEC_CTRL_QUATERNARY_SEL (SEC_CONTROL_BASE + 0x94) |
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62 | #define SEC_CTRL_DEBUG_SEL (SEC_CONTROL_BASE + 0x9c) |
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63 | #define SEC_CTRL_ALTERNATIVE_SEL (SEC_CONTROL_BASE + 0xa4) |
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64 | #define SEC_CTRL_PULLUP_SEL (SEC_CONTROL_BASE + 0xac) |
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65 | |||
66 | #define SEC_CTRL_COPRO_CTRL (SEC_CONTROL_BASE + 0x68) |
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67 | #define SEC_CTRL_SECURE_CTRL (SEC_CONTROL_BASE + 0x98) |
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68 | #define SEC_CTRL_LEON_DEBUG (SEC_CONTROL_BASE + 0xF0) |
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69 | #define SEC_CTRL_PLLB_DIV_CTRL (SEC_CONTROL_BASE + 0xF8) |
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70 | #define SEC_CTRL_PLLB_CTRL0 (SEC_CONTROL_BASE + 0x1F0) |
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71 | #define SEC_CTRL_PLLB_CTRL1 (SEC_CONTROL_BASE + 0x1F4) |
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72 | #define SEC_CTRL_PLLB_CTRL8 (SEC_CONTROL_BASE + 0x1F4) |
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73 | |||
74 | #define REF300_DIV_INT_SHIFT 8 |
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75 | #define REF300_DIV_FRAC_SHIFT 0 |
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76 | #define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) |
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77 | #define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) |
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78 | |||
79 | #define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16 |
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80 | #define USBHSPHY_SUSPENDM_MANUAL_STATE 15 |
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81 | #define USBHSPHY_ATE_ESET 14 |
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82 | #define USBHSPHY_TEST_DIN 6 |
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83 | #define USBHSPHY_TEST_ADD 2 |
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84 | #define USBHSPHY_TEST_DOUT_SEL 1 |
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85 | #define USBHSPHY_TEST_CLK 0 |
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86 | |||
87 | #define USB_CTRL_USBAPHY_CKSEL_SHIFT 5 |
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88 | #define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT) |
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89 | #define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT) |
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90 | #define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT) |
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91 | |||
92 | #define USBAMUX_DEVICE BIT(4) |
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93 | |||
94 | #define USBPHY_REFCLKDIV_SHIFT 2 |
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95 | #define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT) |
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96 | #define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT) |
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97 | #define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT) |
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98 | |||
99 | #define USB_CTRL_USB_CKO_SEL_BIT 0 |
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100 | |||
101 | #define USB_INT_CLK_XTAL 0 |
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102 | #define USB_INT_CLK_REF300 2 |
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103 | #define USB_INT_CLK_PLLB 3 |
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104 | |||
105 | #define SYS_CTRL_GMAC_AUTOSPEED 3 |
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106 | #define SYS_CTRL_GMAC_RGMII 2 |
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107 | #define SYS_CTRL_GMAC_SIMPLE_MUX 1 |
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108 | #define SYS_CTRL_GMAC_CKEN_GTX 0 |
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109 | |||
110 | |||
111 | #define PLLB_ENSAT 3 |
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112 | #define PLLB_OUTDIV 4 |
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113 | #define PLLB_REFDIV 8 |
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114 | #define PLLB_DIV_INT_SHIFT 8 |
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115 | #define PLLB_DIV_FRAC_SHIFT 0 |
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116 | #define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT) |
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117 | #define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT) |
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118 | |||
119 | #ifndef __KERNEL_STRICT_NAMES |
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120 | #ifndef __ASSEMBLY__ |
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121 | |||
122 | #endif /* __ASSEMBLY__ */ |
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123 | #endif /* __KERNEL_STRICT_NAMES */ |
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124 | |||
125 | #endif /* _NAS782X_SYSCTL_H */ |