OpenWrt – Blame information for rev 4
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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4 | office | 1 | #ifndef _NAS782X_CLOCK_H |
| 2 | #define _NAS782X_CLOCK_H |
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| 3 | |||
| 4 | #include <asm/arch/sysctl.h> |
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| 5 | #include <asm/arch/cpu.h> |
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| 6 | |||
| 7 | /* bit numbers of clock control register */ |
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| 8 | #define SYS_CTRL_CLK_COPRO 0 |
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| 9 | #define SYS_CTRL_CLK_DMA 1 |
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| 10 | #define SYS_CTRL_CLK_CIPHER 2 |
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| 11 | #define SYS_CTRL_CLK_SD 3 |
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| 12 | #define SYS_CTRL_CLK_SATA 4 |
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| 13 | #define SYS_CTRL_CLK_I2S 5 |
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| 14 | #define SYS_CTRL_CLK_USBHS 6 |
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| 15 | #define SYS_CTRL_CLK_MACA 7 |
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| 16 | #define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA |
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| 17 | #define SYS_CTRL_CLK_PCIEA 8 |
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| 18 | #define SYS_CTRL_CLK_STATIC 9 |
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| 19 | #define SYS_CTRL_CLK_MACB 10 |
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| 20 | #define SYS_CTRL_CLK_PCIEB 11 |
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| 21 | #define SYS_CTRL_CLK_REF600 12 |
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| 22 | #define SYS_CTRL_CLK_USBDEV 13 |
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| 23 | #define SYS_CTRL_CLK_DDR 14 |
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| 24 | #define SYS_CTRL_CLK_DDRPHY 15 |
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| 25 | #define SYS_CTRL_CLK_DDRCK 16 |
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| 26 | |||
| 27 | /* bit numbers of reset control register */ |
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| 28 | #define SYS_CTRL_RST_SCU 0 |
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| 29 | #define SYS_CTRL_RST_COPRO 1 |
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| 30 | #define SYS_CTRL_RST_ARM0 2 |
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| 31 | #define SYS_CTRL_RST_ARM1 3 |
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| 32 | #define SYS_CTRL_RST_USBHS 4 |
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| 33 | #define SYS_CTRL_RST_USBHSPHYA 5 |
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| 34 | #define SYS_CTRL_RST_MACA 6 |
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| 35 | #define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA |
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| 36 | #define SYS_CTRL_RST_PCIEA 7 |
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| 37 | #define SYS_CTRL_RST_SGDMA 8 |
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| 38 | #define SYS_CTRL_RST_CIPHER 9 |
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| 39 | #define SYS_CTRL_RST_DDR 10 |
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| 40 | #define SYS_CTRL_RST_SATA 11 |
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| 41 | #define SYS_CTRL_RST_SATA_LINK 12 |
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| 42 | #define SYS_CTRL_RST_SATA_PHY 13 |
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| 43 | #define SYS_CTRL_RST_PCIEPHY 14 |
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| 44 | #define SYS_CTRL_RST_STATIC 15 |
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| 45 | #define SYS_CTRL_RST_GPIO 16 |
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| 46 | #define SYS_CTRL_RST_UART1 17 |
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| 47 | #define SYS_CTRL_RST_UART2 18 |
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| 48 | #define SYS_CTRL_RST_MISC 19 |
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| 49 | #define SYS_CTRL_RST_I2S 20 |
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| 50 | #define SYS_CTRL_RST_SD 21 |
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| 51 | #define SYS_CTRL_RST_MACB 22 |
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| 52 | #define SYS_CTRL_RST_PCIEB 23 |
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| 53 | #define SYS_CTRL_RST_VIDEO 24 |
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| 54 | #define SYS_CTRL_RST_DDR_PHY 25 |
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| 55 | #define SYS_CTRL_RST_USBHSPHYB 26 |
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| 56 | #define SYS_CTRL_RST_USBDEV 27 |
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| 57 | #define SYS_CTRL_RST_ARMDBG 29 |
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| 58 | #define SYS_CTRL_RST_PLLA 30 |
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| 59 | #define SYS_CTRL_RST_PLLB 31 |
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| 60 | |||
| 61 | static inline void reset_block(int block, int reset) |
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| 62 | { |
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| 63 | u32 reg; |
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| 64 | if (reset) |
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| 65 | reg = SYS_CTRL_RST_SET_CTRL; |
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| 66 | else |
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| 67 | reg = SYS_CTRL_RST_CLR_CTRL; |
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| 68 | |||
| 69 | writel(BIT(block), reg); |
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| 70 | } |
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| 71 | |||
| 72 | static inline void enable_clock(int block) |
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| 73 | { |
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| 74 | writel(BIT(block), SYS_CTRL_CLK_SET_CTRL); |
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| 75 | } |
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| 76 | |||
| 77 | static inline void disable_clock(int block) |
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| 78 | { |
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| 79 | writel(BIT(block), SYS_CTRL_CLK_CLR_CTRL); |
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| 80 | } |
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| 81 | |||
| 82 | int plla_set_config(int idx); |
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| 83 | |||
| 84 | #endif /* _NAS782X_CLOCK_H */ |