OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | #include <common.h> |
2 | #include <asm/arch/sysctl.h> |
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3 | #include <asm/arch/pinmux.h> |
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4 | #include <asm/arch/clock.h> |
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5 | |||
6 | void reset_cpu(ulong addr) |
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7 | { |
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8 | u32 value; |
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9 | |||
10 | // Assert reset to cores as per power on defaults |
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11 | // Don't touch the DDR interface as things will come to an impromptu stop |
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12 | // NB Possibly should be asserting reset for PLLB, but there are timing |
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13 | // concerns here according to the docs |
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14 | |||
15 | value = |
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16 | BIT(SYS_CTRL_RST_COPRO ) | |
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17 | BIT(SYS_CTRL_RST_USBHS ) | |
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18 | BIT(SYS_CTRL_RST_USBHSPHYA ) | |
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19 | BIT(SYS_CTRL_RST_MACA ) | |
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20 | BIT(SYS_CTRL_RST_PCIEA ) | |
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21 | BIT(SYS_CTRL_RST_SGDMA ) | |
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22 | BIT(SYS_CTRL_RST_CIPHER ) | |
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23 | BIT(SYS_CTRL_RST_SATA ) | |
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24 | BIT(SYS_CTRL_RST_SATA_LINK ) | |
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25 | BIT(SYS_CTRL_RST_SATA_PHY ) | |
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26 | BIT(SYS_CTRL_RST_PCIEPHY ) | |
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27 | BIT(SYS_CTRL_RST_STATIC ) | |
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28 | BIT(SYS_CTRL_RST_UART1 ) | |
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29 | BIT(SYS_CTRL_RST_UART2 ) | |
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30 | BIT(SYS_CTRL_RST_MISC ) | |
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31 | BIT(SYS_CTRL_RST_I2S ) | |
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32 | BIT(SYS_CTRL_RST_SD ) | |
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33 | BIT(SYS_CTRL_RST_MACB ) | |
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34 | BIT(SYS_CTRL_RST_PCIEB ) | |
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35 | BIT(SYS_CTRL_RST_VIDEO ) | |
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36 | BIT(SYS_CTRL_RST_USBHSPHYB ) | |
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37 | BIT(SYS_CTRL_RST_USBDEV ); |
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38 | |||
39 | writel(value, SYS_CTRL_RST_SET_CTRL); |
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40 | |||
41 | // Release reset to cores as per power on defaults |
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42 | writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL); |
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43 | |||
44 | // Disable clocks to cores as per power-on defaults - must leave DDR |
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45 | // related clocks enabled otherwise we'll stop rather abruptly. |
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46 | value = |
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47 | BIT(SYS_CTRL_CLK_COPRO) | |
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48 | BIT(SYS_CTRL_CLK_DMA) | |
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49 | BIT(SYS_CTRL_CLK_CIPHER) | |
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50 | BIT(SYS_CTRL_CLK_SD) | |
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51 | BIT(SYS_CTRL_CLK_SATA) | |
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52 | BIT(SYS_CTRL_CLK_I2S) | |
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53 | BIT(SYS_CTRL_CLK_USBHS) | |
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54 | BIT(SYS_CTRL_CLK_MAC) | |
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55 | BIT(SYS_CTRL_CLK_PCIEA) | |
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56 | BIT(SYS_CTRL_CLK_STATIC) | |
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57 | BIT(SYS_CTRL_CLK_MACB) | |
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58 | BIT(SYS_CTRL_CLK_PCIEB) | |
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59 | BIT(SYS_CTRL_CLK_REF600) | |
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60 | BIT(SYS_CTRL_CLK_USBDEV); |
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61 | |||
62 | writel(value, SYS_CTRL_CLK_CLR_CTRL); |
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63 | |||
64 | // Enable clocks to cores as per power-on defaults |
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65 | |||
66 | // Set sys-control pin mux'ing as per power-on defaults |
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67 | |||
68 | writel(0, SYS_CONTROL_BASE + PINMUX_SECONDARY_SEL); |
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69 | writel(0, SYS_CONTROL_BASE + PINMUX_TERTIARY_SEL); |
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70 | writel(0, SYS_CONTROL_BASE + PINMUX_QUATERNARY_SEL); |
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71 | writel(0, SYS_CONTROL_BASE + PINMUX_DEBUG_SEL); |
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72 | writel(0, SYS_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL); |
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73 | writel(0, SYS_CONTROL_BASE + PINMUX_PULLUP_SEL); |
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74 | |||
75 | writel(0, SEC_CONTROL_BASE + PINMUX_SECONDARY_SEL); |
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76 | writel(0, SEC_CONTROL_BASE + PINMUX_TERTIARY_SEL); |
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77 | writel(0, SEC_CONTROL_BASE + PINMUX_QUATERNARY_SEL); |
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78 | writel(0, SEC_CONTROL_BASE + PINMUX_DEBUG_SEL); |
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79 | writel(0, SEC_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL); |
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80 | writel(0, SEC_CONTROL_BASE + PINMUX_PULLUP_SEL); |
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81 | |||
82 | // No need to save any state, as the ROM loader can determine whether reset |
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83 | // is due to power cycling or programatic action, just hit the (self- |
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84 | // clearing) CPU reset bit of the block reset register |
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85 | value = |
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86 | BIT(SYS_CTRL_RST_SCU) | |
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87 | BIT(SYS_CTRL_RST_ARM0) | |
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88 | BIT(SYS_CTRL_RST_ARM1); |
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89 | |||
90 | writel(value, SYS_CTRL_RST_SET_CTRL); |
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91 | } |