OpenWrt – Blame information for rev 4

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4 office 1 /*
2 * (C) Copyright 2010
3 * Michael Kurz <michi.kurz@googlemail.com>.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23  
24 /* This file contains the configuration parameters for the zyxel nbg460n board. */
25  
26 #ifndef _NBG460N_CONFIG_H
27 #define _NBG460N_CONFIG_H
28  
29 #define CONFIG_MIPS32 1 /* MIPS32 CPU core */
30 #define CONFIG_AR71XX 1
31 #define CONFIG_AR91XX 1
32 #define CONFIG_SYS_HZ 1000
33 #define CONFIG_SYS_MIPS_TIMER_FREQ (400000000/2)
34  
35 /* Cache Configuration */
36 #define CONFIG_SYS_DCACHE_SIZE 32768
37 #define CONFIG_SYS_ICACHE_SIZE 65536
38 #define CONFIG_SYS_CACHELINE_SIZE 32
39 /* Cache lock for stack */
40 #define CONFIG_SYS_INIT_SP_OFFSET 0x1000
41  
42 #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE)
43  
44 #define CONFIG_BAUDRATE 115200
45 #define CONFIG_SYS_BAUDRATE_TABLE {115200}
46  
47 #define CONFIG_MISC_INIT_R
48  
49 /* SPI-Flash support */
50 #define CONFIG_SPI_FLASH
51 #define CONFIG_AR71XX_SPI
52 #define CONFIG_SPI_FLASH_MACRONIX
53 #define CONFIG_SF_DEFAULT_HZ 25000000
54  
55 #define CONFIG_ENV_SPI_MAX_HZ 25000000
56 #define CONFIG_ENV_SPI_BUS 0
57 #define CONFIG_ENV_SPI_CS 0
58  
59 #define CONFIG_ENV_IS_IN_SPI_FLASH
60 #define CONFIG_ENV_ADDR 0xbfc20000
61 #define CONFIG_ENV_OFFSET 0x20000
62 #define CONFIG_ENV_SIZE 0x01000
63 #define CONFIG_ENV_SECT_SIZE 0x10000
64 #define CONFIG_SYS_MAX_FLASH_BANKS 1
65 #define CONFIG_SYS_MAX_FLASH_SECT 64
66 #define CONFIG_SYS_FLASH_BASE 0xbfc00000
67  
68 /* Net support */
69 #define CONFIG_ETHADDR_ADDR 0xbfc0fff8
70 #define CONFIG_SYS_RX_ETH_BUFFER 16
71 #define CONFIG_AG71XX
72 #define CONFIG_AG71XX_PORTS { 1, 1 }
73 #define CONFIG_AG71XX_MII0_IIF MII0_CTRL_IF_RGMII
74 #define CONFIG_AG71XX_MII1_IIF MII1_CTRL_IF_RGMII
75 #define CONFIG_NET_MULTI
76 #define CONFIG_IPADDR 192.168.1.254
77 #define CONFIG_SERVERIP 192.168.1.42
78  
79 /* Switch support */
80 #define CONFIG_MII
81 #define CONFIG_RTL8366_MII
82 #define RTL8366_PIN_SDA 16
83 #define RTL8366_PIN_SCK 18
84 #define MII_GPIOINCLUDE <asm/ar71xx_gpio.h>
85 #define MII_SETSDA(x) ar71xx_setpin(RTL8366_PIN_SDA, x)
86 #define MII_GETSDA ar71xx_getpin(RTL8366_PIN_SDA)
87 #define MII_SETSCK(x) ar71xx_setpin(RTL8366_PIN_SCK, x)
88 #define MII_SDAINPUT ar71xx_setpindir(RTL8366_PIN_SDA, 0)
89 #define MII_SDAOUTPUT ar71xx_setpindir(RTL8366_PIN_SDA, 1)
90 #define MII_SCKINPUT ar71xx_setpindir(RTL8366_PIN_SCK, 0)
91 #define MII_SCKOUTPUT ar71xx_setpindir(RTL8366_PIN_SCK, 1)
92  
93 #define CONFIG_BOOTDELAY 3
94 #define CONFIG_BOOTARGS "console=ttyS0,115200 rootfstype==squashfs,jffs2 noinitrd machtype=NBG460N"
95 #define CONFIG_BOOTCOMMAND "bootm 0xbfc70000"
96 #define CONFIG_LZMA
97  
98  
99 /* Commands */
100 #define CONFIG_SYS_NO_FLASH
101 #include <config_cmd_default.h>
102 #undef CONFIG_CMD_BDI
103 #undef CONFIG_CMD_FPGA
104 #undef CONFIG_CMD_IMI
105 #undef CONFIG_CMD_IMLS
106 #undef CONFIG_CMD_LOADS
107 #define CONFIG_CMD_SF
108 #define CONFIG_CMD_MII
109 #define CONFIG_CMD_PING
110 #define CONFIG_CMD_DHCP
111 #define CONFIG_CMD_SPI
112  
113 /* Miscellaneous configurable options */
114 #define CONFIG_SYS_PROMPT "U-Boot> "
115 #define CONFIG_SYS_CBSIZE 256
116 #define CONFIG_SYS_MAXARGS 16
117 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
118 #define CONFIG_SYS_LONGHELP 1
119 #define CONFIG_CMDLINE_EDITING 1
120 #define CONFIG_AUTO_COMPLETE
121 #define CONFIG_SYS_HUSH_PARSER
122 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
123  
124 /* Size of malloc() pool */
125 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * 0x10000 + 128*1024, 0x1000)
126 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
127  
128 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
129  
130 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
131 #define CONFIG_SYS_LOAD_ADDR 0x80060000 /* default load address */
132  
133 #define CONFIG_SYS_MEMTEST_START 0x80000800
134 #define CONFIG_SYS_MEMTEST_END 0x81E00000
135  
136 #endif /* _NBG460N_CONFIG_H */