OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/mips/ralink/mt7621.c |
2 | +++ b/arch/mips/ralink/mt7621.c |
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3 | office | 3 | @@ -16,6 +16,7 @@ |
1 | office | 4 | #include <asm/mach-ralink/ralink_regs.h> |
5 | #include <asm/mach-ralink/mt7621.h> |
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6 | #include <asm/mips-boards/launch.h> |
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7 | +#include <asm/delay.h> |
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8 | |||
9 | #include <pinmux.h> |
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10 | |||
3 | office | 11 | @@ -177,6 +178,58 @@ bool plat_cpu_core_present(int core) |
1 | office | 12 | return true; |
13 | } |
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14 | |||
15 | +#define LPS_PREC 8 |
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16 | +/* |
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17 | +* Re-calibration lpj(loop-per-jiffy). |
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18 | +* (derived from kernel/calibrate.c) |
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19 | +*/ |
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20 | +static int udelay_recal(void) |
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21 | +{ |
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22 | + unsigned int i, lpj = 0; |
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23 | + unsigned long ticks, loopbit; |
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24 | + int lps_precision = LPS_PREC; |
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25 | + |
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26 | + lpj = (1<<12); |
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27 | + |
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28 | + while ((lpj <<= 1) != 0) { |
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29 | + /* wait for "start of" clock tick */ |
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30 | + ticks = jiffies; |
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31 | + while (ticks == jiffies) |
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32 | + /* nothing */; |
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33 | + |
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34 | + /* Go .. */ |
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35 | + ticks = jiffies; |
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36 | + __delay(lpj); |
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37 | + ticks = jiffies - ticks; |
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38 | + if (ticks) |
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39 | + break; |
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40 | + } |
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41 | + |
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42 | + /* |
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43 | + * Do a binary approximation to get lpj set to |
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44 | + * equal one clock (up to lps_precision bits) |
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45 | + */ |
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46 | + lpj >>= 1; |
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47 | + loopbit = lpj; |
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48 | + while (lps_precision-- && (loopbit >>= 1)) { |
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49 | + lpj |= loopbit; |
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50 | + ticks = jiffies; |
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51 | + while (ticks == jiffies) |
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52 | + /* nothing */; |
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53 | + ticks = jiffies; |
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54 | + __delay(lpj); |
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55 | + if (jiffies != ticks) /* longer than 1 tick */ |
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56 | + lpj &= ~loopbit; |
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57 | + } |
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58 | + printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj); |
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59 | + |
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60 | + for(i=0; i< NR_CPUS; i++) |
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61 | + cpu_data[i].udelay_val = lpj; |
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62 | + |
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63 | + return 0; |
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64 | +} |
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65 | +device_initcall(udelay_recal); |
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66 | + |
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67 | void prom_soc_init(struct ralink_soc_info *soc_info) |
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68 | { |
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69 | void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); |
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70 | --- a/arch/mips/ralink/Kconfig |
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71 | +++ b/arch/mips/ralink/Kconfig |
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3 | office | 72 | @@ -58,6 +58,7 @@ choice |
1 | office | 73 | select CLKSRC_MIPS_GIC |
74 | select HW_HAS_PCI |
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75 | select WEAK_REORDERING_BEYOND_LLSC |
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76 | + select GENERIC_CLOCKEVENTS_BROADCAST |
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77 | endchoice |
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78 | |||
79 | choice |
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3 | office | 80 | --- a/arch/mips/ralink/timer-gic.c |
81 | +++ b/arch/mips/ralink/timer-gic.c |
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82 | @@ -12,6 +12,7 @@ |
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83 | #include <linux/of.h> |
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84 | #include <linux/clk-provider.h> |
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85 | #include <linux/clocksource.h> |
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86 | +#include <asm/time.h> |
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87 | |||
88 | #include "common.h" |
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89 | |||
90 | @@ -19,6 +20,8 @@ void __init plat_time_init(void) |
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91 | { |
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92 | ralink_of_remap(); |
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93 | |||
94 | + mips_hpt_frequency = 880000000 / 2; |
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95 | + |
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96 | of_clk_init(NULL); |
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97 | timer_probe(); |
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98 | } |