OpenWrt – Blame information for rev 2

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1 office 1 / {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "ralink,rt3352-soc";
5  
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9  
10 cpu@0 {
11 compatible = "mips,mips24KEc";
12 reg = <0>;
13 };
14 };
15  
16 chosen {
17 bootargs = "console=ttyS0,57600";
18 };
19  
20 cpuintc: cpuintc {
21 #address-cells = <0>;
22 #interrupt-cells = <1>;
23 interrupt-controller;
24 compatible = "mti,cpu-interrupt-controller";
25 };
26  
27 aliases {
28 spi0 = &spi0;
29 spi1 = &spi1;
30 serial0 = &uartlite;
31 };
32  
33 palmbus: palmbus@10000000 {
34 compatible = "palmbus";
35 reg = <0x10000000 0x200000>;
36 ranges = <0x0 0x10000000 0x1FFFFF>;
37  
38 #address-cells = <1>;
39 #size-cells = <1>;
40  
41 sysc: sysc@0 {
42 compatible = "ralink,rt3352-sysc", "ralink,rt3050-sysc", "syscon";
43 reg = <0x0 0x100>;
44 };
45  
46 timer: timer@100 {
47 compatible = "ralink,rt3352-timer", "ralink,rt2880-timer";
48 reg = <0x100 0x20>;
49  
50 interrupt-parent = <&intc>;
51 interrupts = <1>;
52 };
53  
54 watchdog: watchdog@120 {
55 compatible = "ralink,rt3352-wdt", "ralink,rt2880-wdt";
56 reg = <0x120 0x10>;
57  
58 resets = <&rstctrl 8>;
59 reset-names = "wdt";
60  
61 interrupt-parent = <&intc>;
62 interrupts = <1>;
63 };
64  
65 intc: intc@200 {
66 compatible = "ralink,rt3352-intc", "ralink,rt2880-intc";
67 reg = <0x200 0x100>;
68  
69 interrupt-controller;
70 #interrupt-cells = <1>;
71  
72 interrupt-parent = <&cpuintc>;
73 interrupts = <2>;
74 };
75  
76 memc: memc@300 {
77 compatible = "ralink,rt3352-memc", "ralink,rt3050-memc";
78 reg = <0x300 0x100>;
79  
80 resets = <&rstctrl 20>;
81 reset-names = "mc";
82  
83 interrupt-parent = <&intc>;
84 interrupts = <3>;
85 };
86  
87 uart: uart@500 {
88 compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
89 reg = <0x500 0x100>;
90  
91 resets = <&rstctrl 12>;
92 reset-names = "uart";
93  
94 interrupt-parent = <&intc>;
95 interrupts = <5>;
96  
97 reg-shift = <2>;
98  
99 status = "disabled";
100 };
101  
102 gpio0: gpio@600 {
103 compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio";
104 reg = <0x600 0x34>;
105  
106 gpio-controller;
107 #gpio-cells = <2>;
108  
109 ralink,gpio-base = <0>;
110 ralink,nr-gpio = <24>;
111 ralink,register-map = [ 00 04 08 0c
112 20 24 28 2c
113 30 34 ];
114 resets = <&rstctrl 13>;
115 reset-names = "pio";
116  
117 interrupt-parent = <&intc>;
118 interrupts = <6>;
119 };
120  
121 gpio1: gpio@638 {
122 compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio";
123 reg = <0x638 0x24>;
124  
125 gpio-controller;
126 #gpio-cells = <2>;
127  
128 ralink,gpio-base = <24>;
129 ralink,nr-gpio = <16>;
130 ralink,register-map = [ 00 04 08 0c
131 10 14 18 1c
132 20 24 ];
133  
134 status = "disabled";
135 };
136  
137 gpio2: gpio@660 {
138 compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio";
139 reg = <0x660 0x24>;
140  
141 gpio-controller;
142 #gpio-cells = <2>;
143  
144 ralink,gpio-base = <40>;
145 ralink,nr-gpio = <6>;
146 ralink,register-map = [ 00 04 08 0c
147 10 14 18 1c
148 20 24 ];
149  
150 status = "disabled";
151 };
152  
153 i2c@900 {
154 compatible = "ralink,rt2880-i2c";
155 reg = <0x900 0x100>;
156  
157 resets = <&rstctrl 16>;
158 reset-names = "i2c";
159  
160 #address-cells = <1>;
161 #size-cells = <0>;
162  
163 status = "disabled";
164  
165 pinctrl-names = "default";
166 pinctrl-0 = <&i2c_pins>;
167 };
168  
169 i2s@a00 {
170 compatible = "ralink,rt3352-i2s";
171 reg = <0xa00 0x100>;
172  
173 resets = <&rstctrl 17>;
174 reset-names = "i2s";
175  
176 interrupt-parent = <&intc>;
177 interrupts = <10>;
178  
179 txdma-req = <2>;
180 rxdma-req = <3>;
181  
182 dmas = <&gdma 4>,
183 <&gdma 6>;
184 dma-names = "tx", "rx";
185  
186 status = "disabled";
187 };
188  
189 spi0: spi@b00 {
190 compatible = "ralink,rt3352-spi", "ralink,rt2880-spi";
191 reg = <0xb00 0x40>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194  
195 resets = <&rstctrl 18>;
196 reset-names = "spi";
197  
198 pinctrl-names = "default";
199 pinctrl-0 = <&spi_pins>;
200  
201 status = "disabled";
202 };
203  
204 spi1: spi@b40 {
205 compatible = "ralink,rt3352-spi", "ralink,rt2880-spi";
206 reg = <0xb40 0x60>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209  
210 resets = <&rstctrl 18>;
211 reset-names = "spi";
212  
213 pinctrl-names = "default";
214 pinctrl-0 = <&spi_cs1>;
215  
216 status = "disabled";
217 };
218  
219 uartlite: uartlite@c00 {
220 compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
221 reg = <0xc00 0x100>;
222  
223 resets = <&rstctrl 19>;
224 reset-names = "uartl";
225  
226 interrupt-parent = <&intc>;
227 interrupts = <12>;
228  
229 reg-shift = <2>;
230  
231 pinctrl-names = "default";
232 pinctrl-0 = <&uartlite_pins>;
233 };
234  
235 gdma: gdma@2800 {
236 compatible = "ralink,rt3883-gdma";
237 reg = <0x2800 0x800>;
238  
239 resets = <&rstctrl 14>;
240 reset-names = "dma";
241  
242 interrupt-parent = <&intc>;
243 interrupts = <7>;
244  
245 #dma-cells = <1>;
246 #dma-channels = <16>;
247 #dma-requests = <16>;
248  
249 status = "disabled";
250 };
251 };
252  
253 pinctrl: pinctrl {
254 compatible = "ralink,rt2880-pinmux";
255  
256 pinctrl-names = "default";
257 pinctrl-0 = <&state_default>;
258  
259 state_default: pinctrl0 {
260 };
261  
262 i2c_pins: i2c_pins {
263 i2c_pins {
264 ralink,group = "i2c";
265 ralink,function = "i2c";
266 };
267 };
268  
269 mdio_pins: mdio {
270 mdio {
271 ralink,group = "mdio";
272 ralink,function = "mdio";
273 };
274 };
275  
276 rgmii_pins: rgmii {
277 rgmii {
278 ralink,group = "rgmii";
279 ralink,function = "rgmii";
280 };
281 };
282  
283 spi_pins: spi_pins {
284 spi_pins {
285 ralink,group = "spi";
286 ralink,function = "spi";
287 };
288 };
289  
290 spi_cs1: spi1 {
291 spi1 {
292 ralink,group = "spi_cs1";
293 ralink,function = "spi_cs1";
294 };
295 };
296  
297 uartlite_pins: uartlite {
298 uart {
299 ralink,group = "uartlite";
300 ralink,function = "uartlite";
301 };
302 };
303 };
304  
305 rstctrl: rstctrl {
306 compatible = "ralink,rt3352-reset", "ralink,rt2880-reset";
307 #reset-cells = <1>;
308 };
309  
310 clkctrl: clkctrl {
311 compatible = "ralink,rt2880-clock";
312 #clock-cells = <1>;
313 };
314  
315 ethernet: ethernet@10100000 {
316 compatible = "ralink,rt3352-eth", "ralink,rt3050-eth";
317 reg = <0x10100000 0x10000>;
318  
319 resets = <&rstctrl 21>;
320 reset-names = "fe";
321  
322 interrupt-parent = <&cpuintc>;
323 interrupts = <5>;
324  
325 mediatek,switch = <&esw>;
326 };
327  
328 esw: esw@10110000 {
329 compatible = "ralink,rt3352-esw", "ralink,rt3050-esw";
330 reg = <0x10110000 0x8000>;
331  
332 resets = <&rstctrl 23>;
333 reset-names = "esw";
334  
335 interrupt-parent = <&intc>;
336 interrupts = <17>;
337 };
338  
339 usbphy: usbphy {
340 compatible = "ralink,rt3352-usbphy";
341 #phy-cells = <0>;
342  
343 ralink,sysctl = <&sysc>;
344 resets = <&rstctrl 22 &rstctrl 25>;
345 reset-names = "host", "device";
346 clocks = <&clkctrl 18 &clkctrl 20>;
347 clock-names = "host", "device";
348 };
349  
350 wmac: wmac@10180000 {
351 compatible = "ralink,rt3352-wmac", "ralink,rt2880-wmac";
352 reg = <0x10180000 0x40000>;
353  
354 interrupt-parent = <&cpuintc>;
355 interrupts = <6>;
356  
357 ralink,eeprom = "soc_wmac.eeprom";
358 };
359  
360 ehci: ehci@101c0000 {
361 #address-cells = <1>;
362 #size-cells = <0>;
363 compatible = "generic-ehci";
364 reg = <0x101c0000 0x1000>;
365  
366 phys = <&usbphy>;
367 phy-names = "usb";
368  
369 interrupt-parent = <&intc>;
370 interrupts = <18>;
371  
372 status = "disabled";
373  
374 ehci_port1: port@1 {
375 reg = <1>;
376 #trigger-source-cells = <0>;
377 };
378 };
379  
380 ohci: ohci@101c1000 {
381 #address-cells = <1>;
382 #size-cells = <0>;
383 compatible = "generic-ohci";
384 reg = <0x101c1000 0x1000>;
385  
386 phys = <&usbphy>;
387 phy-names = "usb";
388  
389 interrupt-parent = <&intc>;
390 interrupts = <18>;
391  
392 status = "disabled";
393  
394 ohci_port1: port@1 {
395 reg = <1>;
396 #trigger-source-cells = <0>;
397 };
398 };
399 };