OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | / { |
2 | #address-cells = <1>; |
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3 | #size-cells = <1>; |
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4 | compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc"; |
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5 | |||
6 | cpus { |
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7 | #address-cells = <1>; |
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8 | #size-cells = <0>; |
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9 | |||
10 | cpu@0 { |
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11 | compatible = "mips,mips24KEc"; |
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12 | reg = <0>; |
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13 | }; |
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14 | }; |
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15 | |||
16 | chosen { |
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17 | bootargs = "console=ttyS0,57600"; |
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18 | }; |
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19 | |||
20 | aliases { |
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21 | spi0 = &spi0; |
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22 | serial0 = &uartlite; |
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23 | }; |
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24 | |||
25 | cpuintc: cpuintc { |
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26 | #address-cells = <0>; |
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27 | #interrupt-cells = <1>; |
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28 | interrupt-controller; |
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29 | compatible = "mti,cpu-interrupt-controller"; |
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30 | }; |
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31 | |||
32 | palmbus: palmbus@10000000 { |
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33 | compatible = "palmbus"; |
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34 | reg = <0x10000000 0x200000>; |
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35 | ranges = <0x0 0x10000000 0x1FFFFF>; |
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36 | |||
37 | #address-cells = <1>; |
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38 | #size-cells = <1>; |
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39 | |||
40 | sysc: sysc@0 { |
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41 | compatible = "ralink,rt3050-sysc", "syscon"; |
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42 | reg = <0x0 0x100>; |
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43 | }; |
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44 | |||
45 | timer: timer@100 { |
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46 | compatible = "ralink,rt3050-timer", "ralink,rt2880-timer"; |
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47 | reg = <0x100 0x20>; |
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48 | |||
49 | interrupt-parent = <&intc>; |
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50 | interrupts = <1>; |
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51 | }; |
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52 | |||
53 | watchdog: watchdog@120 { |
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54 | compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt"; |
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55 | reg = <0x120 0x10>; |
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56 | |||
57 | resets = <&rstctrl 8>; |
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58 | reset-names = "wdt"; |
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59 | |||
60 | interrupt-parent = <&intc>; |
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61 | interrupts = <1>; |
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62 | }; |
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63 | |||
64 | intc: intc@200 { |
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65 | compatible = "ralink,rt3050-intc", "ralink,rt2880-intc"; |
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66 | reg = <0x200 0x100>; |
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67 | |||
68 | resets = <&rstctrl 19>; |
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69 | reset-names = "intc"; |
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70 | |||
71 | interrupt-controller; |
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72 | #interrupt-cells = <1>; |
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73 | |||
74 | interrupt-parent = <&cpuintc>; |
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75 | interrupts = <2>; |
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76 | }; |
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77 | |||
78 | memc: memc@300 { |
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79 | compatible = "ralink,rt3050-memc"; |
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80 | reg = <0x300 0x100>; |
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81 | |||
82 | resets = <&rstctrl 20>; |
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83 | reset-names = "mc"; |
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84 | |||
85 | interrupt-parent = <&intc>; |
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86 | interrupts = <3>; |
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87 | }; |
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88 | |||
89 | uart: uart@500 { |
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90 | compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a"; |
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91 | reg = <0x500 0x100>; |
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92 | |||
93 | resets = <&rstctrl 12>; |
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94 | reset-names = "uart"; |
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95 | |||
96 | interrupt-parent = <&intc>; |
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97 | interrupts = <5>; |
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98 | |||
99 | reg-shift = <2>; |
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100 | |||
101 | status = "disabled"; |
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102 | }; |
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103 | |||
104 | gpio0: gpio@600 { |
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105 | compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio"; |
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106 | reg = <0x600 0x34>; |
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107 | |||
108 | gpio-controller; |
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109 | #gpio-cells = <2>; |
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110 | |||
111 | ralink,gpio-base = <0>; |
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112 | ralink,nr-gpio = <24>; |
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113 | ralink,register-map = [ 00 04 08 0c |
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114 | 20 24 28 2c |
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115 | 30 34 ]; |
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116 | |||
117 | resets = <&rstctrl 13>; |
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118 | reset-names = "pio"; |
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119 | |||
120 | interrupt-parent = <&intc>; |
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121 | interrupts = <6>; |
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122 | }; |
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123 | |||
124 | gpio1: gpio@638 { |
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125 | compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio"; |
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126 | reg = <0x638 0x24>; |
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127 | |||
128 | gpio-controller; |
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129 | #gpio-cells = <2>; |
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130 | |||
131 | ralink,gpio-base = <24>; |
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132 | ralink,nr-gpio = <16>; |
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133 | ralink,register-map = [ 00 04 08 0c |
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134 | 10 14 18 1c |
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135 | 20 24 ]; |
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136 | |||
137 | status = "disabled"; |
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138 | }; |
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139 | |||
140 | gpio2: gpio@660 { |
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141 | compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio"; |
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142 | reg = <0x660 0x24>; |
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143 | |||
144 | gpio-controller; |
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145 | #gpio-cells = <2>; |
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146 | |||
147 | ralink,gpio-base = <40>; |
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148 | ralink,nr-gpio = <12>; |
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149 | ralink,register-map = [ 00 04 08 0c |
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150 | 10 14 18 1c |
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151 | 20 24 ]; |
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152 | |||
153 | status = "disabled"; |
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154 | }; |
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155 | |||
156 | gdma: gdma@700 { |
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157 | compatible = "ralink,rt305x-gdma"; |
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158 | reg = <0x700 0x100>; |
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159 | |||
160 | resets = <&rstctrl 14>; |
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161 | reset-names = "dma"; |
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162 | |||
163 | interrupt-parent = <&intc>; |
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164 | interrupts = <7>; |
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165 | |||
166 | #dma-cells = <1>; |
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167 | #dma-channels = <8>; |
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168 | #dma-requests = <8>; |
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169 | |||
170 | status = "disabled"; |
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171 | }; |
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172 | |||
173 | i2c@900 { |
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174 | compatible = "ralink,rt2880-i2c"; |
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175 | reg = <0x900 0x100>; |
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176 | |||
177 | resets = <&rstctrl 16>; |
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178 | reset-names = "i2c"; |
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179 | |||
180 | #address-cells = <1>; |
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181 | #size-cells = <0>; |
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182 | |||
183 | status = "disabled"; |
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184 | |||
185 | pinctrl-names = "default"; |
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186 | pinctrl-0 = <&i2c_pins>; |
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187 | }; |
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188 | |||
189 | i2s@a00 { |
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190 | compatible = "ralink,rt3050-i2s"; |
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191 | reg = <0xa00 0x100>; |
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192 | |||
193 | resets = <&rstctrl 17>; |
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194 | reset-names = "i2s"; |
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195 | |||
196 | interrupt-parent = <&intc>; |
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197 | interrupts = <10>; |
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198 | |||
199 | txdma-req = <2>; |
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200 | |||
201 | dmas = <&gdma 4>; |
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202 | dma-names = "tx"; |
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203 | |||
204 | status = "disabled"; |
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205 | }; |
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206 | |||
207 | spi0: spi@b00 { |
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208 | compatible = "ralink,rt3050-spi", "ralink,rt2880-spi"; |
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209 | reg = <0xb00 0x100>; |
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210 | |||
211 | resets = <&rstctrl 18>; |
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212 | reset-names = "spi"; |
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213 | |||
214 | #address-cells = <1>; |
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215 | #size-cells = <0>; |
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216 | |||
217 | pinctrl-names = "default"; |
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218 | pinctrl-0 = <&spi_pins>; |
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219 | |||
220 | status = "disabled"; |
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221 | }; |
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222 | |||
223 | uartlite: uartlite@c00 { |
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224 | compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a"; |
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225 | reg = <0xc00 0x100>; |
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226 | |||
227 | resets = <&rstctrl 19>; |
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228 | reset-names = "uartl"; |
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229 | |||
230 | interrupt-parent = <&intc>; |
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231 | interrupts = <12>; |
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232 | |||
233 | reg-shift = <2>; |
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234 | |||
235 | pinctrl-names = "default"; |
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236 | pinctrl-0 = <&uartlite_pins>; |
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237 | }; |
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238 | }; |
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239 | |||
240 | pinctrl: pinctrl { |
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241 | compatible = "ralink,rt2880-pinmux"; |
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242 | |||
243 | pinctrl-names = "default"; |
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244 | pinctrl-0 = <&state_default>; |
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245 | |||
246 | state_default: pinctrl0 { |
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247 | sdram { |
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248 | ralink,group = "sdram"; |
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249 | ralink,function = "sdram"; |
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250 | }; |
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251 | }; |
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252 | |||
253 | i2c_pins: i2c_pins { |
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254 | i2c_pins { |
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255 | ralink,group = "i2c"; |
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256 | ralink,function = "i2c"; |
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257 | }; |
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258 | }; |
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259 | |||
260 | spi_pins: spi_pins { |
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261 | spi_pins { |
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262 | ralink,group = "spi"; |
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263 | ralink,function = "spi"; |
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264 | }; |
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265 | }; |
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266 | |||
267 | rgmii_pins: rgmii { |
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268 | rgmii { |
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269 | ralink,group = "rgmii"; |
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270 | ralink,function = "rgmii"; |
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271 | }; |
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272 | }; |
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273 | |||
274 | uartlite_pins: uartlite { |
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275 | uart { |
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276 | ralink,group = "uartlite"; |
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277 | ralink,function = "uartlite"; |
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278 | }; |
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279 | }; |
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280 | }; |
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281 | |||
282 | rstctrl: rstctrl { |
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283 | compatible = "ralink,rt3050-reset", "ralink,rt2880-reset"; |
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284 | #reset-cells = <1>; |
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285 | }; |
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286 | |||
287 | clkctrl: clkctrl { |
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288 | compatible = "ralink,rt2880-clock"; |
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289 | #clock-cells = <1>; |
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290 | }; |
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291 | |||
292 | usbphy: usbphy { |
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293 | compatible = "ralink,rt3050-usbphy"; |
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294 | #phy-cells = <0>; |
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295 | |||
296 | ralink,sysctl = <&sysc>; |
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297 | resets = <&rstctrl 22>; |
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298 | reset-names = "host"; |
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299 | clocks = <&clkctrl 18>; |
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300 | clock-names = "host"; |
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301 | }; |
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302 | |||
303 | ethernet: ethernet@10100000 { |
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304 | compatible = "ralink,rt3050-eth"; |
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305 | reg = <0x10100000 0x10000>; |
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306 | |||
307 | resets = <&rstctrl 21>; |
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308 | reset-names = "fe"; |
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309 | |||
310 | interrupt-parent = <&cpuintc>; |
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311 | interrupts = <5>; |
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312 | |||
313 | mediatek,switch = <&esw>; |
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314 | }; |
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315 | |||
316 | esw: esw@10110000 { |
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317 | compatible = "ralink,rt3050-esw"; |
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318 | reg = <0x10110000 0x8000>; |
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319 | |||
320 | resets = <&rstctrl 23>; |
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321 | reset-names = "esw"; |
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322 | |||
323 | interrupt-parent = <&intc>; |
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324 | interrupts = <17>; |
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325 | }; |
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326 | |||
327 | wmac: wmac@10180000 { |
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328 | compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac"; |
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329 | reg = <0x10180000 0x40000>; |
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330 | |||
331 | interrupt-parent = <&cpuintc>; |
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332 | interrupts = <6>; |
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333 | |||
334 | ralink,eeprom = "soc_wmac.eeprom"; |
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335 | }; |
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336 | |||
337 | otg: otg@101c0000 { |
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338 | #address-cells = <1>; |
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339 | #size-cells = <0>; |
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340 | compatible = "ralink,rt3050-otg", "snps,dwc2"; |
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341 | reg = <0x101c0000 0x40000>; |
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342 | |||
343 | interrupt-parent = <&intc>; |
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344 | interrupts = <18>; |
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345 | |||
346 | resets = <&rstctrl 22>; |
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347 | reset-names = "otg"; |
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348 | |||
349 | status = "disabled"; |
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350 | |||
351 | otg_port1: port@1 { |
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352 | reg = <1>; |
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353 | #trigger-source-cells = <0>; |
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354 | }; |
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355 | }; |
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356 | }; |