OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
2 | |||
3 | / { |
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4 | #address-cells = <1>; |
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5 | #size-cells = <1>; |
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6 | compatible = "mediatek,mt7621-soc"; |
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7 | |||
8 | cpus { |
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9 | cpu@0 { |
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10 | compatible = "mips,mips1004Kc"; |
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11 | }; |
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12 | |||
13 | cpu@1 { |
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14 | compatible = "mips,mips1004Kc"; |
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15 | }; |
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16 | }; |
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17 | |||
3 | office | 18 | cpuintc: cpuintc@0 { |
1 | office | 19 | #address-cells = <0>; |
20 | #interrupt-cells = <1>; |
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21 | interrupt-controller; |
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22 | compatible = "mti,cpu-interrupt-controller"; |
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23 | }; |
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24 | |||
25 | aliases { |
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26 | serial0 = &uartlite; |
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27 | }; |
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28 | |||
3 | office | 29 | cpuclock: cpuclock@0 { |
30 | #clock-cells = <0>; |
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31 | compatible = "fixed-clock"; |
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1 | office | 32 | |
3 | office | 33 | /* FIXME: there should be way to detect this */ |
34 | clock-frequency = <880000000>; |
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1 | office | 35 | }; |
36 | |||
3 | office | 37 | sysclock: sysclock@0 { |
1 | office | 38 | #clock-cells = <0>; |
39 | compatible = "fixed-clock"; |
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40 | |||
41 | /* FIXME: there should be way to detect this */ |
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42 | clock-frequency = <50000000>; |
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43 | }; |
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44 | |||
45 | |||
46 | |||
47 | palmbus: palmbus@1E000000 { |
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48 | compatible = "palmbus"; |
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49 | reg = <0x1E000000 0x100000>; |
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50 | ranges = <0x0 0x1E000000 0x0FFFFF>; |
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51 | |||
52 | #address-cells = <1>; |
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53 | #size-cells = <1>; |
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54 | |||
55 | sysc: sysc@0 { |
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56 | compatible = "mtk,mt7621-sysc"; |
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57 | reg = <0x0 0x100>; |
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58 | }; |
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59 | |||
60 | wdt: wdt@100 { |
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61 | compatible = "mediatek,mt7621-wdt"; |
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62 | reg = <0x100 0x100>; |
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63 | }; |
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64 | |||
65 | gpio@600 { |
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66 | #address-cells = <1>; |
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67 | #size-cells = <0>; |
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68 | |||
69 | compatible = "mtk,mt7621-gpio"; |
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70 | reg = <0x600 0x100>; |
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71 | |||
72 | gpio0: bank@0 { |
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73 | reg = <0>; |
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74 | compatible = "mtk,mt7621-gpio-bank"; |
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75 | gpio-controller; |
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76 | #gpio-cells = <2>; |
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77 | }; |
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78 | |||
79 | gpio1: bank@1 { |
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80 | reg = <1>; |
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81 | compatible = "mtk,mt7621-gpio-bank"; |
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82 | gpio-controller; |
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83 | #gpio-cells = <2>; |
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84 | }; |
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85 | |||
86 | gpio2: bank@2 { |
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87 | reg = <2>; |
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88 | compatible = "mtk,mt7621-gpio-bank"; |
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89 | gpio-controller; |
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90 | #gpio-cells = <2>; |
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91 | }; |
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92 | }; |
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93 | |||
94 | i2c: i2c@900 { |
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95 | compatible = "mediatek,mt7621-i2c"; |
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96 | reg = <0x900 0x100>; |
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97 | |||
98 | clocks = <&sysclock>; |
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99 | |||
100 | resets = <&rstctrl 16>; |
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101 | reset-names = "i2c"; |
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102 | |||
103 | #address-cells = <1>; |
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104 | #size-cells = <0>; |
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105 | |||
106 | status = "disabled"; |
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107 | |||
108 | pinctrl-names = "default"; |
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109 | pinctrl-0 = <&i2c_pins>; |
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110 | }; |
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111 | |||
112 | i2s: i2s@a00 { |
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113 | compatible = "mediatek,mt7621-i2s"; |
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114 | reg = <0xa00 0x100>; |
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115 | |||
116 | clocks = <&sysclock>; |
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117 | |||
118 | resets = <&rstctrl 17>; |
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119 | reset-names = "i2s"; |
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120 | |||
121 | interrupt-parent = <&gic>; |
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122 | interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>; |
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123 | |||
124 | txdma-req = <2>; |
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125 | rxdma-req = <3>; |
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126 | |||
127 | dmas = <&gdma 4>, |
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128 | <&gdma 6>; |
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129 | dma-names = "tx", "rx"; |
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130 | |||
131 | status = "disabled"; |
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132 | }; |
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133 | |||
3 | office | 134 | systick: systick@d00 { |
1 | office | 135 | compatible = "ralink,mt7621-systick", "ralink,cevt-systick"; |
3 | office | 136 | reg = <0xd00 0x10>; |
1 | office | 137 | |
138 | resets = <&rstctrl 28>; |
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139 | reset-names = "intc"; |
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140 | |||
141 | interrupt-parent = <&gic>; |
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142 | interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>; |
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143 | }; |
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144 | |||
145 | memc: memc@5000 { |
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146 | compatible = "mtk,mt7621-memc"; |
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3 | office | 147 | reg = <0x300 0x100>; |
1 | office | 148 | }; |
149 | |||
150 | cpc: cpc@1fbf0000 { |
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3 | office | 151 | compatible = "mtk,mt7621-cpc"; |
152 | reg = <0x1fbf0000 0x8000>; |
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1 | office | 153 | }; |
154 | |||
155 | mc: mc@1fbf8000 { |
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3 | office | 156 | compatible = "mtk,mt7621-mc"; |
157 | reg = <0x1fbf8000 0x8000>; |
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158 | }; |
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1 | office | 159 | |
160 | uartlite: uartlite@c00 { |
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161 | compatible = "ns16550a"; |
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162 | reg = <0xc00 0x100>; |
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163 | |||
3 | office | 164 | clocks = <&sysclock>; |
1 | office | 165 | clock-frequency = <50000000>; |
166 | |||
167 | interrupt-parent = <&gic>; |
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168 | interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; |
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169 | |||
170 | reg-shift = <2>; |
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171 | reg-io-width = <4>; |
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172 | no-loopback-test; |
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173 | }; |
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174 | |||
175 | spi0: spi@b00 { |
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176 | status = "disabled"; |
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177 | |||
178 | compatible = "ralink,mt7621-spi"; |
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179 | reg = <0xb00 0x100>; |
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180 | |||
3 | office | 181 | clocks = <&sysclock>; |
1 | office | 182 | |
183 | resets = <&rstctrl 18>; |
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184 | reset-names = "spi"; |
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185 | |||
186 | #address-cells = <1>; |
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187 | #size-cells = <0>; |
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188 | |||
189 | pinctrl-names = "default"; |
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190 | pinctrl-0 = <&spi_pins>; |
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191 | }; |
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192 | |||
193 | gdma: gdma@2800 { |
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194 | compatible = "ralink,rt3883-gdma"; |
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195 | reg = <0x2800 0x800>; |
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196 | |||
197 | resets = <&rstctrl 14>; |
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198 | reset-names = "dma"; |
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199 | |||
200 | interrupt-parent = <&gic>; |
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201 | interrupts = <0 13 4>; |
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202 | |||
203 | #dma-cells = <1>; |
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204 | #dma-channels = <16>; |
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205 | #dma-requests = <16>; |
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206 | |||
207 | status = "disabled"; |
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208 | }; |
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209 | |||
210 | hsdma: hsdma@7000 { |
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211 | compatible = "mediatek,mt7621-hsdma"; |
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212 | reg = <0x7000 0x1000>; |
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213 | |||
214 | resets = <&rstctrl 5>; |
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215 | reset-names = "hsdma"; |
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216 | |||
217 | interrupt-parent = <&gic>; |
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218 | interrupts = <0 11 4>; |
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219 | |||
220 | #dma-cells = <1>; |
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221 | #dma-channels = <1>; |
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222 | #dma-requests = <1>; |
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223 | |||
224 | status = "disabled"; |
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225 | }; |
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226 | }; |
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227 | |||
228 | pinctrl: pinctrl { |
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229 | compatible = "ralink,rt2880-pinmux"; |
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230 | pinctrl-names = "default"; |
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231 | pinctrl-0 = <&state_default>; |
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232 | |||
233 | state_default: pinctrl0 { |
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234 | }; |
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235 | |||
3 | office | 236 | i2c_pins: i2c { |
237 | i2c { |
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1 | office | 238 | ralink,group = "i2c"; |
239 | ralink,function = "i2c"; |
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240 | }; |
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241 | }; |
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242 | |||
3 | office | 243 | spi_pins: spi { |
244 | spi { |
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1 | office | 245 | ralink,group = "spi"; |
246 | ralink,function = "spi"; |
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247 | }; |
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248 | }; |
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249 | |||
250 | uart1_pins: uart1 { |
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251 | uart1 { |
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252 | ralink,group = "uart1"; |
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253 | ralink,function = "uart1"; |
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254 | }; |
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255 | }; |
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256 | |||
257 | uart2_pins: uart2 { |
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258 | uart2 { |
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259 | ralink,group = "uart2"; |
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260 | ralink,function = "uart2"; |
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261 | }; |
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262 | }; |
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263 | |||
264 | uart3_pins: uart3 { |
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265 | uart3 { |
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266 | ralink,group = "uart3"; |
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267 | ralink,function = "uart3"; |
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268 | }; |
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269 | }; |
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270 | |||
271 | rgmii1_pins: rgmii1 { |
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272 | rgmii1 { |
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273 | ralink,group = "rgmii1"; |
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274 | ralink,function = "rgmii1"; |
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275 | }; |
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276 | }; |
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277 | |||
278 | rgmii2_pins: rgmii2 { |
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279 | rgmii2 { |
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280 | ralink,group = "rgmii2"; |
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281 | ralink,function = "rgmii2"; |
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282 | }; |
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283 | }; |
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284 | |||
285 | mdio_pins: mdio { |
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286 | mdio { |
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287 | ralink,group = "mdio"; |
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288 | ralink,function = "mdio"; |
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289 | }; |
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290 | }; |
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291 | |||
292 | pcie_pins: pcie { |
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293 | pcie { |
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294 | ralink,group = "pcie"; |
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295 | ralink,function = "pcie rst"; |
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296 | }; |
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297 | }; |
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298 | |||
299 | nand_pins: nand { |
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300 | spi-nand { |
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301 | ralink,group = "spi"; |
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302 | ralink,function = "nand1"; |
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303 | }; |
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304 | |||
305 | sdhci-nand { |
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306 | ralink,group = "sdhci"; |
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307 | ralink,function = "nand2"; |
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308 | }; |
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309 | }; |
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310 | |||
311 | sdhci_pins: sdhci { |
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312 | sdhci { |
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313 | ralink,group = "sdhci"; |
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314 | ralink,function = "sdhci"; |
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315 | }; |
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316 | }; |
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317 | }; |
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318 | |||
319 | rstctrl: rstctrl { |
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320 | compatible = "ralink,rt2880-reset"; |
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321 | #reset-cells = <1>; |
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322 | }; |
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323 | |||
324 | clkctrl: clkctrl { |
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325 | compatible = "ralink,rt2880-clock"; |
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326 | #clock-cells = <1>; |
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327 | }; |
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328 | |||
329 | sdhci: sdhci@1E130000 { |
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330 | status = "disabled"; |
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331 | |||
332 | compatible = "ralink,mt7620-sdhci"; |
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333 | reg = <0x1E130000 0x4000>; |
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334 | |||
335 | interrupt-parent = <&gic>; |
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336 | interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; |
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337 | }; |
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338 | |||
339 | xhci: xhci@1E1C0000 { |
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340 | status = "okay"; |
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341 | |||
342 | compatible = "mediatek,mt8173-xhci"; |
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343 | reg = <0x1e1c0000 0x1000 |
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344 | 0x1e1d0700 0x0100>; |
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345 | reg-names = "mac", "ippc"; |
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346 | |||
347 | clocks = <&sysclock>; |
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348 | clock-names = "sys_ck"; |
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349 | |||
350 | interrupt-parent = <&gic>; |
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351 | interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; |
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352 | }; |
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353 | |||
354 | gic: interrupt-controller@1fbc0000 { |
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355 | compatible = "mti,gic"; |
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356 | reg = <0x1fbc0000 0x2000>; |
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357 | |||
358 | interrupt-controller; |
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359 | #interrupt-cells = <3>; |
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360 | |||
361 | mti,reserved-cpu-vectors = <7>; |
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362 | |||
363 | timer { |
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364 | compatible = "mti,gic-timer"; |
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365 | interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; |
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3 | office | 366 | clocks = <&cpuclock>; |
1 | office | 367 | }; |
368 | }; |
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369 | |||
370 | nand: nand@1e003000 { |
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371 | status = "disabled"; |
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372 | |||
373 | compatible = "mtk,mt7621-nand"; |
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374 | bank-width = <2>; |
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375 | reg = <0x1e003000 0x800 |
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376 | 0x1e003800 0x800>; |
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3 | office | 377 | #address-cells = <1>; |
378 | #size-cells = <1>; |
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1 | office | 379 | }; |
380 | |||
3 | office | 381 | hnat: hnat@1e100000 { |
382 | compatible = "mediatek,mt7623-hnat"; |
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383 | reg = <0x1e100000 0x10000>; |
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384 | mtketh-ppd = "eth0"; |
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385 | mtketh-lan = "eth0"; |
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386 | mtketh-wan = "eth0"; |
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387 | resets = <&rstctrl 0>; |
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388 | reset-names = "mtketh"; |
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389 | }; |
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390 | |||
1 | office | 391 | ethernet: ethernet@1e100000 { |
392 | compatible = "mediatek,mt7621-eth"; |
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393 | reg = <0x1e100000 0x10000>; |
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394 | |||
395 | #address-cells = <1>; |
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3 | office | 396 | #size-cells = <0>; |
1 | office | 397 | |
398 | resets = <&rstctrl 6 &rstctrl 23>; |
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399 | reset-names = "fe", "eth"; |
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400 | |||
401 | interrupt-parent = <&gic>; |
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402 | interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; |
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403 | |||
404 | mediatek,switch = <&gsw>; |
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405 | |||
406 | mdio-bus { |
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407 | #address-cells = <1>; |
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408 | #size-cells = <0>; |
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409 | |||
410 | phy1f: ethernet-phy@1f { |
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411 | reg = <0x1f>; |
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412 | phy-mode = "rgmii"; |
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413 | }; |
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414 | }; |
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415 | }; |
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416 | |||
417 | gsw: gsw@1e110000 { |
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418 | compatible = "mediatek,mt7621-gsw"; |
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419 | reg = <0x1e110000 0x8000>; |
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420 | interrupt-parent = <&gic>; |
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421 | interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; |
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422 | }; |
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423 | |||
424 | pcie: pcie@1e140000 { |
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425 | compatible = "mediatek,mt7621-pci"; |
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426 | reg = <0x1e140000 0x100 |
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427 | 0x1e142000 0x100>; |
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428 | |||
429 | #address-cells = <3>; |
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430 | #size-cells = <2>; |
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431 | |||
432 | pinctrl-names = "default"; |
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433 | pinctrl-0 = <&pcie_pins>; |
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434 | |||
435 | device_type = "pci"; |
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436 | |||
437 | bus-range = <0 255>; |
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438 | ranges = < |
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439 | 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ |
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440 | 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ |
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441 | >; |
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442 | |||
443 | interrupt-parent = <&gic>; |
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444 | interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH |
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445 | GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH |
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446 | GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; |
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447 | |||
448 | status = "disabled"; |
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449 | |||
450 | resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; |
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451 | reset-names = "pcie0", "pcie1", "pcie2"; |
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452 | clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; |
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453 | clock-names = "pcie0", "pcie1", "pcie2"; |
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454 | |||
3 | office | 455 | pcie0 { |
1 | office | 456 | reg = <0x0000 0 0 0 0>; |
457 | |||
458 | #address-cells = <3>; |
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459 | #size-cells = <2>; |
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460 | |||
3 | office | 461 | device_type = "pci"; |
1 | office | 462 | }; |
463 | |||
3 | office | 464 | pcie1 { |
1 | office | 465 | reg = <0x0800 0 0 0 0>; |
466 | |||
467 | #address-cells = <3>; |
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468 | #size-cells = <2>; |
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469 | |||
3 | office | 470 | device_type = "pci"; |
1 | office | 471 | }; |
472 | |||
3 | office | 473 | pcie2 { |
1 | office | 474 | reg = <0x1000 0 0 0 0>; |
475 | |||
476 | #address-cells = <3>; |
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477 | #size-cells = <2>; |
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478 | |||
3 | office | 479 | device_type = "pci"; |
1 | office | 480 | }; |
481 | }; |
||
482 | }; |