OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
2 | #include <dt-bindings/clock/mt7621-clk.h> |
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3 | |||
4 | / { |
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5 | #address-cells = <1>; |
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6 | #size-cells = <1>; |
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7 | compatible = "mediatek,mt7621-soc"; |
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8 | |||
9 | cpus { |
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10 | #address-cells = <1>; |
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11 | #size-cells = <0>; |
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12 | |||
13 | cpu@0 { |
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14 | device_type = "cpu"; |
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15 | compatible = "mips,mips1004Kc"; |
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16 | reg = <0>; |
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17 | }; |
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18 | |||
19 | cpu@1 { |
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20 | device_type = "cpu"; |
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21 | compatible = "mips,mips1004Kc"; |
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22 | reg = <1>; |
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23 | }; |
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24 | }; |
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25 | |||
26 | cpuintc: cpuintc { |
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27 | #address-cells = <0>; |
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28 | #interrupt-cells = <1>; |
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29 | interrupt-controller; |
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30 | compatible = "mti,cpu-interrupt-controller"; |
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31 | }; |
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32 | |||
33 | aliases { |
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34 | serial0 = &uartlite; |
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35 | }; |
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36 | |||
37 | pll: pll { |
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38 | compatible = "mediatek,mt7621-pll", "syscon"; |
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39 | |||
40 | #clock-cells = <1>; |
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41 | clock-output-names = "cpu", "bus"; |
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42 | }; |
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43 | |||
44 | sysclock: sysclock { |
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45 | #clock-cells = <0>; |
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46 | compatible = "fixed-clock"; |
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47 | |||
48 | /* FIXME: there should be way to detect this */ |
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49 | clock-frequency = <50000000>; |
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50 | }; |
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51 | |||
52 | |||
53 | |||
54 | palmbus: palmbus@1E000000 { |
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55 | compatible = "palmbus"; |
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56 | reg = <0x1E000000 0x100000>; |
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57 | ranges = <0x0 0x1E000000 0x0FFFFF>; |
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58 | |||
59 | #address-cells = <1>; |
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60 | #size-cells = <1>; |
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61 | |||
62 | sysc: sysc@0 { |
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63 | compatible = "mtk,mt7621-sysc"; |
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64 | reg = <0x0 0x100>; |
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65 | }; |
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66 | |||
67 | wdt: wdt@100 { |
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68 | compatible = "mediatek,mt7621-wdt"; |
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69 | reg = <0x100 0x100>; |
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70 | }; |
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71 | |||
72 | gpio@600 { |
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73 | #address-cells = <1>; |
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74 | #size-cells = <0>; |
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75 | |||
76 | compatible = "mtk,mt7621-gpio"; |
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77 | reg = <0x600 0x100>; |
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78 | |||
79 | gpio0: bank@0 { |
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80 | reg = <0>; |
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81 | compatible = "mtk,mt7621-gpio-bank"; |
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82 | gpio-controller; |
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83 | #gpio-cells = <2>; |
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84 | }; |
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85 | |||
86 | gpio1: bank@1 { |
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87 | reg = <1>; |
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88 | compatible = "mtk,mt7621-gpio-bank"; |
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89 | gpio-controller; |
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90 | #gpio-cells = <2>; |
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91 | }; |
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92 | |||
93 | gpio2: bank@2 { |
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94 | reg = <2>; |
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95 | compatible = "mtk,mt7621-gpio-bank"; |
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96 | gpio-controller; |
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97 | #gpio-cells = <2>; |
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98 | }; |
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99 | }; |
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100 | |||
101 | i2c: i2c@900 { |
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102 | compatible = "mediatek,mt7621-i2c"; |
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103 | reg = <0x900 0x100>; |
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104 | |||
105 | clocks = <&sysclock>; |
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106 | |||
107 | resets = <&rstctrl 16>; |
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108 | reset-names = "i2c"; |
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109 | |||
110 | #address-cells = <1>; |
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111 | #size-cells = <0>; |
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112 | |||
113 | status = "disabled"; |
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114 | |||
115 | pinctrl-names = "default"; |
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116 | pinctrl-0 = <&i2c_pins>; |
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117 | }; |
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118 | |||
119 | i2s: i2s@a00 { |
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120 | compatible = "mediatek,mt7621-i2s"; |
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121 | reg = <0xa00 0x100>; |
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122 | |||
123 | clocks = <&sysclock>; |
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124 | |||
125 | resets = <&rstctrl 17>; |
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126 | reset-names = "i2s"; |
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127 | |||
128 | interrupt-parent = <&gic>; |
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129 | interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>; |
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130 | |||
131 | txdma-req = <2>; |
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132 | rxdma-req = <3>; |
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133 | |||
134 | dmas = <&gdma 4>, |
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135 | <&gdma 6>; |
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136 | dma-names = "tx", "rx"; |
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137 | |||
138 | status = "disabled"; |
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139 | }; |
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140 | |||
141 | systick: systick@500 { |
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142 | compatible = "ralink,mt7621-systick", "ralink,cevt-systick"; |
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143 | reg = <0x500 0x10>; |
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144 | |||
145 | resets = <&rstctrl 28>; |
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146 | reset-names = "intc"; |
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147 | |||
148 | interrupt-parent = <&gic>; |
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149 | interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>; |
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150 | }; |
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151 | |||
152 | memc: memc@5000 { |
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153 | compatible = "mtk,mt7621-memc"; |
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154 | reg = <0x5000 0x1000>; |
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155 | }; |
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156 | |||
157 | cpc: cpc@1fbf0000 { |
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158 | compatible = "mtk,mt7621-cpc"; |
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159 | reg = <0x1fbf0000 0x8000>; |
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160 | }; |
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161 | |||
162 | mc: mc@1fbf8000 { |
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163 | compatible = "mtk,mt7621-mc"; |
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164 | reg = <0x1fbf8000 0x8000>; |
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165 | }; |
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166 | |||
167 | uartlite: uartlite@c00 { |
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168 | compatible = "ns16550a"; |
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169 | reg = <0xc00 0x100>; |
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170 | |||
171 | clock-frequency = <50000000>; |
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172 | |||
173 | interrupt-parent = <&gic>; |
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174 | interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; |
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175 | |||
176 | reg-shift = <2>; |
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177 | reg-io-width = <4>; |
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178 | no-loopback-test; |
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179 | }; |
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180 | |||
181 | uartlite2: uartlite2@d00 { |
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182 | compatible = "ns16550a"; |
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183 | reg = <0xd00 0x100>; |
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184 | |||
185 | clock-frequency = <50000000>; |
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186 | |||
187 | interrupt-parent = <&gic>; |
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188 | interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>; |
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189 | |||
190 | reg-shift = <2>; |
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191 | reg-io-width = <4>; |
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192 | |||
193 | pinctrl-names = "default"; |
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194 | pinctrl-0 = <&uart2_pins>; |
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195 | |||
196 | status = "disabled"; |
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197 | }; |
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198 | |||
199 | uartlite3: uartlite3@e00 { |
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200 | compatible = "ns16550a"; |
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201 | reg = <0xe00 0x100>; |
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202 | |||
203 | clock-frequency = <50000000>; |
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204 | |||
205 | interrupt-parent = <&gic>; |
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206 | interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>; |
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207 | |||
208 | reg-shift = <2>; |
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209 | reg-io-width = <4>; |
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210 | |||
211 | pinctrl-names = "default"; |
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212 | pinctrl-0 = <&uart3_pins>; |
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213 | |||
214 | status = "disabled"; |
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215 | }; |
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216 | |||
217 | spi0: spi@b00 { |
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218 | status = "disabled"; |
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219 | |||
220 | compatible = "ralink,mt7621-spi"; |
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221 | reg = <0xb00 0x100>; |
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222 | |||
223 | clocks = <&pll MT7621_CLK_BUS>; |
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224 | |||
225 | resets = <&rstctrl 18>; |
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226 | reset-names = "spi"; |
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227 | |||
228 | #address-cells = <1>; |
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229 | #size-cells = <0>; |
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230 | |||
231 | pinctrl-names = "default"; |
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232 | pinctrl-0 = <&spi_pins>; |
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233 | }; |
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234 | |||
235 | gdma: gdma@2800 { |
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236 | compatible = "ralink,rt3883-gdma"; |
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237 | reg = <0x2800 0x800>; |
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238 | |||
239 | resets = <&rstctrl 14>; |
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240 | reset-names = "dma"; |
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241 | |||
242 | interrupt-parent = <&gic>; |
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243 | interrupts = <0 13 4>; |
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244 | |||
245 | #dma-cells = <1>; |
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246 | #dma-channels = <16>; |
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247 | #dma-requests = <16>; |
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248 | |||
249 | status = "disabled"; |
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250 | }; |
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251 | |||
252 | hsdma: hsdma@7000 { |
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253 | compatible = "mediatek,mt7621-hsdma"; |
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254 | reg = <0x7000 0x1000>; |
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255 | |||
256 | resets = <&rstctrl 5>; |
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257 | reset-names = "hsdma"; |
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258 | |||
259 | interrupt-parent = <&gic>; |
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260 | interrupts = <0 11 4>; |
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261 | |||
262 | #dma-cells = <1>; |
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263 | #dma-channels = <1>; |
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264 | #dma-requests = <1>; |
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265 | |||
266 | status = "disabled"; |
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267 | }; |
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268 | }; |
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269 | |||
270 | pinctrl: pinctrl { |
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271 | compatible = "ralink,rt2880-pinmux"; |
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272 | pinctrl-names = "default"; |
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273 | pinctrl-0 = <&state_default>; |
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274 | |||
275 | state_default: pinctrl0 { |
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276 | }; |
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277 | |||
278 | i2c_pins: i2c_pins { |
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279 | i2c_pins { |
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280 | ralink,group = "i2c"; |
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281 | ralink,function = "i2c"; |
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282 | }; |
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283 | }; |
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284 | |||
285 | spi_pins: spi_pins { |
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286 | spi_pins { |
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287 | ralink,group = "spi"; |
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288 | ralink,function = "spi"; |
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289 | }; |
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290 | }; |
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291 | |||
292 | uart1_pins: uart1 { |
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293 | uart1 { |
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294 | ralink,group = "uart1"; |
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295 | ralink,function = "uart1"; |
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296 | }; |
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297 | }; |
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298 | |||
299 | uart2_pins: uart2 { |
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300 | uart2 { |
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301 | ralink,group = "uart2"; |
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302 | ralink,function = "uart2"; |
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303 | }; |
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304 | }; |
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305 | |||
306 | uart3_pins: uart3 { |
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307 | uart3 { |
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308 | ralink,group = "uart3"; |
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309 | ralink,function = "uart3"; |
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310 | }; |
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311 | }; |
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312 | |||
313 | rgmii1_pins: rgmii1 { |
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314 | rgmii1 { |
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315 | ralink,group = "rgmii1"; |
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316 | ralink,function = "rgmii1"; |
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317 | }; |
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318 | }; |
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319 | |||
320 | rgmii2_pins: rgmii2 { |
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321 | rgmii2 { |
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322 | ralink,group = "rgmii2"; |
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323 | ralink,function = "rgmii2"; |
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324 | }; |
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325 | }; |
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326 | |||
327 | mdio_pins: mdio { |
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328 | mdio { |
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329 | ralink,group = "mdio"; |
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330 | ralink,function = "mdio"; |
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331 | }; |
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332 | }; |
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333 | |||
334 | pcie_pins: pcie { |
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335 | pcie { |
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336 | ralink,group = "pcie"; |
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337 | ralink,function = "pcie rst"; |
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338 | }; |
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339 | }; |
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340 | |||
341 | nand_pins: nand { |
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342 | spi-nand { |
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343 | ralink,group = "spi"; |
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344 | ralink,function = "nand1"; |
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345 | }; |
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346 | |||
347 | sdhci-nand { |
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348 | ralink,group = "sdhci"; |
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349 | ralink,function = "nand2"; |
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350 | }; |
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351 | }; |
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352 | |||
353 | sdhci_pins: sdhci { |
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354 | sdhci { |
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355 | ralink,group = "sdhci"; |
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356 | ralink,function = "sdhci"; |
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357 | }; |
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358 | }; |
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359 | }; |
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360 | |||
361 | rstctrl: rstctrl { |
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362 | compatible = "ralink,rt2880-reset"; |
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363 | #reset-cells = <1>; |
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364 | }; |
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365 | |||
366 | clkctrl: clkctrl { |
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367 | compatible = "ralink,rt2880-clock"; |
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368 | #clock-cells = <1>; |
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369 | }; |
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370 | |||
371 | sdhci: sdhci@1E130000 { |
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372 | status = "disabled"; |
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373 | |||
374 | compatible = "ralink,mt7620-sdhci"; |
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375 | reg = <0x1E130000 0x4000>; |
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376 | |||
377 | interrupt-parent = <&gic>; |
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378 | interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; |
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379 | |||
380 | pinctrl-names = "default"; |
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381 | pinctrl-0 = <&sdhci_pins>; |
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382 | }; |
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383 | |||
384 | xhci: xhci@1E1C0000 { |
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385 | #address-cells = <1>; |
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386 | #size-cells = <0>; |
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387 | status = "okay"; |
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388 | |||
389 | compatible = "mediatek,mt8173-xhci"; |
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390 | reg = <0x1e1c0000 0x1000 |
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391 | 0x1e1d0700 0x0100>; |
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392 | reg-names = "mac", "ippc"; |
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393 | |||
394 | clocks = <&sysclock>; |
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395 | clock-names = "sys_ck"; |
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396 | |||
397 | interrupt-parent = <&gic>; |
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398 | interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; |
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399 | |||
400 | /* |
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401 | * Port 1 of both hubs is one usb slot and referenced here. |
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402 | * The binding doesn't allow to address individual hubs. |
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403 | * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci. |
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404 | */ |
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405 | xhci_ehci_port1: port@1 { |
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406 | reg = <1>; |
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407 | #trigger-source-cells = <0>; |
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408 | }; |
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409 | |||
410 | /* |
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411 | * Only the second usb hub has a second port. That port serves |
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412 | * ehci and ohci. |
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413 | */ |
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414 | ehci_port2: port@2 { |
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415 | reg = <2>; |
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416 | #trigger-source-cells = <0>; |
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417 | }; |
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418 | }; |
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419 | |||
420 | gic: interrupt-controller@1fbc0000 { |
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421 | compatible = "mti,gic"; |
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422 | reg = <0x1fbc0000 0x2000>; |
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423 | |||
424 | interrupt-controller; |
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425 | #interrupt-cells = <3>; |
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426 | |||
427 | mti,reserved-cpu-vectors = <7>; |
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428 | |||
429 | timer { |
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430 | compatible = "mti,gic-timer"; |
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431 | interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; |
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432 | clocks = <&pll MT7621_CLK_CPU>; |
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433 | }; |
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434 | }; |
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435 | |||
436 | nand: nand@1e003000 { |
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437 | status = "disabled"; |
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438 | |||
439 | compatible = "mtk,mt7621-nand"; |
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440 | bank-width = <2>; |
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441 | reg = <0x1e003000 0x800 |
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442 | 0x1e003800 0x800>; |
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443 | }; |
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444 | |||
445 | ethernet: ethernet@1e100000 { |
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446 | compatible = "mediatek,mt7621-eth"; |
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447 | reg = <0x1e100000 0x10000>; |
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448 | |||
449 | #address-cells = <1>; |
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450 | #size-cells = <1>; |
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451 | |||
452 | resets = <&rstctrl 6 &rstctrl 23>; |
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453 | reset-names = "fe", "eth"; |
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454 | |||
455 | interrupt-parent = <&gic>; |
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456 | interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; |
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457 | |||
458 | mediatek,switch = <&gsw>; |
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459 | |||
460 | mdio-bus { |
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461 | #address-cells = <1>; |
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462 | #size-cells = <0>; |
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463 | |||
464 | phy1f: ethernet-phy@1f { |
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465 | reg = <0x1f>; |
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466 | phy-mode = "rgmii"; |
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467 | }; |
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468 | }; |
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469 | |||
470 | hnat: hnat@0 { |
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471 | compatible = "mediatek,mt7623-hnat"; |
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472 | reg = <0 0x10000>; |
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473 | mtketh-ppd = "eth0"; |
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474 | mtketh-lan = "eth0"; |
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475 | mtketh-wan = "eth0"; |
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476 | resets = <&rstctrl 0>; |
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477 | reset-names = "mtketh"; |
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478 | }; |
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479 | }; |
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480 | |||
481 | gsw: gsw@1e110000 { |
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482 | compatible = "mediatek,mt7621-gsw"; |
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483 | reg = <0x1e110000 0x8000>; |
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484 | interrupt-parent = <&gic>; |
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485 | interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; |
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486 | }; |
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487 | |||
488 | pcie: pcie@1e140000 { |
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489 | compatible = "mediatek,mt7621-pci"; |
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490 | reg = <0x1e140000 0x100 |
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491 | 0x1e142000 0x100>; |
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492 | |||
493 | #address-cells = <3>; |
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494 | #size-cells = <2>; |
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495 | |||
496 | pinctrl-names = "default"; |
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497 | pinctrl-0 = <&pcie_pins>; |
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498 | |||
499 | device_type = "pci"; |
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500 | |||
501 | bus-range = <0 255>; |
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502 | ranges = < |
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503 | 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ |
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504 | 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ |
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505 | >; |
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506 | |||
507 | interrupt-parent = <&gic>; |
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508 | interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH |
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509 | GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH |
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510 | GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; |
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511 | |||
512 | status = "disabled"; |
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513 | |||
514 | resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; |
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515 | reset-names = "pcie0", "pcie1", "pcie2"; |
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516 | clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; |
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517 | clock-names = "pcie0", "pcie1", "pcie2"; |
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518 | |||
519 | pcie0: pcie@0,0 { |
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520 | reg = <0x0000 0 0 0 0>; |
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521 | |||
522 | #address-cells = <3>; |
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523 | #size-cells = <2>; |
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524 | |||
525 | ranges; |
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526 | }; |
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527 | |||
528 | pcie1: pcie@1,0 { |
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529 | reg = <0x0800 0 0 0 0>; |
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530 | |||
531 | #address-cells = <3>; |
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532 | #size-cells = <2>; |
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533 | |||
534 | ranges; |
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535 | }; |
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536 | |||
537 | pcie2: pcie@2,0 { |
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538 | reg = <0x1000 0 0 0 0>; |
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539 | |||
540 | #address-cells = <3>; |
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541 | #size-cells = <2>; |
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542 | |||
543 | ranges; |
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544 | }; |
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545 | }; |
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546 | }; |