OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | /dts-v1/; |
2 | |||
3 | #include "mt7620a.dtsi" |
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4 | |||
5 | #include <dt-bindings/gpio/gpio.h> |
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6 | #include <dt-bindings/input/input.h> |
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7 | |||
8 | / { |
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9 | compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; |
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10 | model = "Ralink MT7620a V22SG High Power evaluation board"; |
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11 | |||
12 | keys { |
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13 | compatible = "gpio-keys-polled"; |
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14 | poll-interval = <20>; |
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15 | |||
16 | reset { |
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17 | label = "reset"; |
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18 | gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; |
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19 | linux,code = <KEY_RESTART>; |
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20 | }; |
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21 | |||
22 | aoss { |
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23 | label = "aoss"; |
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24 | gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; |
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25 | linux,code = <KEY_WPS_BUTTON>; |
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26 | }; |
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27 | }; |
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28 | |||
29 | nand { |
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30 | compatible = "mtk,mt7620-nand"; |
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31 | |||
32 | partitions { |
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33 | compatible = "fixed-partitions"; |
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34 | #address-cells = <1>; |
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35 | #size-cells = <1>; |
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36 | |||
37 | partition@0 { |
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38 | label = "u-boot"; |
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39 | reg = <0x0 0x40000>; |
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40 | read-only; |
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41 | }; |
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42 | |||
43 | partition@40000 { |
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44 | label = "u-boot-env"; |
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45 | reg = <0x40000 0x20000>; |
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46 | read-only; |
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47 | }; |
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48 | |||
49 | factory: partition@60000 { |
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50 | label = "factory"; |
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51 | reg = <0x60000 0x20000>; |
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52 | read-only; |
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53 | }; |
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54 | |||
55 | partition@80000 { |
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56 | compatible = "denx,uimage"; |
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57 | label = "firmware"; |
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58 | reg = <0x80000 0x7f80000>; |
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59 | }; |
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60 | }; |
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61 | }; |
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62 | }; |
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63 | |||
64 | &pinctrl { |
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65 | state_default: pinctrl0 { |
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66 | gpio { |
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67 | ralink,group = "i2c", "uartf", "spi"; |
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68 | ralink,function = "gpio"; |
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69 | }; |
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70 | }; |
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71 | }; |
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72 | |||
73 | ðernet { |
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74 | status = "okay"; |
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75 | pinctrl-names = "default"; |
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76 | pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; |
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77 | mediatek,portmap = "llllw"; |
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78 | |||
79 | port@4 { |
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80 | status = "okay"; |
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81 | phy-handle = <&phy4>; |
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82 | phy-mode = "rgmii"; |
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83 | }; |
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84 | |||
85 | port@5 { |
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86 | status = "okay"; |
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87 | phy-handle = <&phy5>; |
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88 | phy-mode = "rgmii"; |
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89 | }; |
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90 | |||
91 | mdio-bus { |
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92 | status = "okay"; |
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93 | |||
94 | phy4: ethernet-phy@4 { |
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95 | reg = <4>; |
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96 | phy-mode = "rgmii"; |
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97 | }; |
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98 | |||
99 | phy5: ethernet-phy@5 { |
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100 | reg = <5>; |
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101 | phy-mode = "rgmii"; |
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102 | }; |
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103 | }; |
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104 | }; |
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105 | |||
106 | &gsw { |
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107 | mediatek,port4 = "gmac"; |
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108 | }; |
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109 | |||
110 | &pcie { |
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111 | status = "okay"; |
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112 | }; |
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113 | |||
114 | &ehci { |
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115 | status = "okay"; |
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116 | }; |
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117 | |||
118 | &ohci { |
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119 | status = "okay"; |
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120 | }; |