OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /dts-v1/; |
2 | |||
3 | #include "mt7620a.dtsi" |
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4 | |||
5 | #include <dt-bindings/gpio/gpio.h> |
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6 | #include <dt-bindings/input/input.h> |
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7 | |||
8 | / { |
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9 | compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; |
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10 | model = "Ralink MT7620a + MT7610e evaluation board"; |
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11 | |||
3 | office | 12 | gpio-keys-polled { |
1 | office | 13 | compatible = "gpio-keys"; |
3 | office | 14 | #address-cells = <1>; |
15 | #size-cells = <0>; |
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1 | office | 16 | poll-interval = <20>; |
17 | |||
18 | s2 { |
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19 | label = "S2"; |
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20 | gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; |
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21 | linux,code = <BTN_0>; |
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22 | }; |
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23 | |||
24 | s3 { |
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25 | label = "S3"; |
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26 | gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; |
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27 | linux,code = <BTN_1>; |
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28 | }; |
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29 | }; |
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30 | }; |
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31 | |||
32 | &spi0 { |
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33 | status = "okay"; |
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34 | |||
35 | m25p80@0 { |
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3 | office | 36 | #address-cells = <1>; |
37 | #size-cells = <1>; |
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1 | office | 38 | compatible = "jedec,spi-nor"; |
39 | reg = <0>; |
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40 | spi-max-frequency = <10000000>; |
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41 | |||
3 | office | 42 | partition@0 { |
43 | label = "u-boot"; |
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44 | reg = <0x0 0x30000>; |
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45 | read-only; |
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46 | }; |
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1 | office | 47 | |
3 | office | 48 | partition@30000 { |
49 | label = "u-boot-env"; |
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50 | reg = <0x30000 0x10000>; |
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51 | read-only; |
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52 | }; |
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1 | office | 53 | |
3 | office | 54 | factory: partition@40000 { |
55 | label = "factory"; |
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56 | reg = <0x40000 0x10000>; |
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57 | read-only; |
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58 | }; |
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1 | office | 59 | |
3 | office | 60 | partition@50000 { |
61 | label = "firmware"; |
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62 | reg = <0x50000 0x7b0000>; |
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1 | office | 63 | }; |
64 | }; |
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65 | }; |
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66 | |||
67 | &pinctrl { |
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68 | state_default: pinctrl0 { |
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69 | gpio { |
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70 | ralink,group = "i2c", "uartf"; |
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71 | ralink,function = "gpio"; |
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72 | }; |
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73 | }; |
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74 | }; |
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75 | |||
76 | ðernet { |
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77 | status = "okay"; |
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78 | pinctrl-names = "default"; |
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79 | pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; |
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80 | mediatek,portmap = "llllw"; |
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81 | |||
82 | port@4 { |
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83 | status = "okay"; |
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84 | phy-mode = "rgmii"; |
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85 | phy-handle = <&phy4>; |
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86 | }; |
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87 | |||
88 | port@5 { |
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89 | status = "okay"; |
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90 | phy-mode = "rgmii"; |
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91 | phy-handle = <&phy5>; |
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92 | }; |
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93 | |||
94 | mdio-bus { |
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95 | status = "okay"; |
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96 | |||
97 | phy4: ethernet-phy@4 { |
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98 | reg = <4>; |
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99 | phy-mode = "rgmii"; |
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100 | }; |
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101 | |||
102 | phy5: ethernet-phy@5 { |
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103 | reg = <5>; |
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104 | phy-mode = "rgmii"; |
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105 | }; |
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106 | }; |
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107 | }; |
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108 | |||
109 | &gsw { |
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110 | mediatek,port4 = "gmac"; |
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111 | }; |
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112 | |||
113 | &sdhci { |
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114 | status = "okay"; |
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115 | }; |
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116 | |||
117 | &pcie { |
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118 | status = "okay"; |
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119 | }; |
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120 | |||
121 | &ehci { |
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122 | status = "okay"; |
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123 | }; |
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124 | |||
125 | &ohci { |
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126 | status = "okay"; |
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127 | }; |