OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /dts-v1/; |
2 | |||
3 | #include "mt7620a.dtsi" |
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4 | |||
5 | #include <dt-bindings/gpio/gpio.h> |
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6 | #include <dt-bindings/input/input.h> |
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7 | |||
8 | / { |
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9 | compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; |
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10 | model = "Ralink MT7620a + MT7610e evaluation board"; |
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11 | |||
12 | keys { |
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13 | compatible = "gpio-keys"; |
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14 | poll-interval = <20>; |
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15 | |||
16 | s2 { |
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17 | label = "S2"; |
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18 | gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; |
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19 | linux,code = <BTN_0>; |
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20 | }; |
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21 | |||
22 | s3 { |
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23 | label = "S3"; |
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24 | gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; |
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25 | linux,code = <BTN_1>; |
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26 | }; |
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27 | }; |
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28 | }; |
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29 | |||
30 | &spi0 { |
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31 | status = "okay"; |
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32 | |||
33 | m25p80@0 { |
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34 | compatible = "jedec,spi-nor"; |
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35 | reg = <0>; |
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36 | spi-max-frequency = <10000000>; |
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37 | |||
38 | partitions { |
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39 | compatible = "fixed-partitions"; |
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40 | #address-cells = <1>; |
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41 | #size-cells = <1>; |
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42 | |||
43 | partition@0 { |
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44 | label = "u-boot"; |
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45 | reg = <0x0 0x30000>; |
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46 | read-only; |
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47 | }; |
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48 | |||
49 | partition@30000 { |
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50 | label = "u-boot-env"; |
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51 | reg = <0x30000 0x10000>; |
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52 | read-only; |
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53 | }; |
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54 | |||
55 | factory: partition@40000 { |
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56 | label = "factory"; |
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57 | reg = <0x40000 0x10000>; |
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58 | read-only; |
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59 | }; |
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60 | |||
61 | partition@50000 { |
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62 | compatible = "denx,uimage"; |
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63 | label = "firmware"; |
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64 | reg = <0x50000 0x7b0000>; |
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65 | }; |
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66 | }; |
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67 | }; |
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68 | }; |
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69 | |||
70 | &pinctrl { |
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71 | state_default: pinctrl0 { |
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72 | gpio { |
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73 | ralink,group = "i2c", "uartf"; |
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74 | ralink,function = "gpio"; |
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75 | }; |
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76 | }; |
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77 | }; |
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78 | |||
79 | ðernet { |
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80 | status = "okay"; |
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81 | pinctrl-names = "default"; |
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82 | pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; |
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83 | mediatek,portmap = "llllw"; |
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84 | |||
85 | port@4 { |
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86 | status = "okay"; |
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87 | phy-mode = "rgmii"; |
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88 | phy-handle = <&phy4>; |
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89 | }; |
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90 | |||
91 | port@5 { |
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92 | status = "okay"; |
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93 | phy-mode = "rgmii"; |
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94 | phy-handle = <&phy5>; |
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95 | }; |
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96 | |||
97 | mdio-bus { |
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98 | status = "okay"; |
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99 | |||
100 | phy4: ethernet-phy@4 { |
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101 | reg = <4>; |
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102 | phy-mode = "rgmii"; |
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103 | }; |
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104 | |||
105 | phy5: ethernet-phy@5 { |
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106 | reg = <5>; |
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107 | phy-mode = "rgmii"; |
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108 | }; |
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109 | }; |
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110 | }; |
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111 | |||
112 | &gsw { |
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113 | mediatek,port4 = "gmac"; |
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114 | }; |
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115 | |||
116 | &sdhci { |
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117 | status = "okay"; |
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118 | }; |
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119 | |||
120 | &pcie { |
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121 | status = "okay"; |
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122 | }; |
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123 | |||
124 | &ehci { |
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125 | status = "okay"; |
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126 | }; |
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127 | |||
128 | &ohci { |
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129 | status = "okay"; |
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130 | }; |