OpenWrt – Blame information for rev 3
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1 | office | 1 | From patchwork Thu Sep 28 12:58:34 2017 |
2 | Content-Type: text/plain; charset="utf-8" |
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3 | MIME-Version: 1.0 |
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4 | Content-Transfer-Encoding: 7bit |
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5 | Subject: [v2, |
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6 | 3/7] PCI: aardvark: set host and device to the same MAX payload size |
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7 | X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
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8 | X-Patchwork-Id: 819587 |
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9 | Message-Id: <20170928125838.11887-4-thomas.petazzoni@free-electrons.com> |
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10 | To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org |
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11 | Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>, |
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12 | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement |
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13 | <gregory.clement@free-electrons.com>, |
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14 | Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>, |
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15 | Yehuda Yitschak <yehuday@marvell.com>, |
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16 | linux-arm-kernel@lists.infradead.org, Antoine Tenart |
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17 | <antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?= |
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18 | <miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>, |
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19 | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
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20 | Date: Thu, 28 Sep 2017 14:58:34 +0200 |
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21 | From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
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22 | List-Id: <linux-pci.vger.kernel.org> |
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23 | |||
24 | From: Victor Gu <xigu@marvell.com> |
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25 | |||
26 | Since the Aardvark does not implement a PCIe root bus, the Linux PCIe |
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27 | subsystem will not align the MAX payload size between the host and the |
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28 | device. This patch ensures that the host and device have the same MAX |
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29 | payload size, fixing a number of problems with various PCIe devices. |
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30 | |||
31 | This is part of fixing bug |
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32 | https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was |
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33 | reported as the user to be important to get a Intel 7260 mini-PCIe |
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34 | WiFi card working. |
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35 | |||
36 | Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") |
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37 | Signed-off-by: Victor Gu <xigu@marvell.com> |
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38 | Reviewed-by: Evan Wang <xswang@marvell.com> |
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39 | Reviewed-by: Nadav Haklai <nadavh@marvell.com> |
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40 | [Thomas: tweak commit log.] |
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41 | Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
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42 | --- |
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43 | drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++- |
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44 | 1 file changed, 59 insertions(+), 1 deletion(-) |
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45 | |||
46 | --- a/drivers/pci/host/pci-aardvark.c |
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47 | +++ b/drivers/pci/host/pci-aardvark.c |
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48 | @@ -30,9 +30,11 @@ |
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49 | #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 |
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50 | #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) |
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51 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 |
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52 | +#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2 |
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53 | #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) |
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54 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 |
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55 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 |
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56 | +#define PCIE_CORE_MPS_UNIT_BYTE 128 |
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57 | #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 |
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58 | #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) |
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59 | #define PCIE_CORE_LINK_TRAINING BIT(5) |
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60 | @@ -297,7 +299,8 @@ static void advk_pcie_setup_hw(struct ad |
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61 | |||
62 | /* Set PCIe Device Control and Status 1 PF0 register */ |
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63 | reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | |
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64 | - (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | |
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65 | + (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << |
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66 | + PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | |
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67 | PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | |
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68 | (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << |
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69 | PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); |
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70 | @@ -886,6 +889,58 @@ out_release_res: |
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71 | return err; |
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72 | } |
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73 | |||
74 | +static int advk_pcie_find_smpss(struct pci_dev *dev, void *data) |
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75 | +{ |
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76 | + u8 *smpss = data; |
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77 | + |
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78 | + if (!dev) |
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79 | + return 0; |
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80 | + |
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81 | + if (!pci_is_pcie(dev)) |
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82 | + return 0; |
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83 | + |
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84 | + if (*smpss > dev->pcie_mpss) |
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85 | + *smpss = dev->pcie_mpss; |
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86 | + |
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87 | + return 0; |
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88 | +} |
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89 | + |
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90 | +static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data) |
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91 | +{ |
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92 | + int mps; |
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93 | + |
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94 | + if (!dev) |
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95 | + return 0; |
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96 | + |
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97 | + if (!pci_is_pcie(dev)) |
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98 | + return 0; |
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99 | + |
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100 | + mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data; |
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101 | + pcie_set_mps(dev, mps); |
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102 | + |
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103 | + return 0; |
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104 | +} |
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105 | + |
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106 | +static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie) |
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107 | +{ |
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108 | + u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ; |
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109 | + u32 reg; |
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110 | + |
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111 | + /* Find the minimal supported MAX payload size */ |
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112 | + advk_pcie_find_smpss(bus->self, &smpss); |
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113 | + pci_walk_bus(bus, advk_pcie_find_smpss, &smpss); |
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114 | + |
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115 | + /* Configure RC MAX payload size */ |
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116 | + reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG); |
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117 | + reg &= ~PCI_EXP_DEVCTL_PAYLOAD; |
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118 | + reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT; |
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119 | + advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); |
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120 | + |
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121 | + /* Configure device MAX payload size */ |
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122 | + advk_pcie_bus_configure_mps(bus->self, &smpss); |
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123 | + pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss); |
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124 | +} |
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125 | + |
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126 | static int advk_pcie_probe(struct platform_device *pdev) |
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127 | { |
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128 | struct device *dev = &pdev->dev; |
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3 | office | 129 | @@ -959,6 +1014,9 @@ static int advk_pcie_probe(struct platfo |
1 | office | 130 | list_for_each_entry(child, &bus->children, node) |
131 | pcie_bus_configure_settings(child); |
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132 | |||
133 | + /* Configure the MAX pay load size */ |
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134 | + advk_pcie_configure_mps(bus, pcie); |
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135 | + |
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136 | pci_bus_add_devices(bus); |
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137 | return 0; |
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138 | } |