OpenWrt – Blame information for rev 2

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Rev Author Line No. Line
1 office 1 From 788d269aee4c612d5cd97b896ea5d22f19137097 Mon Sep 17 00:00:00 2001
2 From: Chaotian Jing <chaotian.jing@mediatek.com>
3 Date: Mon, 16 Oct 2017 09:46:34 +0800
4 Subject: [PATCH 155/224] mmc: mediatek: add busy_check support
5  
6 bit7 of PATCH_BIT1 has different meaning in new design, to
7 compatible with previous platform, clear this bit in new
8 platform.
9  
10 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
11 Tested-by: Sean Wang <sean.wang@mediatek.com>
12 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
13 ---
14 drivers/mmc/host/mtk-sd.c | 7 +++++++
15 1 file changed, 7 insertions(+)
16  
17 --- a/drivers/mmc/host/mtk-sd.c
18 +++ b/drivers/mmc/host/mtk-sd.c
19 @@ -316,6 +316,7 @@ struct mtk_mmc_compatible {
20 u32 pad_tune_reg;
21 bool async_fifo;
22 bool data_tune;
23 + bool busy_check;
24 };
25  
26 struct msdc_tune_para {
27 @@ -380,6 +381,7 @@ static const struct mtk_mmc_compatible m
28 .pad_tune_reg = MSDC_PAD_TUNE,
29 .async_fifo = false,
30 .data_tune = false,
31 + .busy_check = false,
32 };
33  
34 static const struct mtk_mmc_compatible mt8173_compat = {
35 @@ -388,6 +390,7 @@ static const struct mtk_mmc_compatible m
36 .pad_tune_reg = MSDC_PAD_TUNE,
37 .async_fifo = false,
38 .data_tune = false,
39 + .busy_check = false,
40 };
41  
42 static const struct mtk_mmc_compatible mt2701_compat = {
43 @@ -396,6 +399,7 @@ static const struct mtk_mmc_compatible m
44 .pad_tune_reg = MSDC_PAD_TUNE0,
45 .async_fifo = true,
46 .data_tune = true,
47 + .busy_check = false,
48 };
49  
50 static const struct mtk_mmc_compatible mt2712_compat = {
51 @@ -404,6 +408,7 @@ static const struct mtk_mmc_compatible m
52 .pad_tune_reg = MSDC_PAD_TUNE0,
53 .async_fifo = true,
54 .data_tune = true,
55 + .busy_check = true,
56 };
57  
58 static const struct of_device_id msdc_of_ids[] = {
59 @@ -1275,6 +1280,8 @@ static void msdc_init_hw(struct msdc_hos
60 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
61 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
62 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
63 + if (host->dev_comp->busy_check)
64 + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
65 if (host->dev_comp->async_fifo) {
66 sdr_set_field(host->base + MSDC_PATCH_BIT2,
67 MSDC_PB2_RESPWAIT, 3);